Re: gEDA-user: Power relay question
Bad things: - your friends may make fun of you for not using the latest programmable solution ;) Hey, I think that part is the most cool :) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Power relay question
On 07/28/2011 05:52 PM, Rob Butts wrote: This is a dumb question but I'm having a mental block. I have a 12 volt dc motor that I want to run from the push of a momentary pushbutton which will run until a limit switch gets hit. Digikey has a power latching relay PB1088-ND (cheap) that I can't tell if it actually latches once energized. (I attached the relay document) Is relays and switches even the best/cheapest solution? Suggestions? Power: quantity of 2 12 volt batteries available Input: momenary 12 volt pushbutton #1 Requirements: 12 volt dc motor #1 12 volt dc motor #2 The application: Stage 1: momentary signal from pushbutton #1 starts motor #1 that runs until a limit switch is hit triggering stage 2 Stage 2: motor #2 runs until another limit switch is hit and remains stable Stage 3: momentary signal from pushbutton #1 reverses the polarity of power to the motor #2 running it until back to it's start position and triggering stage 4 Stage 4: reverse of the ploarity of the power to motor #1 running it until it is back to the start position Thanks for any suggestions if non I'll just wing it. I haven't thought this through, but what about a triac or some combo of triac and mosfet? gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
On 06/24/2011 07:10 AM, myken wrote: This is strange in my simulation the attached circuit works fine. In real life it kinda works but the signals are distorted like you can see. I think that has something to do with the fact we used a pulse transformer to try the circuit. If we disconnect Vx the signals stay the same, so the distortion is in the transformer. If you say it doesn't work then why doesn't it work? On 22/06/11 22:39, Andy Fierman wrote: One thing that seems to be a problem, is that you've created a tuned circuit on the primary. L-R-C, series resonant at about 23 kHz, which seems like that's what you were trying to do. The Q is very high, X/R, and R is 0.25 per data sheet. So, you the thing peaks at precisely your source frequency! In my simulation, the output voltage is *huge*, the transformer current is equally high. Try your simulation in the frequency domain as well as the time domain. Regarding your experimental setup - you are probably saturating your core. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
On 06/22/2011 04:39 PM, Andy Fierman wrote: Vcc and Vss are still sensitive to load. So if the design requires both Vss and Vee be equal and opposite, then it needs regulation - zener, for example. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
On 06/16/2011 02:30 PM, myken wrote: Hello all, I would appreciate some expert advice. Are you trying to make a low current power supply? I agree with DJ - the unequal loading on + and - cycle will average to something other than zero (unequal capacitors, unequal diodes, etc) If Vx must always be average zero - you'll need to do something else. If you can handle a little voltage drop, don't care what happens to Vx, and don't mind adding a few parts, make a cheapo regulator with a zener and BJT? (Or maybe use TL31 instead of zener) What about a small transformer, one winding on primary, center tapped on secondary. Add a diode and a cap for each leg - and there you go! Anyway, there's lots of ways to do this. If regulated output is what you want, a little more work is required. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: Track routing strategies and tips
The schematic should be as readable as possible. Clearly you do not work where I do :) (or as some folks say there you go, making sense again) Preferred signal direction is left to right, top to bottom. Me too, whenever possible. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb: Track routing strategies and tips
Colin D Bennett wrote: As a rather inexperienced PCB designer, I find that I have to throw away two or three layouts until I get one that is usable--and still not entirely satisfactory. I always end up with such a mess of traces that I know I need better organization and a method to the madness. But I am a newb with little knowledge so I fall back on trial-and-error. I am also new to routing my own stuff but have a bunch of experience telling others how to do it for me (day job ;) On a prior job, the layout house did all auto-routes. They'd start several jobs with different router restrictions, allow them to route for a while, then pick one, and optimize it - probably by hand. Yes, starting over is common. Kai-Martin posted that placement is more important than routing. I'd say they are equally important. The best layout guy in the world can't fix a lousy placement. Bogus layout guys throw more layers at the problem. So yeah, take the time to plan it out before routing. Does anyone have any tips on how to plan a layout for easy and clean track routing? In particular for 2-layer boards. No substitute for experience here. But, partitioning the design by type may help : analog, digital, low-speed, high-speed. Try to think beyond blindly connecting the parts. Sometimes swapping gates, adding parts or other strategies become clear as you route. This is a huge benefit when you route your own board. Layout guys just connect the pieces together. One strategy that I have seen and recently tried is to use the top layer for all horizontal trace runs and the bottom layer for all vertical trace runs, or vice-versa. 2-layer is tough. You also have to account for power and ground. The parts themselves also crowd routing area. 2-layer is not particularly suitable for high-speed anything. Seems good for power supply design, and some audio work (I've seen a lot of audio ref boards on 2 layer). You can make good designs with 2-layer, just is more work. Cost difference to 4-layer is not bad. Yes X-Y routing is the way to go to avoid blocking. Works great for digital stuff. Do you ever use the pcb autorouter or do you always route by hand? I have yet to make the auto router work - but haven't really tried very hard. Hand routing is my preference but it takes longer. Do you ever study other people's PCB designs to learn from them? Yeah, a lot. You will find good and bad. There's a whole world of opinion out there - and you know what they say about opinions :) SI-LIST is a great place to exchange ideas on layout. Several industry experts frequently post. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OFF: capacitors for RF power amplifier
Kovacs Levente wrote: I'm currently designing a power amplifier for the HF (3-30MHz) radio band. I am selecting capacitors for the low pass harmonic filter bank at the output. My question is what kind of capacitors should I use? I apply not more then 100V of say 30MHz maximum. My best bet is to use X7R capacitors with as much DC voltage rating as I can get. I don't know if there's any connection between the DC and AC losses. Thanks, Levente I also would recommend the plastic types. Wima makes nice ones but there are others. C0G/NP0 good too, as already pointed out. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OFF: capacitors for RF power amplifier
quick link to Wima tech info: http://www.wima.de/EN/technicalinformation.htm One really nice thing about plastic film caps is that they fail open. Ceramic tends to fail short - which can sometimes ruin your day :) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: place to buy SMPS transformers?
yamazakir2 wrote: Anybody know of a source, other than digikey, that sells prefabbed prewound SMPS transformers? Try coilcraft : http://coilcraft.com/prod_pwr.cfm ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: High Temperature Connector
John Luciani wrote: I am looking for a low profile wire to board connector - either two contacts 5A per contact or four contacts 2.5A per contact. I need a temperature rating of at least 110degC (preferable 120degC). UL recognized is required. Being able to remove the wires would be nice but is not a requirement. We have been able to find 105degC rated connectors but nothing higher yet. Take a look at omnetics connectors. Where I work, we routinely run them at 175C or more. They are expensive though. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Soldering iron tip turns black
Rob Butts wrote: I asked a question a couple of days ago about soldering small smt components. Kaimartin posted a video of someone soldering smt components [1]http://www.youtube.com/watch?v=wQXhny3R7lk In the video the tip to the soldering iron is a shiny silver and you can see that the solder sticks to the tip. At work, I use SN96 lead-free solder. Our irons are routinely set to 800F. These days we use Hakko irons, very nice stuff, and the iron turns off when it's in the cradle. Heat up is really quick too. Tips last me a very long time. Prior to this, we used Weller fire-starters. Sometimes the tips would turn black after a few minutes and there was no amount of cleaning, tinning or whatever that could save them. I suppose some non-brand tips are not so good - but generally they all croaked after just a short amount of time. Although I like the sponges, sometimes people use a steel wool pad instead. I've seen pretty good results with that. The best way to keep the tip clean - turn off the iron when not in use. Keep the temperature lower, if possible. I too have heard about globbing solder onto the tip when not in use, but have not tried it. best luck to you :) gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: OT: Gilbert Cell
Has anyone worked with Gilbert Cells? I'm having a lot of trouble with one from ON Semi, MC1496, formerly Motorola's part, I think. The thing is configured as a product detector. There's 2 input frequencies and they both mix down to 5 kHz. That part works well. But, the chip just happens to oscillate at 5 kHz all by itself even without the local oscillator running. Go figure. There's also a very slow moving, 400 Hz or so, modulating the 5 kHz. I cannot for the life of me, figure out where it's coming from or how to get rid of it. I appreciate any help. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: pcb outline clarification
My design creates an outline layer. The rectangle the represents the outline of my board is about 11 X 11. The drawing area is about 20 X 14. In the fab.gbr layer, there is a note at the very bottom stating Board outline is the centerline of this 10 mil rectangle - 0,0 to 2,14000 mils. Is that going to confuse the PCB manufacturer? I want them to cut along the lines on the outline layer, not the fab layer. thanks ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb outline clarification
DJ Delorie wrote: If you do the outline right, PCB should print Board Outline is the centerline of this path on the fab layer. I can peek at your .pcb if you want to send me a copy. Thanks for the offer! I see what was wrong, though. My outline layer was labeled Outline. Changing it to all lower case fixed it. Now the output is precisely as you said. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: silkscreen found flag set
This seems like a bug - when I place some silkscreen on the component side (not sure about the solder side) PCB sets a flag found. This makes the silkscreen show up highlighted. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How to connect pads to anything?
Markus Hitter wrote: Instead I even get DRC errors stating the track and the pad are too close *sigh* Maybe your design rules are prohibiting making the connection? You could try disabling the auto enforce drc clearance - look under the settings menu selections. If that works out, you may have to change your design rules (menu File-Preferences-Sizes-DesignRuleChecking). Otherwise, change the spacing on your solder jumper. I see that you have the pads about 8.1 mils apart - that's pretty close. Check your design rules. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How to connect pads to anything?
ElementLine [ ... is that a typo? The line is incomplete. I deleted, and then loaded the part onto a layout, which worked out. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: How to connect pads to anything?
If you are willing, send the .pcb file over. I can take a closer look. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: pcb crooked traces
I hope the attachment comes through. If not, I'll post it somewhere. I cannot get rid of the jagged diagonal lines on my design. There's lots of them. The picture shows a couple of examples. I've tried different grid sizes, line widths, but nothing fixes the problem. Redrawing them in order to eliminate any sections does not help. On PCB, it shows at some zoom levels but not others. It is in the gerbers as well and it is in the photo-mode picture I attached. PCB 2009 It passes my design rules, but looks ugly. Traces are 8 mil, spacing is 8 mil. Grid space is 1 mil. gene inline: crookedTraces.png ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb crooked traces
If the tracks select as a single piece, it is just a rendering artefact due to the line not being _exactly_ 45 degrees. The gerber plot might be better when viewed in High quality mode in gerbv. PCB, and the lower quality gerbv modes don't render anti-aliased lines, so this is likely the source of what you are seeing. The fact it changes with zoom level also leads me to suspect the same. That helps! Still have a couple of duds - but they look to be multiple segment lines that need patching up. Let me see how that works out. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: QFN soldering
here's a video I found that answers a lot of questions - http://store.curiousinventor.com/guides/Surface_Mount_Soldering/QFN/ (scroll down just a little for the video) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: QFN soldering
does anyone have experience with this package? I want to know if they are hard to work with. The exposed pad underneath is a problem for hand soldering - but maybe could be left unsoldered for prototypes. Maybe just place some solder paste under there ? If the pcb pads are long enough, is it feasible to solder to the edge of the chip instead of getting it underneath the device? thanks gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Icarus verilog Synthesis
I am looking for a book that for example describes how a for/while/repeat/forever and other verilog behavioral constructs are converted to multiplexors/and gates etc. For FPGA work, I am unaware of any engine that can synthesize those constructs. If you read through the XST manual from Xilinx (just for an example), I am pretty sure they tell you what can and cannot be synthesized. The commands you just listed work well for test benches or other verification code (and simulation too) but are probably not appropriate for fpga level design. Maybe VLSI is different - but I have no experience with that. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: next PCB release - 1.99za vs 4.0
DJ Delorie wrote: Shall we / I push this? I think it looks good overall. off the top of my head . . . A) slots in planes (may be already in the process?) B) square/rectangular holes (e.g. mounting tabs) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: the incredible growing PCB window
gene glick wrote: Stefan Salewski wrote: On Sat, 2010-08-28 at 20:35 -0400, gene glick wrote: I haven't yet put my finger on what operations cause this, but the PCB GUI window keeps growing larger than my screen! Anybody know what gives? yep, sorry about that - PCB version 20091103 OS : linux, slackware V12 GUI: GTK compiled myself. Desktop: KDE 3.5 Some further info: - The problem is repeatable on other desktops (XFCE, Fluxbox, KDE) - It looks like the screen always grows when I set a mark, CTL-M, and move the mouse around. In the title bar is the position indicator. As the numbers move and become larger than the allocated space, the indicator box expands. On XFCE desktop, the position indicator grew to the left, pushing the pcb title left but the screen didn't grow - at least for a while. Eventually, it grew to the right. But on all other desktops, the window grew to the right only. It pushes the right hand side of the window off the visible viewing area. My pcb board area is 20 X 14, and the pcb itself is 11 X 11. regards gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: the incredible growing PCB window
Stefan Salewski wrote: Please try this: Select File-Preferences, and then General, and Alternate window layout to allow smaller horizontal size. And try Put layout name on the window title bar below. That is a good work around, thanks! DJ: What's your screen resolution? 1280 X 800. I have to run a video patch at boot time called 915resolution. Without this, I don't get resolution beyond 1040 X something. I can reproduce the window grows feature, but only if I start with a really small window, and it only grows so far then stops. Yes, same here - as long as I check off the alternate window option. Otherwise the window fills up all the horizontal width of display, and grows past it. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem unresponsive to keyboard input
kai-martin knaak wrote: Cory Cross wrote: I always got bit by pressing the Tab key, it would move the focus to one of the GUI buttons at the top of the screen and nothing more would pop up in the status bar. Hard to figure out if you are not expecting it. Another quick hit to Tab and everything goes back to normal. I can confirm this for a fairly recently compiled gschem. This looks and feels a lot like the unresponsive mode we experienced. ---)kaimartin(--- same thing here. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: the incredible growing PCB window
Stefan Salewski wrote: On Sun, 2010-08-29 at 14:57 -0400, gene glick wrote: PCB version 20091103 OS : linux, slackware V12 GUI: GTK compiled myself. Desktop: KDE 3.5 I may try it out with another desktop to see if there's any change. Additionally, I have to apply a patch during boot to make my my screen size go to 1280 X 800. Just wondering if it has any implication here. On any other program, I have not seen this problem. gene I am using version 20091103 (GTK) myself, I have never seen problems with window sizes. You may try to delete the .pcb/ configuration directory in your home directory, it contains a .pcb/preferences file with window sizes. Maybe there is something wrong. If you delete it, PCB will generate a new one. That wasn't it. I think the problem appears when I am dragging a component (left-click + drag) and auto-panning. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem unresponsive to keyboard input
DJ Delorie wrote: Sounds like command-line mode, the : key. Press ENTER to run the command, or ESC to abort it ? I've had the very same thing happen to me too. Usually if I 'alt-tab' to another open window, then 'alt-tab' back. Something along those lines but I've never spent much time trying to get the exact sequence. I too have been unable to exit from the mode other than to restart the app. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: the incredible growing PCB window
Stefan Salewski wrote: On Sat, 2010-08-28 at 20:35 -0400, gene glick wrote: I haven't yet put my finger on what operations cause this, but the PCB GUI window keeps growing larger than my screen! Anybody know what gives? It's not the end of the world, just weird. gene May it be useful to say -- which PCB version -- which OS -- which GUI (GTK or Lesstif/OpenmMotif) -- compiled yourself or binary from a distribution -- ... yep, sorry about that - PCB version 20091103 OS : linux, slackware V12 GUI: GTK compiled myself. Desktop: KDE 3.5 I may try it out with another desktop to see if there's any change. Additionally, I have to apply a patch during boot to make my my screen size go to 1280 X 800. Just wondering if it has any implication here. On any other program, I have not seen this problem. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: the incredible growing PCB window
I haven't yet put my finger on what operations cause this, but the PCB GUI window keeps growing larger than my screen! Anybody know what gives? It's not the end of the world, just weird. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gnetlist didn't catch duplicate hierarchical block
FYI - maybe by design? But I accidentally named 2 hierarchical blocks with the same refdes's. gnetlist -g drc2 didn't flag it either as a warning nor an error. The netlist is worked out correct, nonetheless - but maybe because I don't have any similarly named components within each block. Just good luck, in my case. Is it a bug? Is it a feature? Whatever - there it is. :) gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: analog/digital partitioning
On Thu, Jul 22, 2010 at 8:29 PM, Geoff Swan wrote: I came across this ( http://www.tentlabs.com/InfoSupport/page35/files/Supply_decoupling.pdf) some time ago. I would be interested to hear peoples thoughts as there are clearly many differing views on correct grounding and supply decoupling. The article certainly made a lot of sense to me and until proven otherwise it's the approach I follow. I understand why multiple ground planes seem attractive with the idea of somehow partitioning different current flows - but I have yet to see an implementation where this worked as intended. I have debugged circuits where there were as many as 4 separate ground planes and this certainly did not help the noise problems. I recognise that this is not enough to rule out the approach - just that the person designing didn't understand what they were doing. If someone has a design/layout that has *correctly* implemented split grounds etc I would be keen to have a look. Better yet if the design approach can be explained. This is one of those elements of practical electronic design that seems to be glossed over as assumed knowledge, and not necessarily very well taught. regards, Geoff This is a huge topic, Geoff. There are a whole lot of rules of thumb that have been written to help people get to the finish line without spending too much time thinking about it. In the specific case, the best answer is it depends, and you have to excercise some brain cells, assuming you understand the basic reasons for making a design/layout decistion. Also, what works at audio doesn't necessarily work at 1 GHz. Edge rates are just as important as clock rates in the SI world. For some good info, you can check out stuff from Howard Johnson, Henry Ott, Eric Bogatin, Doug Smith, Lee Ritchey to name just a few (there are many more). In my case (this thread) I was concerned about slots. Having been taught they are not good (rule of thumb) I was having a tough time allowing it - even though it looks like a pretty good solution. Here's some info from Henry Ott on this subject: http://www.hottconsultants.com/techtips/tips-slots.html Some info from Lee Ritchey apparently backs up the notion as well (I don't have any reference to it though) good luck gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gnetlist hierarchy with pass-through
I have a hierarchical block with these names: V7 input power to block V7_RTN input power to block, return leg V5 output power from block V5_RTN output power from block , return leg within the block, V7_RTN and V5_RTN are connected - in other words, it's a pass through. At the top level, there's a net labeled V7_RTN connected to V7_RTN-PIN on block and likewise a net labeled V5_RTN connected to V5_RTN-PIN. I expected to get V7_RTN and V5_RTN connected at the top level (although not sure what name it would have taken), but the netlister does not honor the connection (looks like it makes 2 separate nets). Is this by design? gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: dxf dwg viewer?
Stephen Ecob wrote: On Sat, Jun 26, 2010 at 10:33 PM, gene glick carzr...@optonline.net wrote: can anyone recommend a viewer for these drawings? I like QCad community edition. DXF is its native format, and it can edit as well as view. Thanks, that worked great! BTW, I just noticed that DIA can open and edit it as well. DIA is a very nice package, similar to visio gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: sd card footprint
billium wrote: Hello all, Has anybody got a footprint for a SD card, not mini or micro. This has been asked in the past but the person with the required footprint was on geocities which is now defunkt. I suppose that was me :) Try this, if you still need it http://www.avtek-us.com/pub/sdCardExample.tgz ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: dxf dwg viewer?
can anyone recommend a viewer for these drawings? gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: cutout in plane
Best method to put a hole in a plane? I tried the zero width line with clearance of 15 mil which sort of works, but leaves behind a small 0.1 mil line. It's visible on the gerber. Basically, I want a power plane (+3.3V) with a small power island in the middle (+1.2V). thanks gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: cutout in plane
DJ Delorie wrote: You can either get the git head PCB which has true hole support, or draw a C shaped polygon where the two arms touch to make a pseudo-hole. Hi DJ, Yep, that seems to work. How does the git head feature work? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: cutout in plane
hey, maybe I should look back at my emails :D I see a bunch of stuff there about this very thing - doh! ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: cutout in plane
DJ Delorie wrote: How does the git head feature work? I haven't had a chance to play with it yet. It's ok to do it peace meal, isn't it? Make an island, whatever shape. The surround it with other rectangles, for example, until there's a desired gap. My power plane is going to be made up of a bunch of polygons, looking like a big ole quilt :D But I think it works. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PCB 45 degree lines
Hi, I know we've gone over this before, but I still can't get a decent 45 degree line. I've changed to the ,45 line type instead of -/ type and have the same problem. Last time I brought this up, I was trying to attach to an already drawn line segment and right at the connection point there is some jaggedness. Well this hasn't gotten better. But worse, is when drawing one complete line from pad to pad, with a long 45 angle, the raged lines appear. It passes DRC, but just looks kind of lousy. I'm using 8 mil lines, 8 mil space and 1 mill grid space - if that helps any. thanks gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: pcb 45 degree angles
My 45 degree routes don't always make straight lines. There's a very slight jog in them. Usually, this happens if the route stopped, and then I added to it. I don't know if that makes much sense, but if it does, is there a way to clean that up? I can post a picture of it, if needed. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb 45 degree angles
John Luciani wrote: When this happens to me it is caused by not starting on the end point. Sometimes, especially with 45 deg traces, the end point can be a little tough to select. Also if you have changed to a coarser grid it can be more difficult to hit the end point. (* jcl *) These particular traces are 8 mil, and the grid space is 1 mill. I'm fairly certain that it connects to the right place, but it's as if the grid spacing is off by less than 1 mil so the trace is off kilter, ever so slightly. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: flash data bus pinout
I have an 8-bit flash PROM to connect to a uP. It's the only PROM. Otherwise the micro data bus is 32-bit wide, and SDRAM lives there. The PROM has it's own CS, ALE, etc. For a better layout, it would be far easier to route D0 of the uP to D7 of the PROM. I don't see any reason not to - just wondering if you all agree. This is something I've done in the past with SRAM, but heard it's not kosher with SDRAM. thanks gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: un-tented vias and solder mask
timecop wrote: Thats funny, i'd rather HAVE my vias covered with solder mask. Me too, but there's merit to both ways. I work with a guy who made all the vias visible, but placed them so badly that stuff shorted to them all the time - like a metal can from a crystal, *bad*. I had him just cover them all up. For me, if I need to solder to a via, it's easy to scrape the soldermask off with an exacto. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: fitting a board into a chassis
Bob Paddock wrote: On yet another note, has anyone used metal dome push-button switches? I have used membrane switches with domes. Check their rated life. After a few hundred thousand operations some of them collapse and short. Can happen if you are designing equipment for years of service. http://www.duraswitch.com claim to not have this problem. This idea is fading for me. I think it's going to be better to use a tactile momentary push-button switch. My search is ongoing. I'd like to find one that allows a long enough button so I can mount it on main pcb, and make the pcb small enough to allow some fitting slop. Otherwise, I'll go with plan 'b' and make a small button board :) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: fitting a board into a chassis
DJ Delorie wrote: I used a tactile switch and some wooden buttons in my alarm clock... http://www.delorie.com/electronics/alarmclock/ http://www.delorie.com/electronics/alarmclock/20071007-button-detail.jpg That is pretty close to what I think would work nice. I'm having zero luck finding the buttons that mate to the switch though. Yours is custom, obviously. I'll keep looking. Again, this means a front-panel for the buttons, but maybe that's the way it should be. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb DRC
timecop wrote: Poor excuse. People soldering those close-up components will not know where to orient it and have to refer to your assembly drawing. A colleague recently made a board where with the refdes's under the parts and called it industry standard practice. Nobody liked hauling around an assembly print to know what was what. not printing silk outline for at least R/C/L is silly. Very true. Although some places you'd have to be creative, seems like lots of room for silkscreen 2. Many of your parts are placed *extremely* close together. Too close what? Those are 0603 components? No problem unless the pads are wrong. Yep, look for example, at X2/C10 (at X=3426, Y=2381) it is so close to X2/R9 and X2/R5. How will you avoid solder bridges there? In fact, the solder mask in that area overlaps, so theres nothing to stop the solder bridge. Also, the body of X2/U1 overlaps the body of X2/R9 and X2/R5. Maybe that U1 body outline is really bigger than the actual part, but even so, it's going to be very tight to assemble. There's a ton of real-estate there, why not spread it out a little bit. Minor point - in the area where the layer numbers are visible, 1 2 3 4 5 6, the 6 is mirror imaged. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb DRC
Stephan Boettcher wrote: Stephan Boettcher boettc...@physik.uni-kiel.de writes: I did not dare to ask for so detailed reviews of this board, Hi Stephan, Sorry about that - it's a habit of mine. Your system sounds interesting. I just skimmed through your description and will read it in further detail later. thanks for sharing it. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb DRC
Stephan Boettcher wrote: And since I do not have much experience with GHz class opamps, I tend to put the parts rather too close than too far apart. I do not want an oscillator there. Some recent work at my day job involved 400 MHz opamps. These things require careful layout to keep from oscillating, just as you say. The vendor (TI, I think) recommends removing copper on all layers around the input pins. Trust me, this works. One board accidentally removed the cutouts, and the opamp sang like a soprano. Other stuff that is pretty good practice is to place a series 10-Ohm resistor on the output of the amp. You can always zero it out, but it gives you the chance to decouple the output from the input - especially if you are running unity gain. Watch that phase margin! And since we want to sample with 14-bit resolution, I do not want too big antennas on the input circuits either, to pick up digital noise from the back end. I suggest to follow the current path, from opamp vcc/vee to load, and back to opamp. Be sure the return path is not through the supply, possibly off the card. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: fitting a board into a chassis
What's your opinion on this? In this application, there are connectors on the front and rear of the box. I could: 1) Make the board large enough that the connectors are in the correct positions. or 2) Make 2 cards, one smaller that fits snuggly against the back, for example and then a 2nd small board for the front connectors. Then, cable the 2 cards together. In (1), I am worried that the tolerances of the card and box will make fitting it difficult. In (2), I don't like the additional board + cables. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: fitting a board into a chassis
Stefan Salewski wrote: On Sat, 2010-03-27 at 14:18 -0400, gene glick wrote: What's your opinion on this? In this application, there are connectors on the front and rear of the box. When ever possible, I would place connectors on front and one side, this makes live much easier. Yep, but it won't work in my app :( On yet another note, has anyone used metal dome push-button switches? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: fitting a board into a chassis
David Griffith wrote: On yet another note, has anyone used metal dome push-button switches? Are you talking about those metal snap domes used in Atari 2600 joysticks? I have no idea about the Atari. But, for example, here's one vendor : http://www.snaptron.com/homemainxxzxqma100.cfm What I am looking for are push buttons for the front panel. It should be, maybe, a nice round mushroom type of button. I'm not saying these dome thingys are what I want because I'm not sure what exactly I want and I am not exactly clear on how these domes work. Any idea? thanks gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb DRC
This is the board: http://www.ieap.uni-kiel.de/et/people/stephan/solo/eda/erena/erena.pcb Any idea if it is a good idea to just ignore these violations? Blindly ignoring violations is probably not a good idea. Better to understand them first. I hope you don't think I am picking on you, and maybe I am mis-reading the design, but I think there's a bunch of stuff wrong: 1. You have silkscreen printing going right through most of your pads. How do you plan to solder to that? 2. Many of your parts are placed *extremely* close together. Certainly a pick and place machine won't be able to handle it. Hand placing may be difficult. I'm not sure if you'll be able to solder to them. 3. On the signal layer, you have a big copper ring going along the perimeter, unconnected to anything. That is not a good idea. Maybe you intended this to be a ground guard ring? If so, it should connect to ground. There's more. Have I misunderstood your layout? gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Cygwin still supported?
David MacQuigg wrote: The alternatives I am considering are install under Mac OS X, or set up a third machine with a suitable Linux distro. I've been using Cygwin for all my Unix needs, so I would like to stick with that, if possible. I also use CentOS (a clone of Redhat) on a remote server. Suggestions will be greatly appreciated. My usual suggestion is to load up Sun VirtualBox, then install any Linux/Unix flavor you like. You'll be running 'real' linux at that point, and installing gEDA/GAF is pretty easy. Works great, and plays just fine with Windows as a host. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: if you people want to do it then put up the *cash*
So now the question is Who else will pledge money?. John You can count me in too. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gschem status window opens full screen
How do I stop this - it's making me nuts :) gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gschem status window opens full screen
Peter Clifton wrote: Just delete the section, and gschem won't try to override anything. It will - however, save the position when you close the log window / gschem, and keep that for next time. worked great - thanks, Peter! ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA user: gnetlist -gdrc buffer overflow and gnetlist -gspice-sdb killed
Facundo Ferrer wrote: When I try to check my circuit with drc or drc2 gnetlist finished with a buffer overflow. I don't know how to solve this. Also, I tried with spice-sdb but gnetlist finish with Killed. Have you tried this: http://www.geda.seul.org/wiki/geda:faq-gnetlist ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
John Griessen wrote: Bob Paddock wrote: Not sure. I know our CM loves that I put fuducials on the QFN So these footprint fiducials are outboard of the part so they show in a vision system as the part is being placed? Do you put silk outline outside them or some silk circles around each one to clue the CM about what they are good for, or does that just need some notes and documentation and phone calls? maybe this helps : http://www.carltonindustriesonline.com/cic_Fiducial.html ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: any last minute advice prior to sending out for PCB fab
After a very long time, I am just about ready to send out 3 different boards for fab. I would appreciate any advice to improve my chances of success. So far here's what has been done: 1. Run DRC on all PCBs with no issues.. 2. Checked schematics. 3. Checked schematic matches layout. 4. In process of checking all the components, especially the transistor pinouts (all SOT23 devices) 5. Checked the board dimensions. These boards plug into one another, so have to be sure they match up. It looks good physically and the pin numbers look correct from board-to-board. 6. Checked the soldermask. I found a bunch with very minimal dam spacing so fixed them. 7. fixed cosmetic trace runs that looked ugly. 8. double checked for unused traces left behind from component moves. The cash layout for PCB fab is going to be large enough that I am nervous about not getting it right. Still, I have a CPU card and SMPS to do which can wait a bit while this gets put together. what else? Any suggestions? thanks gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
DJ Delorie wrote: Print out your surface copper layers and put the parts on the printout to make sure they match. that's a really good idea, thanks! It'll delay things some, but yeah, sounds like the conservative way to go. I'll have to order up a bunch of parts to make it happen but that's ok. Printing out 1:1 should be close enough on a laser printer, I think. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: any last minute advice prior to sending out for PCB fab
John Luciani wrote: Check the gerbers and drill files using gerbv. I use a script that zips and renames all the files for the fab house. I take the zip file that is created, unzip it and check those files with gerbv. For a system of boards that plug into each I might panelize them so that they all align. You would quickly see misalignment. You would also save some money on the fabrication. (* jcl *) I completely forgot to mention that I generated the Ben-mode prints to check it all out - that is really helpful. And yes, like you, run a script to generate and rename the gerber files. Gerbv is a great tool, I like it a bunch. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Message and Library windows
(or certainly fix the message window's focus-stealing, attention grabbing - behaviour. The same is true of the netlist window when you press F on a net.) That one burns me often :D ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: TL431
As has already been mentioned, the problem will be what happens as the supply turns on. In theory, as VCC ramps up, the 431 will start to regulate and so limit its own cathode voltage. If VCC exceeds 36V before the 431 has started drawing current then all bets are off. Crude but you could try putting a zener in series with R3/NPN_B and 431 cathode to drop the excess voltage so that VCC - Vzen 36V. Any series combination of components from VCC to the cathode will suffer from this problem. The VCC will be present at the cathode if nothing is conducting, right. So what makes them break? If it's just a potential thing, like mosfet gate punch-through then this can never work. If it's the power dissipated in the part then I guess it won't matter until it really starts to conduct and this method should be safe. And another: they are notoriously unstable (and the spice models don't always show it) with certain cathode loads. Yep, I may have TI's model and the thing goes unstable with increasing load capacitance. That was a surprise. The feedback capacitor suggested helps, but does not eliminate the problem. All in all, may be more trouble than it's worth. I agree and have given up :) Instead, I'm using LM317, and some extra stuff to drop the voltage down to its input. Not so bad on part count. Cheers, Andy. thanks, Andy. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: TL431
I did not know what the regulator will be used for. +12V regulator supplies hi/low side mosfet driver. Positive side is ground, negative side is -50VDC. LM317 can replace both TL431 and series transistor. LM317HV. seems expensive and only comes in large packages. Nice idea though. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: TL431
Wojciech Kazubski wrote: - Anyone use these shunt regulators? I'm wondering about the max voltage. Or set up your mailer to use a fixed-width font.. Yes, that was it - thanks. I suspect this TL431 isn't a good device for my app. I have an LM317 to give me around +12V for bootstap voltage to a high-side mosfet driver. The average current is very low, but the peaks can get pretty high. The LM317 circuit is solid, just uses a lot of parts. I was trying to replace the LM317 with TL431 - but simulation does not look promising. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: TL431
Anyone use these shunt regulators? I'm wondering about the max voltage. Data sheet says max cathode-to-anode voltage is 36V. What if VCC = 50 V, as in this cheezy drawing is trying to show. R1 and R2 set the output voltage at the emitter. R3 limits the current to the cathode *and* drops enough voltage (greater than 14V) to allow the the cathode-anode voltage to be within 36V. Is that legit? Or maybe I have to design in some circuitry to drop the voltage down at the cathode. (npn) VCC -- C E -- | \ /| / -/ R3 \| B\ /| / R1 || \ | / | | | | --/ | / / \ | TL431 / \- -| | / | \ R2 | / | | | | | / / / ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: TL431
gene glick wrote: Anyone use these shunt regulators? I'm wondering about the max voltage. wow, that drawing didn't look very good in my mail client, but if you cut and paste into kedit it looks reasonable. :) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: PCB Prototype houses that do 0.031 boards?
Bob Paddock wrote: Anyone know of a proto-house that will do 0.031 thick boards? All the usual, automatic robot, players I've looked at only do 0.062 tick boards. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user These guys are in china. I plan to use them shortly, but can't say if they are good or not. Prices are very nice :) http://www.pcbcart.com/ gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: Latex
we're getting a bit more OT, but...
yep :)
\chead{\includegraphics{foo.eps}}
I had tried that already but it wasn't quite what I was looking for.
What worked out nice was placing a table in the header and placing
things exactly where I want them.
gene
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Re: gEDA-user: OT: Latex
I switched to LaTeX 15 years ago and have never looked back. mmm LaTeX. it just wasn't working well for a bunch of reasons (bugs, poor scaling to large documents, poor multi-author support, poor interaction with cvs or other source control system, sounds like you live in my cube (anti-productivity pod, for the dilbert fans) For all those same reasons, I've just switched. So far so good. It'll be interesting to see if I can convince my co-workers to try it out. One thing that I don't like though, is image support. Unless I am missing something, images are not actually part of the source doc, but are sucked in and then processed onto the output. Distributing the pdf, for example, doesn't matter since the pictures are included. But for multi-authors, any images have to be included with the article source files. The LyX route is working for now - but am already finding reasons to add LaTeX commands into the source file. Headers with images are a drag - still fighting that one. Time to get a good book :D gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: pcb join pad to polygon
I made a polygon on the top layer, and I want to place a component pad within the polygon. Is there a way to make it connect without adding a trace? By default the tool places a clearance gap around the pad - so it doesn't touch. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb join pad to polygon
Peter Clifton wrote: You can set the polygon to be solid, s key, but it does mean it will short against everything it touches. I often just use a small solid polygon which shorts against things to bridge the gap between a pad and a bigger, clearing polygon. Yep, that works ok. I had to use 2 polygons because the first touches some through hole pins that I need the thermal on. Setting 'S' makes them go away. cool ... thanks gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb join pad to polygon
Ben Jackson wrote: On Sun, Feb 07, 2010 at 09:18:35AM -0500, gene glick wrote: I made a polygon on the top layer, and I want to place a component pad within the polygon. Is there a way to make it connect without adding a trace? By default the tool places a clearance gap around the pad - so it doesn't touch. Are you sure you want 100% connection like the other reply suggested? That can be very hard to solder, especially on a multilayer board where the top is well stitched to internal ground layers. I really think pads should have the same thermal feature that pins do, but since they don't I just draw lines and set *them* to merge with the poly. If I want low impedence I just make a + of wires. Hmm, maybe - maybe not. Here's the scoop: first is a connector, with through hole pins. It can't use solid connections otherwise I'll never be able to solder to it - or remove it. This thing runs on +/-50V rails, and is high current. It connects to a 0.01 Ohm surface mount resistor (2512) used for current monitoring. This circuit is set to trip at about 17A. This is peak stuff, not average. Maybe I should look up how fat a 1/2 ounce trace needs to be to handle that sort of current. Maybe it's sufficient to make the track no larger than the width of the 2512 resistor? gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb join pad to polygon
Peter Clifton wrote: For 0.01 Ohm sensing, you probably want to attempt at making a kelvin connection, see http://www.edn.com/article/CA502424.html Interesting. I'm really not yet convinced on the best trace width - if it turns out to be larger than the pad size of that 0.1 Ohm resistor, than it is irrelevant. There's a bunch of calculators online to help figure out appropriate trace width. I suppose that they assume DC. My app is audio, so the likelihood of an average current is much lower. I really care about the peaks, and more importantly, a short circuit. So even then, by the time the circuit figures out there is a short, the drive circuit is already shut down (maybe the order of tens of microseconds, or so). I don't expect things to heat up much - which implies that the kelvin technique would work. I'm just not sure though, which route to go. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: OT: Latex
Do you all use Latex for editing docs, or maybe open office or other? I'm getting fed up with the open office bugs and starting to think that Latex is a better alternative. Busy compiling Lyx as we speak. Just curious if it works out well- thanks gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: Latex
Dave McGuire wrote: I use OpenOffice for quick dirty stuff, but LaTeX (with PDF output) for anything that has to look good. Lyx is pretty nice but those types of front-ends usually just get in the way. -Dave First off, thanks for the input from all. So you write in a text editor, add in your own codes? OK. This is new to me since I've used MS Word for ever, and Open Office to a lesser extent in the past 2 years. I dread using Open Office for reports :( It's a huge struggle every time to get stuff to look nice. All the rhetoric about TeX sounds good. So now I will see. Lyx seems ok to me so far. The option to edit directly is always there - I think. Anyway, time to fire up the Chevelle SS396, pop the clutch, burn some rubber, and haul butt up the learning curve :) gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Move refdes on the board
uv wrote: Dear Sirs, How can I move/rotate the reference designator of component in PCB 20091103? In the previous versions this feature was made by same controls like moving any other object on the board. Thank you Péter I've had trouble moving text on the 'other' side of the board. If you 'tab' to the opposite side, then 'tab' back again, you may not be able to move the text around. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: soldermask clearance
What's the right amount of clearance? Seems like .003 is good, but I don't know. A google search found one article that said for fine pitched parts, it's better to have the entire row blocked. That is, instead of individual clearances around each pad, the soldermask exposes the entire row at once. They claim the very thin webs in between pads are too thin to cure correctly, and will smudge later onto the pads. Anybody experience this sort of thing? If there's no soldermask in between pads, isn't is more likely to get a solder bridge? thanks gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: ExecuteFile(bob.cmd) question
Why does this take so long to complete in PCB2008 and 2009 version, but is a snap in the git head version? Also, is it really necessary? gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: sd-card connector sym and fp needed
Michael Kamper wrote: Hi! Anyone has a sd-card design including a footprint I could use? I found an old thread but the link provided there is dead and the author unfortunately doesn't answer. Sorry for not ever replying, somehow I missed this. Try this link instead of the original: http://avtek-us.com//pub/sdCardExample.tgz ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: blue sky ideas - written down finally
DJ Delorie wrote: I'm not exactly sure what's best here, but I know it doesn't belong in the *gate*. My idea is to have a table object that shows up in the schematic, like in a corner or something, that lists all the power pins and what nets they connect to. I've seen other schematics with this, it seemed much cleaner than what we do. I think you are advocating the logical view schematic (as opposed to a physical view). BTW, John Doty does this for his connectors - as I recall. A schematic represents different things to different people: The technician likes the symbols to closely resemble the physical parts. It makes working on the board easier since he doesn't need data sheets in addition to the schematic. The engineer is interested in connectivity and functionality. There's a ton of divergence here - analog vs digital, low speed high speed etc. The PCB layout guy wants the schematic to give clues, how the engineer envisioned the flow of physical parts. That's just a short list, I'm sure. Be aware though, you probably can't make everyone happy with any one style. Personally, the physical view seems to cover the largest group. Yeah, large FPGA or uP don't fit very well on the sheet. Maybe that's a place where your method works out. It seems to work for John Doty and connectors. You just don't want to get to the point where you'd be better off with just a netlist - which totally defeats the purpose of a graphical entry system. $0.02 from gene :) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: unable to move silkscreen text on bottom layer
I can create text on the solder side of the board, but cannot move it, select it, rotate it or delete it. At some point earlier, I placed a bunch of text on the back side of the board and was able to rotate and move it. Now I can't. Any help? PCB version 20081128 (I tried in a newer build git head 3d stuff, but exactly same problem persists). gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: unable to move silkscreen text on bottom layer
update to that last post: Method 1 - This sequence leads to the problem: 1. Open PCB 2. Turn off all layers except component side. 3. Flip board (tab) Method 2 - But, this sequence always seems to work: 1. Open PCB 2. Flip board (tab) 3. Turn off all layers except solder side. I usually turn off the ground and power layers because it slows down the drawing response time. It's also just in my way when editing the text. On a whim, I tried method 2 and am now able to edit the solder side text. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: unable to move silkscreen text on bottom layer
gene glick wrote: update to that last post: Method 1 - This sequence leads to the problem: 1. Open PCB 2. Turn off all layers except component side. 3. Flip board (tab) Method 2 - But, this sequence always seems to work: 1. Open PCB 2. Flip board (tab) 3. Turn off all layers except solder side. One more thing I just ran into ... After method 2, I can't edit, move, select text on component side - doh! gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: unable to move silkscreen text on bottom layer
DJ Delorie wrote: Try no grid Same result :( ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: radial pkg advice
Here's the specs for a radial leaded capacitor: 7.5mm lead spacing, +/- 0.4mm lead diameter, phi = 0.5mm What makes more sense for pcb layout: 1) Go with the spec as-is, and squeeze the leads into board if spacing is off nominal. 2) Use 7.5mm spacing with large holes to accommodate the tolerance. I figure the max spacing is 7.5 + 0.4 + (0.5*phi) = 8.1mm and minimum spacing is 7.5 - 0.4 - (0.5*phi) = 6.85mm So a hole size of (8.1 - 6.85)= 1.25mm should let the cap just drop right in for all cases, yes? Would it be too sloppy though? regards gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gschem 1.5.2.20090328
I've hit this problem a couple of times now. Any plain text on the schematic is messing up the backend processing. The most recent problem occurred when I made a very minor change, rotated a connector on the schematic. Gnetlist -g PCB reports read garbage and points to the sch file that I just modified. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: PCB footprint for Vampire PCB2F/A wanted
Anybody have this? gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: OT diode reverse saturation current
I'm trying to find some info on the temperature variation of the reverse saturation current of a diode. Anyone know about this? gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: hierarchy browser app
I'm working on something, and a side effect of it outputs the schematic hierarchy. Is this useful to anyone? The syntax is '.' is the top-most directory of the schematic. '/' separates the paths and the schematic name. So, for example, ./schematic1.sch is a schematic located at the root of the tree. Here's a sample output as of this morning (using a current schematic of mine): ./ampzilla-base_pg1.sch ./S2/fpga_pg1.sch ./S2/fpga_pg2.sch ./S2/fpga_pg3.sch ./ampzilla-base_pg2.sch ./S4/spdif_pg1.sch ./S6/audio_top_pg1.sch ./S6/S104/fe_1ch_pg1.sch ./S6/S104/fe_1ch_pg2.sch ./S6/S103/fe_1ch_pg1.sch ./S6/S103/fe_1ch_pg2.sch ./S6/S109/adc_2ch_pg1.sch ./S6/S110/adc_2ch_pg1.sch ./S6/S105/fe_1ch_pg1.sch ./S6/S105/fe_1ch_pg2.sch ./S6/S106/fe_1ch_pg1.sch ./S6/S106/fe_1ch_pg2.sch ./S6/S111/adc_2ch_pg1.sch ./S6/S107/fe_1ch_pg1.sch ./S6/S107/fe_1ch_pg2.sch ./S6/S108/fe_1ch_pg1.sch ./S6/S108/fe_1ch_pg2.sch ./S6/S100/power_pg1.sch ./S6/S100/power_pg1.sch ./S6/audio_top_pg2.sch ./S6/audio_top_pg3.sch ./S6/S301/dac_2ch_pg1.sch ./S6/S303/mux4_pg1.sch ./S6/S304/mux4_pg1.sch ./S6/S307/ampConnectorOnly_pg1.sch ./S6/S309/ampConnectorOnly_pg1.sch ./S6/S308/power_pg1.sch ./S6/S308/power_pg1.sch ./S6/audio_top_pg4.sch ./S6/S401/dac_2ch_pg1.sch ./S6/S408/ampConnectorOnly_pg1.sch ./S6/S409/ampConnectorOnly_pg1.sch ./S6/S402/mux1_pg1.sch ./S6/S403/mux1_pg1.sch ./S6/audio_top_pg5.sch ./S6/S501/dac_2ch_pg1.sch ./S6/S509/ampConnectorOnly_pg1.sch ./S6/S508/ampConnectorOnly_pg1.sch ./S6/S502/mux1_pg1.sch ./S6/S503/mux1_pg1.sch ./S6/audio_top_pg6.sch ./S6/S601/dac_2ch_pg1.sch ./S6/S609/ampConnectorOnly_pg1.sch ./S6/S608/ampConnectorOnly_pg1.sch ./S6/S602/mux1_pg1.sch ./S6/S603/mux1_pg1.sch ./S6/audio_top_pg7.sch ./S6/S700/volume_8ch_pg1.sch ./S1/ethernet_passthrough_pg1.sch I found something interesting too. Look back and you will find ./S6/S100/power_pg1.sch ./S6/S100/power_pg1.sch So I managed to have the source= attribute embedded in the symbol *and* on the schematic. Somehow I didn't catch it before. The netlist came out correctly just the same :) gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: hierarchy browser app take 2
Wow - what happened to my last email? OK, here's another attempt . . . I am working on a program, and it has a side benefit that displays the schematic hierarchy. Is that something anyone could use? Here's a sample output: ./ampzilla-base_pg1.sch ./S2/fpga_pg1.sch ./S2/fpga_pg2.sch ./S2/fpga_pg3.sch ./ampzilla-base_pg2.sch ./S4/spdif_pg1.sch ./S6/audio_top_pg1.sch ./S6/S104/fe_1ch_pg1.sch ./S6/S104/fe_1ch_pg2.sch ./S6/S103/fe_1ch_pg1.sch ./S6/S103/fe_1ch_pg2.sch ./S6/S109/adc_2ch_pg1.sch ./S6/S110/adc_2ch_pg1.sch ./S6/S105/fe_1ch_pg1.sch ./S6/S105/fe_1ch_pg2.sch ./S6/S106/fe_1ch_pg1.sch ./S6/S106/fe_1ch_pg2.sch ./S6/S111/adc_2ch_pg1.sch ./S6/S107/fe_1ch_pg1.sch ./S6/S107/fe_1ch_pg2.sch ./S6/S108/fe_1ch_pg1.sch ./S6/S108/fe_1ch_pg2.sch ./S6/S100/power_pg1.sch ./S6/S100/power_pg1.sch ./S6/audio_top_pg2.sch ./S6/audio_top_pg3.sch ./S6/S301/dac_2ch_pg1.sch ./S6/S303/mux4_pg1.sch ./S6/S304/mux4_pg1.sch ./S6/S307/ampConnectorOnly_pg1.sch ./S6/S309/ampConnectorOnly_pg1.sch ./S6/S308/power_pg1.sch ./S6/S308/power_pg1.sch ./S6/audio_top_pg4.sch ./S6/S401/dac_2ch_pg1.sch ./S6/S408/ampConnectorOnly_pg1.sch ./S6/S409/ampConnectorOnly_pg1.sch ./S6/S402/mux1_pg1.sch ./S6/S403/mux1_pg1.sch ./S6/audio_top_pg5.sch ./S6/S501/dac_2ch_pg1.sch ./S6/S509/ampConnectorOnly_pg1.sch ./S6/S508/ampConnectorOnly_pg1.sch ./S6/S502/mux1_pg1.sch ./S6/S503/mux1_pg1.sch ./S6/audio_top_pg6.sch ./S6/S601/dac_2ch_pg1.sch ./S6/S609/ampConnectorOnly_pg1.sch ./S6/S608/ampConnectorOnly_pg1.sch ./S6/S602/mux1_pg1.sch ./S6/S603/mux1_pg1.sch ./S6/audio_top_pg7.sch ./S6/S700/volume_8ch_pg1.sch ./S1/ethernet_passthrough_pg1.sch ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: hierarchy browser app take 2
sorry for that - somehow my email client went all squirrelly and didn't display the message content. You can ignore this take 2 version. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: bom fails
I've tried this in both version 1.4.0 release and 1.5.2, with different messages, but all fail. I've tried gnetlist -g partslist gnetlist -g partslist1 gnetlist -g partslist2 gnetlist -g partslist3 and all fail. Any help? Here's the output from gnetlist -g partslist1 (partslist2 partslist3 same result), from 1.5.2 release: Backtrace: In /home/gene/geda/share/gEDA/scheme/gnet-partslist-common.scm: 28: 720* [get-parts-table (S6/S108/U42 S6/S108/R44 S6/S108/R43 ...)] 19: 721 (if (null? packages) (quote ()) ...) ... 24: 722 [cons (U42 NE5532ADR unknown SO8) ... 28: 723* [get-parts-table (S6/S108/R44 S6/S108/R43 S6/S108/C45 ...)] 19: 724 (if (null? packages) (quote ()) ...) ... 24: 725 [cons (R44 MCR10EZHF1001 1k 0805) ... 28: 726* [get-parts-table (S6/S108/R43 S6/S108/C45 S6/S108/C44 ...)] 19: 727(if (null? packages) (quote ()) ...) ... 24: 728[cons (R43 MCR10EZHF47R0 47 0805) ... 28: 729*[get-parts-table (S6/S108/C45 S6/S108/C44 S6/S108/C43 ...)] 19: 730 (if (null? packages) (quote ()) ...) ... 24: 731 [cons (C45 GRM1885C1H182JA01D 1800pf 0603) ... 28: 732* [get-parts-table (S6/S108/C44 S6/S108/C43 S6/S108/C42 ...)] 19: 733 (if (null? packages) (quote ()) ...) ... 24: 734 [cons (C44 CAPACITOR08055C104KAT2A .1uF 0805) ... 28: 735* [get-parts-table (S6/S108/C43 S6/S108/C42 S6/S108/R42 ...)] 19: 736 (if (null? packages) (quote ()) ...) ... 22: 737 (if (string=? # include) (get-parts-table #) (cons # #)) 22: 738* [string=? ... 22: 739* (get-device package) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: opamp slew rate limiting
Mark Rages wrote: I thought the whole point of a Schmitt input was to give the input a little snap and therefore increase the rise/fall times. It will. In my setup, 2 channels each setup as I described. The relative phase from one channel to the other remained pretty much constant throughout the various stages (which I require), including the slow-edge opamp circuit. It all fell apart going through the schmitt trigger. The faster edge into the schmitt trigger eliminated the phase/timing distortion. All in all, and I think most people agree, this isn't the ideal circuit for the given application :) I don't even want to describe the lousy asynchronous flip-flop design that follows the schmitt trigger for fear of a scolding :) (not my design, I have to repeat that for my sanity) In fact, I've done something similar to what you're doing. IIRC, it was like this: digital signal - big long RC - schmitt inverter - 4000-series flip-flop clock. And that circuit, inelegant as it was, worked fine. yep. You need the fast-ish edge for the clock. The CD4000 logic don't require very fast edges (5uS rise, for example) to work. Anything slower and you cannot guarantee the timing specs. That's what the scmitt trigger did in your case. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: opamp slew rate limiting
The gain is set at -10. The prior stage has gain, and off-hand I don't recall how large the signal is, I'll check. GBW for the part is 8MHz, I run it at 5kHz*10= 50 kHz GBW - plenty of headroom there. SR definition is SR = 2 * pi * f * Vpk So I need SR 6.28 * 5000 cycles/sec * 15 Volts, or 471,000 Volts/Second. If my math is right, that works out to 0.471 V/uS. Lots of margin there too, the part can do 20. I agree about the linear/saturation description, but couldn't find any hard literature on the subject. I removed all external capacitance, so all that remains is stray - hopefully small. You say that The gain is sufficiently large that the opamp is driven into saturation by the sine wave but by how much is it driven into saturation? Just near the peaks and troughs or very close to the zero crossings? great point. Maybe I should increase the gain to force the saturation earlier into the cycle. I was trying just the opposite. Ozzy Lash wrote: Are you sure your not just tracking the slow edge of the sine wave? Your 12 microseconds is about 20 degrees for your 5 kHz sinusoid. If you increase the frequency does the edge steepen? Does the slew rate go up and down as you increase and decrease the amplitude of the sinusoid? If so, I think that is your problem Bill Yeah, I now think this is the case. As has been alluded to already, the slew rate of the opamp is usually specified for the device operating in the linear region. If it is being driven hard into saturation then there will be some recovery time before the output can drag itself. out of saturation as the signal changes direction. Yeah, I thought the same thing. Wouldn't that just add delay, but not change the slew rate once it comes out of saturation? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: opamp slew rate limiting
Martin Maney wrote: Nah. You should use a good comparator with controlled hysteresis. An opamp, any opamp, makes at best a mediocre comparator. Actually, it worked! Not sure why I didn't think of it earlier, but I threw the circuit into simulation to see. By cranking the gain up from -10, to -200, the amp saturates much earlier in the cycle. Interestingly, with gain of -10, and input signal of about 2 Vrms, the output looked exactly like it does on the bench with edge rate of 20 uS. In simulation, changed the gain to -200 and the edges go to about 2 uS. Worked precisely the same on the bench. This I can live with, and solved my problem. I'm pretty sure this supports the notion that the output was really just following the input, saturating later in the cycle. Regarding John's point, I did in fact, change to FET input by going from opa2227 to opa2132. While the slower bipolar input device would probably work, I think I prefer the faster device for various reasons, including yours. Yeah, I totally agree that a comparator is the way to go - but it's too late for that. It's not my design, I'm just the flunky who gets to make it work right - or at least as good as possible. The digital logic used is old CD4000 stuff which is pretty slow. There's a D flip-flop in the circuit that calls for edges no slower than 10 uS - pretty slow by modern standards, but this circuit failed to even meet that. Oh, btw, this opamp used drives a schmitt trigger - sort of a poor mans comparator. Same problem though, with the slow edge rate fooling it. This turned out to be a fun thread, thanks for the help :) gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
