Re: gEDA-user: Now who's with me?
John P. Doty wrote: Bill Gatliff wrote: In the bigger picture, I'll note that the tutorials and FAQs I've seen for gEDA all focus on a pretty specific workflow, which is to turn a schematic into a circuit board layout. There are obviously a zillion different ways that the tools would be useful, and I would really appreciate it if someone would write a few of them down! I'm working on a gnetlist back end tutorial. I think that the capabilities of gnetlist are underappreciated, and that specialized back ends could be very useful. I'm a Contributing Editor for Embedded Systems Design magazine. If anyone wants to help me co-author a few short articles on using gEDA for things like circuit board layout, schematic capture, simulations, and whatever else it's good for, I'd be more than happy to give you ample credit and to assist in whatever capacity I can to see to it that the documents get published. They should be good candidates for the Wiki, too! If we can get some word out, and commit to documenting some of the really cool ways people are solving problems with gEDA, then I think we'll all get along a _lot_ better. We'll focus our efforts on the parts of gEDA that are truly lacking (and even identify them!). And we'd call more attention to the project, too. bluto Now who's with me? /bluto b.g. I am. I've spent some time on testing and documenting the gnetlist-verilog scheme language backend to help use the Gnucap simulator with gschem schematics. The gnetlist-verilog back end outputs a subset of verilog-ams, which is fully hierarchical. I'd like to get that to some more workable state -- it already did some hierarchic netlisting -- but I have not done the unit tests for it or written it up. Bragging on something like that kind of gnetlist to gnucap integration could get more Linux_Fund contributions to help with PCB using the same things -- putting out a new version of the gnetlist-pcb netlist with circuit values for the trace capacitances and distances. John Griessen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Now who's with me?
Bragging on something like that kind of gnetlist to gnucap integration could get more Linux_Fund contributions to help with PCB using the same things -- putting out a new version of the gnetlist-pcb netlist with circuit values for the trace capacitances and distances. The LF netlister is all new anyway, I could add more attributes if needed. The thing is, PCB doesn't do anything with them at the moment. How would gschem know about trace capacitances anyway? The netlister is only sch-pcb at the moment. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Now who's with me?
DJ Delorie wrote: -- putting out a new version of the gnetlist-pcb netlist with circuit values for the trace capacitances and distances. The LF netlister is all new anyway, I could add more attributes if needed. [jg]I read here: http://www.linuxfund.org/projects/pcb/proposal/ that the LF netlister means forward annotation. The thing is, PCB doesn't do anything with them at the moment. How would gschem know about trace capacitances anyway? The netlister is only sch-pcb at the moment. [jg]I wasn't thinking of the gschem representation of the design getting back annotated, just a separate simulation version of the design schematic. A subset that is the zone of interest for simulation purposes. Hmmm... back annotation -- I guess a good way would be similar to the way PCB handles an imported netlist -- it shows rat-nest lines and notes how many missing nets there are. That kind of functionality in gschem would be handy for adding trace capacitance lumped parameter components to a simulation schematic. You would not want all of the netlist usually, just the part you are simulating, so having a way to export only some from pcb would be a good way. Drawing a polygon on a layer so it contains the traces you want exported for back annotation is what I think of first for selecting a zone of interest for simulating. Then the back annotation file could be a difference file -- a to do list of changes to make just like the .pfa forward annotation file in the LF proposal. I guess my idea doesn't fit in the LF proposal after all -- it would mostly be an addition to gschem rather. To add gschem functions that let you load a netlist, then add components to match it as in pcb layout. Instead of that, you could just handle little cases like trace capacitance as a special feature of wires, but that would be specific and a fair amount of work.To import new netlist elements would be general and more power/flexibility. So the short answer is: gschem would know about trace capacitances by getting a match the netlist mode as well as the extract the netlist from the current state of the schematic mode it has now. John Griessen -- Ecosensory Austin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Now who's with me?
The LF netlister is all new anyway, I could add more attributes if needed. [jg]I read here: http://www.linuxfund.org/projects/pcb/proposal/ that the LF netlister means forward annotation. Right, gschem-pcb is forward. pcb-gschem is back annotation. I guess my idea doesn't fit in the LF proposal after all -- it would mostly be an addition to gschem rather. To add gschem functions that let you load a netlist, then add components to match it as in pcb layout. That would be back annotation. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
