Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
Good point Rick, I should have explained that even though the larger inductance reduces the rms current in the primary significantly, the positive and negative peak currents are highly asymmetric. Simulating with a sinewave input, the positive peak current is about 110mA whilst the negative is about -390mA. Hence the transformer has to have a considerably higher peak current rating than the rms values might suggest. Robert originally said his input is bandlimited 15KHz to 28KHz but all his circuits include some form of discrete bandpass filtering. I suspect what Robert intends is that C1 and some combination of the transformer primary - as in his later posting - or a single inductance to ground or an additional series inductance - as in the original circuit posted - forms a bandpass filter centred on about 23kHz. In any case it is difficult to see how C1 can be removed without adding some sort of active buffer stage between the rectifiers and the filter, which then requires some sort of bootstrap supply to bring up the buffer to drive the rectifiers. Andy. signality.co.uk On 29 June 2011 23:54, rickman gnuarm.g...@arius.com wrote: The transformer allows a DC path to exist on the secondary side, but you still have the capacitor on the primary side of the circuit. If the positive and negative pulse currents are not equal, you will still have a problem on the primary side. You need to remove the cap C1. I still can't tell exactly what is going on in your circuit because you don't provide any labels on the o'scope diagrams. It would also be useful to see current waveforms from the simulations and waveforms from the loads. As was asked for previously, we still have not seen your requirements so I can't tell exactly what you are trying to do with this circuit. How large is the DC offset in the source? Why don't you include that in your simulation model? What voltage do you need out of this supply? I really can't tell what is needed in your design and what is just wrong. Rick On 6/24/2011 7:10 AM, myken wrote: This is strange in my simulation the attached circuit works fine. In real life it kinda works but the signals are distorted like you can see. I think that has something to do with the fact we used a pulse transformer to try the circuit. If we disconnect Vx the signals stay the same, so the distortion is in the transformer. If you say it doesn't work then why doesn't it work? On 22/06/11 22:39, Andy Fierman wrote: Sorry Robert, Both Wojciech and I are wrong. His suggestion about adding a choke is basically the same as mine of using a transformer. The idea of both is to add a dc path to ground at the rectifier inputs. The difference is that the transformer adds DC isolation - which if you include your bandpass filter - you do not need. Sounds like the thing to do but sadly, the simulations show the reality! A choke does not do what you want and neither does a simple 1:1 transformer. However, if you use a 1:1:1 transformer then it all comes together. You can use a transformer with a 1:2 turns ratio, centre tapped and keep to the original half wave rectifier scheme. If you use a three winding transformer of 1:1:1 then you can use two bridge rectifiers. Using bridge rectifiers doubles the ripple frequency so allows lower smoothing C for the same ripple voltage. The attached (not very good quality) pdf shows the non-working choke and 1:1 transformer ideas and the working 1:1:1 transformer versions. Note the 1u smoothing capacitor values. These were reduced to make the simulation reach a steady state sooner than with the original 100uF values. Andy. signality.co.uk On 22 June 2011 01:12, Wojciech Kazubski [1][1]w...@o2.pl wrote: Hello all, I would appreciate some expert advice. I have a system which rectifies a sine wave input signal of 20Khz after a LC filter (see Rectifier_sim.jpeg) Everything works fine if LOAD_1 and LOAD_2 are equal. Vx is then (almost) the same as Vin. And Vcc and Vss are equal to the positive or negative part of the sine wave (less the DC losses) (Vss = -Vin_top and Vcc = Vin_top). BUT if LOAD_1 and LOAD_2 are not equal (like in Rectifier_sim.jpeg) it seems that Vx is lifted (DC component added) and Vss moves to the 0V and Vcc is lifted to twice the value I would expect (Vss = 0 and Vcc = Vin_toptop) (see rectifiersmp.eps). Our real life prototype shows the same behaviour as the simulation. I need this set-up for my system to work and I can not guarantee that the two loads always will be equal. Vin can be anything between 10Vtt and 90Vtt. I have tried adding a resistor from Vx to ground and that seems to help but increases the current drawn from the source (V1) to a unacceptable level. It should be a low power solution. If I short-circuit C1 everything works fine again (V1 has a low resistance output) but of course will
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
It's also hard to see how the circuit could work with C1 in series with the transformer current. Why is a capacitor needed if you use the transformer? Maybe there is some effect that will balance things out, but if the two currents are unequal, actually it would be the integral of the two currents that need to be equal, the peak value is unimportant, the voltage on the capacitor will grow without limit... until something limits it. In the circuit with the transformer, is there some effect that will balance the positive and negative currents in the primary? Rick On 6/30/2011 4:06 AM, Andy Fierman wrote: Good point Rick, I should have explained that even though the larger inductance reduces the rms current in the primary significantly, the positive and negative peak currents are highly asymmetric. Simulating with a sinewave input, the positive peak current is about 110mA whilst the negative is about -390mA. Hence the transformer has to have a considerably higher peak current rating than the rms values might suggest. Robert originally said his input is bandlimited 15KHz to 28KHz but all his circuits include some form of discrete bandpass filtering. I suspect what Robert intends is that C1 and some combination of the transformer primary - as in his later posting - or a single inductance to ground or an additional series inductance - as in the original circuit posted - forms a bandpass filter centred on about 23kHz. In any case it is difficult to see how C1 can be removed without adding some sort of active buffer stage between the rectifiers and the filter, which then requires some sort of bootstrap supply to bring up the buffer to drive the rectifiers. Andy. signality.co.uk On 29 June 2011 23:54, rickmangnuarm.g...@arius.com wrote: The transformer allows a DC path to exist on the secondary side, but you still have the capacitor on the primary side of the circuit. If the positive and negative pulse currents are not equal, you will still have a problem on the primary side. You need to remove the cap C1. I still can't tell exactly what is going on in your circuit because you don't provide any labels on the o'scope diagrams. It would also be useful to see current waveforms from the simulations and waveforms from the loads. As was asked for previously, we still have not seen your requirements so I can't tell exactly what you are trying to do with this circuit. How large is the DC offset in the source? Why don't you include that in your simulation model? What voltage do you need out of this supply? I really can't tell what is needed in your design and what is just wrong. Rick On 6/24/2011 7:10 AM, myken wrote: This is strange in my simulation the attached circuit works fine. In real life it kinda works but the signals are distorted like you can see. I think that has something to do with the fact we used a pulse transformer to try the circuit. If we disconnect Vx the signals stay the same, so the distortion is in the transformer. If you say it doesn't work then why doesn't it work? On 22/06/11 22:39, Andy Fierman wrote: Sorry Robert, Both Wojciech and I are wrong. His suggestion about adding a choke is basically the same as mine of using a transformer. The idea of both is to add a dc path to ground at the rectifier inputs. The difference is that the transformer adds DC isolation - which if you include your bandpass filter - you do not need. Sounds like the thing to do but sadly, the simulations show the reality! A choke does not do what you want and neither does a simple 1:1 transformer. However, if you use a 1:1:1 transformer then it all comes together. You can use a transformer with a 1:2 turns ratio, centre tapped and keep to the original half wave rectifier scheme. If you use a three winding transformer of 1:1:1 then you can use two bridge rectifiers. Using bridge rectifiers doubles the ripple frequency so allows lower smoothing C for the same ripple voltage. The attached (not very good quality) pdf shows the non-working choke and 1:1 transformer ideas and the working 1:1:1 transformer versions. Note the 1u smoothing capacitor values. These were reduced to make the simulation reach a steady state sooner than with the original 100uF values. Andy. signality.co.uk On 22 June 2011 01:12, Wojciech Kazubski [1][1]w...@o2.pl wrote: Hello all, I would appreciate some expert advice. I have a system which rectifies a sine wave input signal of 20Khz after a LC filter (see Rectifier_sim.jpeg) Everything works fine if LOAD_1 and LOAD_2 are equal. Vx is then (almost) the same as Vin. And Vcc and Vss are equal to the positive or negative part of the sine wave (less the DC losses) (Vss = -Vin_top and Vcc = Vin_top). BUT if LOAD_1 and LOAD_2 are not equal (like in Rectifier_sim.jpeg) it seems that Vx is lifted (DC component added) and Vss moves to the 0V and Vcc is lifted to twice the
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
The transformer allows a DC path to exist on the secondary side, but you still have the capacitor on the primary side of the circuit. If the positive and negative pulse currents are not equal, you will still have a problem on the primary side. You need to remove the cap C1. I still can't tell exactly what is going on in your circuit because you don't provide any labels on the o'scope diagrams. It would also be useful to see current waveforms from the simulations and waveforms from the loads. As was asked for previously, we still have not seen your requirements so I can't tell exactly what you are trying to do with this circuit. How large is the DC offset in the source? Why don't you include that in your simulation model? What voltage do you need out of this supply? I really can't tell what is needed in your design and what is just wrong. Rick On 6/24/2011 7:10 AM, myken wrote: This is strange in my simulation the attached circuit works fine. In real life it kinda works but the signals are distorted like you can see. I think that has something to do with the fact we used a pulse transformer to try the circuit. If we disconnect Vx the signals stay the same, so the distortion is in the transformer. If you say it doesn't work then why doesn't it work? On 22/06/11 22:39, Andy Fierman wrote: Sorry Robert, Both Wojciech and I are wrong. His suggestion about adding a choke is basically the same as mine of using a transformer. The idea of both is to add a dc path to ground at the rectifier inputs. The difference is that the transformer adds DC isolation - which if you include your bandpass filter - you do not need. Sounds like the thing to do but sadly, the simulations show the reality! A choke does not do what you want and neither does a simple 1:1 transformer. However, if you use a 1:1:1 transformer then it all comes together. You can use a transformer with a 1:2 turns ratio, centre tapped and keep to the original half wave rectifier scheme. If you use a three winding transformer of 1:1:1 then you can use two bridge rectifiers. Using bridge rectifiers doubles the ripple frequency so allows lower smoothing C for the same ripple voltage. The attached (not very good quality) pdf shows the non-working choke and 1:1 transformer ideas and the working 1:1:1 transformer versions. Note the 1u smoothing capacitor values. These were reduced to make the simulation reach a steady state sooner than with the original 100uF values. Andy. signality.co.uk On 22 June 2011 01:12, Wojciech Kazubski [1][1]w...@o2.pl wrote: Hello all, I would appreciate some expert advice. I have a system which rectifies a sine wave input signal of 20Khz after a LC filter (see Rectifier_sim.jpeg) Everything works fine if LOAD_1 and LOAD_2 are equal. Vx is then (almost) the same as Vin. And Vcc and Vss are equal to the positive or negative part of the sine wave (less the DC losses) (Vss = -Vin_top and Vcc = Vin_top). BUT if LOAD_1 and LOAD_2 are not equal (like in Rectifier_sim.jpeg) it seems that Vx is lifted (DC component added) and Vss moves to the 0V and Vcc is lifted to twice the value I would expect (Vss = 0 and Vcc = Vin_toptop) (see rectifiersmp.eps). Our real life prototype shows the same behaviour as the simulation. I need this set-up for my system to work and I can not guarantee that the two loads always will be equal. Vin can be anything between 10Vtt and 90Vtt. I have tried adding a resistor from Vx to ground and that seems to help but increases the current drawn from the source (V1) to a unacceptable level. It should be a low power solution. If I short-circuit C1 everything works fine again (V1 has a low resistance output) but of course will disable the filter, which we don't what. Is there anyone here who can explain to me how and why this is happening and if available can anyone suggest a solution to me. I have been wrestling with this problem for a couple of days now, so any help will be very much appreciated. Many thanks, Robert There is no DC patch from Vx to ground. If both loads are equal, both rectified curreant are equal and cancel one another. If the loads are different, the imbalance current charges Vx node until both output currents become equal again. To avoid this place a choke between Vx and ground. Wojciech Kazubski ___ geda-user mailing list [[2]2]geda-user@moria.seul.org [3][3]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list [[4]4]geda-user@moria.seul.org [5][5]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. [6]mailto:w...@o2.pl 2. [7]mailto:geda-user@moria.seul.org 3. [8]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user 4. [9]mailto:geda-user@moria.seul.org 5. [10]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
The most recent circuit you posted is not the same as your original and as Gene pointed out, you have now made a series resonant circuit between the 220nF cap and the 200uH primary inductance. In the simulation, the source resistance is zero, the ESR of the cap is zero and there is only 0.25R series R and a bit over 500R parallel R (admittedly highly nonlinear) to damp the resonance. This is why the output voltage is so high. The value of output voltages you see in simulation may depend somewhat on exactly how the simulator is set up (and which simulator you use). Gnucap, LTspice and QUCS show rectified output voltages of around 180V for the 500k side output and 153V for the 500R side. I haven't run this in ngspice. A real transformer would have a K 1 but for this level of simulation setting K to 1 instead of 0.999 will significantly speed up the simulation with negligible effect on the output. Setting K to 1 introduces some leakage inductance but at 0.999 this is very small so it has a high resonant frequency with the 220nF input cap. The nonlinearity of the load switching between 500R and 500k through the diodes kicks this into ringing so the simulator spends ages calculating each ring. As Wojciech suggested, if you use an inductor with a much higher value then the resonance drops to well below your band of interest and the output voltages are about where you'd expect. The primary currents also fall dramatically. In your circuit, with an ideal inductor they are about 4.1A rms. Your little pulse transformer probably saturates some way below that current. With a 2mH primary inductance this falls to about 108mA rms. Of course, you then lose the bandpass filter effect of the resonance at 23kHz. The same general discussion applies to if you use a single inductor instead of a 1:1 transformer except of course there is no leakage inductance to worry about. What were the scales on the scope traces you sent? Cheers, Andy. signality.co.uk On 27 June 2011 01:27, Wojciech Kazubski w...@o2.pl wrote: Dnia piątek 24 czerwca 2011 o 13:10:35 myken napisał(a): This is strange in my simulation the attached circuit works fine. In real life it kinda works but the signals are distorted like you can see. I think that has something to do with the fact we used a pulse transformer to try the circuit. If we disconnect Vx the signals stay the same, so the distortion is in the transformer. If you say it doesn't work then why doesn't it work? Probably the transformer has too low inductance for that frequency, it should be in mH range. Magnetizing current I=Uin/(2*pi*f*L) is high and saturates the core so waveforms are not sinusoidal. Wojciech Kazubski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
Dnia piątek 24 czerwca 2011 o 13:10:35 myken napisał(a): This is strange in my simulation the attached circuit works fine. In real life it kinda works but the signals are distorted like you can see. I think that has something to do with the fact we used a pulse transformer to try the circuit. If we disconnect Vx the signals stay the same, so the distortion is in the transformer. If you say it doesn't work then why doesn't it work? Probably the transformer has too low inductance for that frequency, it should be in mH range. Magnetizing currentI=Uin/(2*pi*f*L) is high and saturates the core so waveforms are not sinusoidal. Wojciech Kazubski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
On 06/24/2011 07:10 AM, myken wrote: This is strange in my simulation the attached circuit works fine. In real life it kinda works but the signals are distorted like you can see. I think that has something to do with the fact we used a pulse transformer to try the circuit. If we disconnect Vx the signals stay the same, so the distortion is in the transformer. If you say it doesn't work then why doesn't it work? On 22/06/11 22:39, Andy Fierman wrote: One thing that seems to be a problem, is that you've created a tuned circuit on the primary. L-R-C, series resonant at about 23 kHz, which seems like that's what you were trying to do. The Q is very high, X/R, and R is 0.25 per data sheet. So, you the thing peaks at precisely your source frequency! In my simulation, the output voltage is *huge*, the transformer current is equally high. Try your simulation in the frequency domain as well as the time domain. Regarding your experimental setup - you are probably saturating your core. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
Vcc and Vss are still sensitive to load. So if the design requires both Vss and Vee be equal and opposite, then it needs regulation - zener, for example. Your absolutely right, but that's what comes next. It is the regulators how create the difference in load balance. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
On 06/24/2011 06:10 AM, myken wrote: I think that has something to do with the fact we used a pulse transformer to try the circuit. Looks like a diode drop to me, not transformer problems. You've got a series chain of reactances. You're gonna get oscillations and lagging, leading voltage division. Lose the filtering before rectifying. Make the impedances low at the source, higher and filtered, at the load. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
On 06/22/2011 04:39 PM, Andy Fierman wrote: Vcc and Vss are still sensitive to load. So if the design requires both Vss and Vee be equal and opposite, then it needs regulation - zener, for example. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
Hello all, I would appreciate some expert advice. I have a system which rectifies a sine wave input signal of 20Khz after a LC filter (see Rectifier_sim.jpeg) Everything works fine if LOAD_1 and LOAD_2 are equal. Vx is then (almost) the same as Vin. And Vcc and Vss are equal to the positive or negative part of the sine wave (less the DC losses) (Vss = -Vin_top and Vcc = Vin_top). BUT if LOAD_1 and LOAD_2 are not equal (like in Rectifier_sim.jpeg) it seems that Vx is lifted (DC component added) and Vss moves to the 0V and Vcc is lifted to twice the value I would expect (Vss = 0 and Vcc = Vin_toptop) (see rectifiersmp.eps). Our real life prototype shows the same behaviour as the simulation. I need this set-up for my system to work and I can not guarantee that the two loads always will be equal. Vin can be anything between 10Vtt and 90Vtt. I have tried adding a resistor from Vx to ground and that seems to help but increases the current drawn from the source (V1) to a unacceptable level. It should be a low power solution. If I short-circuit C1 everything works fine again (V1 has a low resistance output) but of course will disable the filter, which we don't what. Is there anyone here who can explain to me how and why this is happening and if available can anyone suggest a solution to me. I have been wrestling with this problem for a couple of days now, so any help will be very much appreciated. Many thanks, Robert There is no DC patch from Vx to ground. If both loads are equal, both rectified curreant are equal and cancel one another. If the loads are different, the imbalance current charges Vx node until both output currents become equal again. To avoid this place a choke between Vx and ground. Wojciech Kazubski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
Ooops, Just missed the Undo Send window ... Typo in (i): if the source has a peak to peak swing of x volts but a dc offset of y then (neglecting the diode drops) vcc = x/2+y and vss = x/2-y. :) Andy On 19 June 2011 11:01, Andy Fierman andyfier...@signality.co.uk wrote: Rick is spot on. However, there are more things you need to consider: i) Does your signal source have a mean DC level of zero? Without C1, if the source has a peak to peak swing of x volts but a dc offset of y then (neglecting the diode drops) vcc = x+y and vss = x-y. If you have to remove a DC offset then you'll have to put a transformer between C1 and the recirfiers. Then C1 keeps DC out of the transformer primary and the transformer secondary provides the necessary dc path for the rectifiers to work as required. ii) I note that C1 and L1 form a series resonant circuit with a centre frequency at about 22.9kHz. So is your source really bandlimited 15kHz - 28kHz by the time it gets to your circuit or are you trying to do the bandpass filtering as part of your circuit? If the latter then you will have to keep C1, L1 but add the transformer as described in (i) above. The you will have to model that transformer to include at least the leakage inductance to get the bandpass response right. Such transformers are not difficult to design and source. iii) What is the source impedance? Does the 8 ohms represent all of your source impedance or is there more hidden in the source itself? You will need to allow for all of it to see how the rectified outputs drop and ripple increases with load current. iv) Don't forget that a SMPS represents a constant power or negative resistance load. As the input voltage drops the current it draws from the source increases. The actual behaviour of a real SMPS is complicated by any input undervoltage lockout and soft start features. This may or may not play well with your source. I'd like to make a general point here. This isn't a criticism but an important observation: when asking a question about how to do something, it saves everyone a lot of time, guesswork and blind alleys if the problem that is to be solved is clearly stated alongside whatever attempt at a solution that the specific question may be about. Essentially, include the design specification in the original question otherwise no-one knows the whole story so the question doesn't get a proper answer in a timely manner. Clearly in some instances the design spec may not be something that can be given openly but usually the part relevant to a question can be reframed so as to not give away too much. However, there has to be enough information so that the boundaries of the problem in question can be understood. This question is a classic example. Several people have discussed removing a part of the circuit that I now strongly suspect (C1 and L1) is an essential (if inappropriately implemented) part of the circuit because it wasn't clear what the overall function or scope of the circuit was. Cheers, Andy. signality.co.uk On 18 June 2011 21:19, rickman gnuarm.g...@arius.com wrote: What is the purpose of C1 and L1? If you want to filter anything, it should be AFTER you rectify the signal to DC. A series cap is going to remove low frequencies... like DC which is attenuated very highly. So much in fact that you can't draw a DC signal through a capacitor. That is why your circuit is not working. If you remove C1 and L1 the circuit will work the way you want it to I believe. Also, with an input frequency of 15 kHz or higher, you won't be needing 100 uF output filter capacitors for a light load. How many mA is your load? How much ripple can you allow? Use those two values to calculate the value of output filter capacitor you need. Once I fix your circuit by removing the input filter I measure 19.14 volts out and 38.2 mA of current into a 500 ohm load. Is that what you are shooting for? The 100 uF cap gives around 10 mV of ripple. With lighter loads or more ripple the cap can be smaller. Rick On 6/17/2011 4:44 AM, myken wrote: Yeap, it should be a very low power power supply. Vx is not important Vcc and Vss are. Vin can be anything from 15Khz to 28Khz so a transformer is not the most desired option. I have designed two SMPS for Vcc and Vss but there load to the rectifier are not the same, with the described result. I will try the options suggested in this list today. Robert. On 17/06/11 04:13, gene glick wrote: On 06/16/2011 02:30 PM, myken wrote: Hello all, I would appreciate some expert advice. Are you trying to make a low current power supply? I agree with DJ - the unequal loading on + and - cycle will average to something other than zero (unequal capacitors, unequal diodes, etc) If Vx must always be average zero - you'll need to do something else. If you can handle a little voltage drop, don't care what happens to
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
Hello all, As a remark on your observation Andy I would like to say in my defence that I simplified and reduced the problem/information simply to avoid wasting anyones time with details and (in my opinion) irrelevant side effects. That the two load resistors are in fact a representation of two complete sub-systems is in my opinion not relevant to the question I was asking. But maybe that was a mistake. Nevertheless I got very very great and useful feedback from this list with the information I provided. I decided that I need C1 to eliminate any DC component from the input signal and the hits for using a transformer has let me to understand my error in thinking. It was never my intention to waste anyone time by holding back information but it was my intention not to waste anyone's time by reducing the number of details ;-) What I should do in the future is be more clear about the kind of information I would like to get from this list. a. complete design b. detailed design solution c. tutorial on electronics d. coffee-machine feedback I was looking for the last one, just some feedback from other professionals to get me on track to a solution. And that's what I got, in our situation the solution is to use a transformer, thanks everyone! Cheers, Robert. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
What is the purpose of C1 and L1? If you want to filter anything, it should be AFTER you rectify the signal to DC. A series cap is going to remove low frequencies... like DC which is attenuated very highly. So much in fact that you can't draw a DC signal through a capacitor. That is why your circuit is not working. If you remove C1 and L1 the circuit will work the way you want it to I believe. Also, with an input frequency of 15 kHz or higher, you won't be needing 100 uF output filter capacitors for a light load. How many mA is your load? How much ripple can you allow? Use those two values to calculate the value of output filter capacitor you need. Once I fix your circuit by removing the input filter I measure 19.14 volts out and 38.2 mA of current into a 500 ohm load. Is that what you are shooting for? The 100 uF cap gives around 10 mV of ripple. With lighter loads or more ripple the cap can be smaller. Rick On 6/17/2011 4:44 AM, myken wrote: Yeap, it should be a very low power power supply. Vx is not important Vcc and Vss are. Vin can be anything from 15Khz to 28Khz so a transformer is not the most desired option. I have designed two SMPS for Vcc and Vss but there load to the rectifier are not the same, with the described result. I will try the options suggested in this list today. Robert. On 17/06/11 04:13, gene glick wrote: On 06/16/2011 02:30 PM, myken wrote: Hello all, I would appreciate some expert advice. Are you trying to make a low current power supply? I agree with DJ - the unequal loading on + and - cycle will average to something other than zero (unequal capacitors, unequal diodes, etc) If Vx must always be average zero - you'll need to do something else. If you can handle a little voltage drop, don't care what happens to Vx, and don't mind adding a few parts, make a cheapo regulator with a zener and BJT? (Or maybe use TL31 instead of zener) What about a small transformer, one winding on primary, center tapped on secondary. Add a diode and a cap for each leg - and there you go! Anyway, there's lots of ways to do this. If regulated output is what you want, a little more work is required. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
Yeap, it should be a very low power power supply. Vx is not important Vcc and Vss are. Vin can be anything from 15Khz to 28Khz so a transformer is not the most desired option. I have designed two SMPS for Vcc and Vss but there load to the rectifier are not the same, with the described result. I will try the options suggested in this list today. Robert. On 17/06/11 04:13, gene glick wrote: On 06/16/2011 02:30 PM, myken wrote: Hello all, I would appreciate some expert advice. Are you trying to make a low current power supply? I agree with DJ - the unequal loading on + and - cycle will average to something other than zero (unequal capacitors, unequal diodes, etc) If Vx must always be average zero - you'll need to do something else. If you can handle a little voltage drop, don't care what happens to Vx, and don't mind adding a few parts, make a cheapo regulator with a zener and BJT? (Or maybe use TL31 instead of zener) What about a small transformer, one winding on primary, center tapped on secondary. Add a diode and a cap for each leg - and there you go! Anyway, there's lots of ways to do this. If regulated output is what you want, a little more work is required. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
Simply reproducing the filter twice, one for each polarity of rectifier will not work. If you can float the load or the source then splitting the circuit into two and using a bridge rectifier in each will work OK. The attached shows what I mean. Cheers, Andy. www.signality.co.uk On 16 June 2011 23:05, myken my...@iae.nl wrote: Thanks DJ, I had the same thought that Vx was floating somewhere unwanted, that's why I added the resistor (which didn't work). Gazing at this problem for a couple of days make me miss the obvious, just split the filter. Brilliant. I'll give it a try. Robert. On 16/06/11 20:48, DJ Delorie wrote: When you put two capacitors in series, there's no way to know what the voltage between them will be. You have three with a common central connection Vx. V1 acts to charge the node, the loads act to discharge it, so an unequal load means unequal discharging and thus nonzero average node voltage. Since D1 and D2 may have different average currents through them, Vx will adjust until the average current through R2 is the same as the net current throuth the two diodes. Can you split the filter into two filters, one for each load? or at least move C1 to the Vx side of the filter, and split it into two capacitors? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user rects_01.pdf Description: Adobe PDF document ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
On 06/16/2011 02:30 PM, myken wrote: Hello all, I would appreciate some expert advice. Are you trying to make a low current power supply? I agree with DJ - the unequal loading on + and - cycle will average to something other than zero (unequal capacitors, unequal diodes, etc) If Vx must always be average zero - you'll need to do something else. If you can handle a little voltage drop, don't care what happens to Vx, and don't mind adding a few parts, make a cheapo regulator with a zener and BJT? (Or maybe use TL31 instead of zener) What about a small transformer, one winding on primary, center tapped on secondary. Add a diode and a cap for each leg - and there you go! Anyway, there's lots of ways to do this. If regulated output is what you want, a little more work is required. gene ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
When you put two capacitors in series, there's no way to know what the voltage between them will be. You have three with a common central connection Vx. V1 acts to charge the node, the loads act to discharge it, so an unequal load means unequal discharging and thus nonzero average node voltage. Since D1 and D2 may have different average currents through them, Vx will adjust until the average current through R2 is the same as the net current throuth the two diodes. Can you split the filter into two filters, one for each load? or at least move C1 to the Vx side of the filter, and split it into two capacitors? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
On 06/16/2011 01:30 PM, myken wrote: see Rectifier_sim.jpeg) Everything works fine if LOAD_1 and LOAD_2 are equal. Lose C1. Lose R1. Add L2 feeding D1. Separate D1 D2. Add some rc filter R between D2, C2. Or try moving L1 between D2, C2 John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: OT: help needed; asymmetric load after rectifier seems to disrupt its working.
Thanks DJ, I had the same thought that Vx was floating somewhere unwanted, that's why I added the resistor (which didn't work). Gazing at this problem for a couple of days make me miss the obvious, just split the filter. Brilliant. I'll give it a try. Robert. On 16/06/11 20:48, DJ Delorie wrote: When you put two capacitors in series, there's no way to know what the voltage between them will be. You have three with a common central connection Vx. V1 acts to charge the node, the loads act to discharge it, so an unequal load means unequal discharging and thus nonzero average node voltage. Since D1 and D2 may have different average currents through them, Vx will adjust until the average current through R2 is the same as the net current throuth the two diodes. Can you split the filter into two filters, one for each load? or at least move C1 to the Vx side of the filter, and split it into two capacitors? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
