Re: gEDA-user: Open VHDL Simulators?
Hello. Am 29.04.2008 um 01:23 schrieb Stephen Williams: Attila Kinali wrote: On Sat, 26 Apr 2008 09:22:17 +0200 Hagen SANKOWSKI [EMAIL PROTECTED] wrote: Mostly bad VHDL design goes to FPGA, good Verilog design goes to ASICs. Uhm... I don't think i have to comment on something uneducated like this, do i? Right, let's please not fall into this pit. I was hoping the mud would dry up and blow away. Sorry, I don't want to put up a pit. Just a moody observation over the years... Regards, hsank ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open VHDL Simulators?
On Fri, 25 Apr 2008 14:04:38 -0700 Stephen Williams [EMAIL PROTECTED] wrote: As you know, this year's Icarus Verilog GSoC candidate is working on a VHDL code generator back-end for Icarus Verilog. Hooray! But suddenly the obvious question comes up, How are we going to run these generated files? I'm here looking for suggestions. After rethinking about this. What speaks against adding a VHDL front-end to Icarus? VHDL and Verilog are feature wise very similar and those few differences are not that difficult. As a special benefit it would give us the first OSS simulator with both VHDL and Verilog support. There are GPL'ed VHDL yacc/bison definitions out there which could be reused. And even if not, writing one is just typing down the definitions. If someone would take up this task, i'd donate the current VHDL standards and Ashenden's execellent book on VHDL[1]. Attila Kinali [1] http://www.ashenden.com.au/designers-guide/DG.html -- Praised are the Fountains of Shelieth, the silver harp of the waters, But blest in my name forever this stream that stanched my thirst! -- Deed of Morred ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open VHDL Simulators?
Attila Kinali wrote: On Fri, 25 Apr 2008 14:04:38 -0700 Stephen Williams [EMAIL PROTECTED] wrote: As you know, this year's Icarus Verilog GSoC candidate is working on a VHDL code generator back-end for Icarus Verilog. Hooray! But suddenly the obvious question comes up, How are we going to run these generated files? I'm here looking for suggestions. After rethinking about this. What speaks against adding a VHDL front-end to Icarus? VHDL and Verilog are feature wise very similar and those few differences are not that difficult. As a special benefit it would give us the first OSS simulator with both VHDL and Verilog support. There are GPL'ed VHDL yacc/bison definitions out there which could be reused. And even if not, writing one is just typing down the definitions. If someone would take up this task, i'd donate the current VHDL standards and Ashenden's execellent book on VHDL[1]. Attila Kinali [1] http://www.ashenden.com.au/designers-guide/DG.html has anyone looked at tyvis/warped from clifton labs? -Dan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open VHDL Simulators?
Attila Kinali wrote: On Fri, 25 Apr 2008 14:04:38 -0700 Stephen Williams [EMAIL PROTECTED] wrote: As you know, this year's Icarus Verilog GSoC candidate is working on a VHDL code generator back-end for Icarus Verilog. Hooray! But suddenly the obvious question comes up, How are we going to run these generated files? I'm here looking for suggestions. After rethinking about this. What speaks against adding a VHDL front-end to Icarus? VHDL and Verilog are feature wise very similar and those few differences are not that difficult. As a special benefit it would give us the first OSS simulator with both VHDL and Verilog support. It's not so obvious how that would work, or even whether it would be a good idea. One possibility might be to have e.g. the freehdl compiler generate vvp output, but would that be of use to anyone? Currently, vvp doesn't do any kind of linking, but if it did support linking, and if there is a VHDL compiler that can generate vvp code, then that could lead to a mixed language simulator, but the vvp semantics may not be a good match for VHDL. Anyhow, the parsing of VHDL is actually relatively easy, things get exciting when elaboration happens. That's where most of the VHDL complexity lives. That is to some degree true of Verilog as well, and most of the Icarus Verilog compiler is parse and elaborate. The code generator parts are a small part of the tool itself. I have a copy of 1076-1993 already. I got it when I was deciding which (Verilog or VHDL) to do. It's kinda dusty at the moment. If someone really wants to pursue this from the development perspective, then iverilog-devel at lists.sourceforge.net is where Icarus Verilog development talk happens. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open VHDL Simulators?
On Sat, 26 Apr 2008 09:22:17 +0200 Hagen SANKOWSKI [EMAIL PROTECTED] wrote: As a freelancer now 10 years in business I work nearly on a every day basis with *both* languages, Verilog HDL and VHDL. In general, I see two trends. First, the serious and bigger the SoC design, the often companies probably use Verilog instead of VHDL. So the offer with language knowledge for Verilog or VHDL is even a good indication of ambitions. Second, with SystemVerilog and all the released sources for the Sparcs and PowerPC the Verilog camp overruns the more european and academic design villages. For me the development of VHDL slows down in general while SystemVerilog eats the market for dedicated Verification languages. Where do you work? Because here in Europe, companies still use mostly VHDL. Verilog skils don't go very far. Mostly bad VHDL design goes to FPGA, good Verilog design goes to ASICs. Uhm... I don't think i have to comment on something uneducated like this, do i? So please Steve, keep your attention on Verilog, 'a cobbler should stick to his last'. And, btw. you did a great job with icarus :-) Thanks! If you want support VHDL, than be aware that the VHDL language is more hugh than Verilog with even millions of pitfalls and ways to describe one behavior. Eh.. VHDL is huge, yes (actually the largest language i know), but at least it has a clean design, compared to Verilog which looks like someone tried to hammer C into a form that it can simulate hardware too. In number of pitfalls and ambiguities, i think Verilog is worse. Especialy if you consider that certain Verilog constructs differ only in one character, but have very sublte different meanings. A very good way for hard to trace down typos. ghdl and freehdl are light years away from quality of icarus. Yet, i got ghdl running and simulating within minutes while it took me half a day to figure out why icarus wasn't. But yes, ghdl and freehdl are far a away from being feature complete, though i don't think that was the question here. Attila Kinali -- Praised are the Fountains of Shelieth, the silver harp of the waters, But blest in my name forever this stream that stanched my thirst! -- Deed of Morred ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open VHDL Simulators?
Stephen Williams wrote: [...] Has anybody here used ghdl? freehdl? Relative merits? Which is most active? The most portable? Easiest to use? It just seems like ghdl has the most activity associated with it, but FreeHDL doesn't look completely dead either. So what to choose? For openSUSE you can find RPM packages of both simulators through: http://software.opensuse.org/search Both packages have source packages available and I believe it should be fairly simple to use those and compile a package for a different distribution. Although I did create the ghdl package, I only tested it with a simple VHDL example. So I cannot comment on how feature rich it is. Before creating the RPM I had installed it from source on one of my computers. What I always found to be a hassle to figure out is to get the correct version of ADA compiler. Guenter ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open VHDL Simulators?
al davis wrote: On Friday 25 April 2008, Stephen Williams wrote: As you know, this year's Icarus Verilog GSoC candidate is working on a VHDL code generator back-end for Icarus Verilog. Hooray! But suddenly the obvious question comes up, How are we going to run these generated files? I'm here looking for suggestions. What you need is the ability to translate the other way too. That way, you can go around the loop and see if you get equivalent Verilog back. Going both ways has another obvious benefit. We would get real VHDL support too. I fully agree. That would be awesome if along with the Verilog-VHDL converter there would be a VHDL-Verilog converter for the same feature set. When converting Verilog code to VHDL, chances are that there is a test bench already available in Verilog. So instead of converting this test bench as well, it would make more sense to keep that test bench and verify the VHDL based on the converted Verilog code. However, I do understand that in order to get matching Verilog-VHDL relationship there is the need during development to verify VHDL. I am not sure whether this fits here, there is Python project called MyHDL and it allows to convert Python code to Verilog. With the latest development snapshot the author Jan Decaluwe added a conversion from Python to VHDL. You can read about that under: http://myhdl.jandecaluwe.com/doku.php/dev:whatsnew:0.6 With the toVerilog conversion, co-simulation trough the PLI interface is used to verify the created Verilog code with the Python test bench. With the toVHDL conversation he could not use co-simulation and instead did some toVHDL conversation of the test bench code as well. Maybe his thoughts are of some help here. You will also find posts on comp.lang.vhdl from him about problems he ran into with the toVHDL conversion. That might be of some help for the student working on the VHDL converter. Now, Jan did not go that route, but, GHDL has some PLI interface support. It seems like there has been some work in ADA on that, but there is also some C or C++ code for that. At least I was reading about that in the GHDL mailing list archive some time ago. There is a IEEE paper about using GHDL in connection with SystemC via the PLI: A Methodology and Toolset to Enable SystemC and VHDL Co-simulation Maciel, R.; Albertini, B.; Rigo, S.; Araujo, G.; Azevedo, R. VLSI, 2007. ISVLSI apos;07. IEEE Computer Society Annual Symposium on Volume , Issue , 9-11 March 2007 Page(s):351 - 356 Maybe that is of any help here. Cheers, Guenter ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open VHDL Simulators?
Attila Kinali wrote: On Sat, 26 Apr 2008 09:22:17 +0200 Hagen SANKOWSKI [EMAIL PROTECTED] wrote: Mostly bad VHDL design goes to FPGA, good Verilog design goes to ASICs. Uhm... I don't think i have to comment on something uneducated like this, do i? Right, let's please not fall into this pit. I was hoping the mud would dry up and blow away. -- Steve WilliamsThe woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open VHDL Simulators?
On Monday 28 April 2008, Stephen Williams wrote: Mostly bad VHDL design goes to FPGA, good Verilog design goes to ASICs. Uhm... I don't think i have to comment on something uneducated like this, do i? Right, let's please not fall into this pit. I was hoping the mud would dry up and blow away. That's one of the reasons for the gnucap language plugins. The simulator core is completely neutral to the language. The snapshot has Spice, Spectre, and Verilog. VHDL should be easy, and will happen. This is the structural subset, primarily analog. Behavioral modeling is in plugins. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open VHDL Simulators?
Hello. Am 25.04.2008 um 23:04 schrieb Stephen Williams: As you know, this year's Icarus Verilog GSoC candidate is working on a VHDL code generator back-end for Icarus Verilog. Hooray! But suddenly the obvious question comes up, How are we going to run these generated files? I'm here looking for suggestions. Has anybody here used ghdl? freehdl? Relative merits? Which is most active? The most portable? Easiest to use? It just seems like ghdl has the most activity associated with it, but FreeHDL doesn't look completely dead either. So what to choose? Well, I used ghdl some yeas back for a small project and was surprised of the instability. The simulation failed with obivous error messages. For ghdl I see the pitfall of design at close relationship between ghdl and a dedicated (old fashioned) version of GCC. Freehdl doesn't compile on my box. As a freelancer now 10 years in business I work nearly on a every day basis with *both* languages, Verilog HDL and VHDL. In general, I see two trends. First, the serious and bigger the SoC design, the often companies probably use Verilog instead of VHDL. So the offer with language knowledge for Verilog or VHDL is even a good indication of ambitions. Second, with SystemVerilog and all the released sources for the Sparcs and PowerPC the Verilog camp overruns the more european and academic design villages. For me the development of VHDL slows down in general while SystemVerilog eats the market for dedicated Verification languages. Mostly bad VHDL design goes to FPGA, good Verilog design goes to ASICs. So please Steve, keep your attention on Verilog, 'a cobbler should stick to his last'. And, btw. you did a great job with icarus :-) Thanks! If you want support VHDL, than be aware that the VHDL language is more hugh than Verilog with even millions of pitfalls and ways to describe one behavior. ghdl and freehdl are light years away from quality of icarus. Your code generator at the moment supports EDIF, right? So why you don't use Verilog itself again? This will be a good starting point for netlist-based timing simulations with rising SDF support. If you are in need of the Verilog to VHDL translation, keep an eye on this dedicated tools, they works fine. And keep the Unix philosophy, one tool should do one thing, but this one great. If there is one Verilog lover or programmer with spare time, I still miss a better quality for Coverage and even a Lint tool for Verilog.. Regards hsank ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open VHDL Simulators?
On Fri, 25 Apr 2008 14:04:38 -0700 Stephen Williams [EMAIL PROTECTED] wrote: As you know, this year's Icarus Verilog GSoC candidate is working on a VHDL code generator back-end for Icarus Verilog. Hooray! But suddenly the obvious question comes up, How are we going to run these generated files? I'm here looking for suggestions. Has anybody here used ghdl? freehdl? Relative merits? Which is most active? The most portable? Easiest to use? It just seems like ghdl has the most activity associated with it, but FreeHDL doesn't look completely dead either. So what to choose? I tried ghdl once or twice in the past (many many years back) and am still lurking on its mailinglist. Development seems to have slown down recently, but has still some progress. (i guess it's because it's mostly feature complete for the author). I've never gotten freehdl working when i tried to use (around the same time as ghdl). And never heard of it since. HTH Attila Kinali -- The true CS students do not need to know how to program. They learn how to abstract the process of programming to the point of making programmers obsolete. -- Jabber in #holo ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: Open VHDL Simulators?
On Friday 25 April 2008, Stephen Williams wrote: As you know, this year's Icarus Verilog GSoC candidate is working on a VHDL code generator back-end for Icarus Verilog. Hooray! But suddenly the obvious question comes up, How are we going to run these generated files? I'm here looking for suggestions. What you need is the ability to translate the other way too. That way, you can go around the loop and see if you get equivalent Verilog back. Going both ways has another obvious benefit. We would get real VHDL support too. On Friday 25 April 2008, Stephen Williams wrote: It just seems like ghdl has the most activity associated with it, but FreeHDL doesn't look completely dead either. So what to choose? Another case of free projects not working together. FreeHDL is hosted at seul.org, but seems to have the closest ties with qucs. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
