Re: gEDA-user: An idea: rework design support...
On May 14, 2011, at 11:08 PM, DJ Delorie wrote: > >> To counter that.. I see no compelling reason to keep it though. > > We'll need it more when we add layer types. Real physical layers have material properties, thickness, and perhaps others. They don't have "types". > >> Given we'll probably end up keeping the irksome things, can we swap the >> terminology around? > > Yup. I think we decided "sheets" was the best term for what is now > known as "layers". Sheets are "views" of the design. They are not a direct representation of the physical structure. They are derived data, not fundamental. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: An idea: rework design support...
> To counter that.. I see no compelling reason to keep it though. We'll need it more when we add layer types. > Given we'll probably end up keeping the irksome things, can we swap the > terminology around? Yup. I think we decided "sheets" was the best term for what is now known as "layers". ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: An idea: rework design support...
On 05/14/2011 05:47 PM, Peter Clifton wrote: On Sat, 2011-05-14 at 13:56 -0400, DJ Delorie wrote: > > I do not have a problem with the idea of single layer per physical > > layer, > > PCB uses a single layer group per physical layer, with one or more > drawing layers within each group. I see no reason to dump that now. > We just need to work on the UI and terminology so that it's less > confusing how it all works together. To counter that.. I see no compelling reason to keep it though. Certainly if we were to add the ability to tag objects and change viewing styles based upon tags. Given we'll probably end up keeping the irksome things, can we swap the terminology around? Physical PCB layer, mechanical drawing etc.. WAS: "Layer group" -> TO-BECOME: "Layer" I'd like if the name was less ambiguous... as in: "Layer group" -> "Stackup_Layer" or "Physical_layer" which would require changing how outline is done -- like John Doty suggested. As is, the terminology makes people that use gimp or photoshop or inkscape think of image or drawing layers that can be arranged in any order. John Griessen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: An idea: rework design support...
On May 14, 2011, at 4:47 PM, Peter Clifton wrote:
> On Sat, 2011-05-14 at 13:56 -0400, DJ Delorie wrote:
>>> I do not have a problem with the idea of single layer per physical
>>> layer,
>>
>> PCB uses a single layer group per physical layer, with one or more
>> drawing layers within each group. I see no reason to dump that now.
>> We just need to work on the UI and terminology so that it's less
>> confusing how it all works together.
>
> To counter that.. I see no compelling reason to keep it though.
> Certainly if we were to add the ability to tag objects and change
> viewing styles based upon tags.
It goes deeper than tags. It goes deeper than "UI and terminology", although
the abuse of terminology is a symptom ("polygons" are not simple geometric
figures, "elements" are not elementary, ...). The key thing that's missing is
the idea that complex things are composed of simpler things. Circuits composed
of subcircuits composed of footprints and nets, ...
Instead, there's a kludgy collection of magical objects. This is not only
confusing to users, but it makes users unnecessarily dependent on the
developers. Users should be able to define whatever composite objects they
need, rather than be restricted to the limited built-in set. And the necessity
to keep implementing magical objects from an open-ended list, and to insure
that they all play nicely together, are unnecessary burdens on the developers.
> Given we'll probably end up keeping the irksome things, can we swap the
> terminology around?
>
> Physical PCB layer, mechanical drawing etc..
>
> WAS: "Layer group" -> TO-BECOME: "Layer"
>
> Alternative terminology might be "foil" or "artwork", depending on
> context.
The material (copper, teflon, nichrome, ink, ...) that the elementary objects
in a layer are made of is simply a property of the layer, I think.
>
>
> Logical group for partitioning geometry within a given PCB layer
>
> WAS: "Layer" -> TO-BECOME: "object group" | "sub-layer" |
Composite objects generally occupy multiple physical layers. So, shoehorning
them into "layers" is confusing and unnatural.
---
John Doty Noqsi Aerospace, Ltd.
This message contains technical discussion involving difficult issues. No
personal disrespect or malice is intended. If you perceive such, your
perception is simply wrong. I'm a busy person, and in my business "go along to
get along" causes mission failures and sometimes kills people, so I tend to be
a bit blunt.
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Re: gEDA-user: An idea: rework design support...
On Sat, 2011-05-14 at 13:56 -0400, DJ Delorie wrote: > > I do not have a problem with the idea of single layer per physical > > layer, > > PCB uses a single layer group per physical layer, with one or more > drawing layers within each group. I see no reason to dump that now. > We just need to work on the UI and terminology so that it's less > confusing how it all works together. To counter that.. I see no compelling reason to keep it though. Certainly if we were to add the ability to tag objects and change viewing styles based upon tags. Given we'll probably end up keeping the irksome things, can we swap the terminology around? Physical PCB layer, mechanical drawing etc.. WAS: "Layer group" -> TO-BECOME: "Layer" Alternative terminology might be "foil" or "artwork", depending on context. Logical group for partitioning geometry within a given PCB layer WAS: "Layer" -> TO-BECOME: "object group" | "sub-layer" | Our current "layers" within a "layer group" are what an SVG or general graphics editor might call "layers" to describe the way they build up to make a single drawing (in this case of a physical PCB layer), but as such, the term is too overloaded for us to use here. What these sub-layers actually do is group drawing primitives so they can be coloured differently. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: An idea: rework design support...
On May 14, 2011, at 2:31 PM, DJ Delorie wrote: > >> No, it does not. There is no 1-1 relationship between pcb layers and >> physical layers. > > Yes, there is. You just have a different interpretation of the word > "layers" than the rest of us. My interpretation corresponds to the normal meaning of the word "layer". It is simply based on geometry. DJ, this is why we can't discuss anything. Good software needs to be based on clean concepts, not a tangle of epicycles. --- John Doty Noqsi Aerospace, Ltd. This message contains technical discussion involving difficult issues. No personal disrespect or malice is intended. If you perceive such, your perception is simply wrong. I'm a busy person, and in my business "go along to get along" causes mission failures and sometimes kills people, so I tend to be a bit blunt. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: An idea: rework design support...
> No, it does not. There is no 1-1 relationship between pcb layers and > physical layers. Yes, there is. You just have a different interpretation of the word "layers" than the rest of us. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: An idea: rework design support...
On May 14, 2011, at 11:56 AM, DJ Delorie wrote: > >> I do not have a problem with the idea of single layer per physical >> layer, > > PCB uses a single layer group per physical layer, No, it does not. There is no 1-1 relationship between pcb layers and physical layers. Examples: The insulating layers are missing, although their geometry and physical properties matter. The outline "layer" corresponds to a relationship between the geometries of physical layers. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: An idea: rework design support...
> I do not have a problem with the idea of single layer per physical > layer, PCB uses a single layer group per physical layer, with one or more drawing layers within each group. I see no reason to dump that now. We just need to work on the UI and terminology so that it's less confusing how it all works together. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: An idea: rework design support...
Peter Clifton writes: > FWIW, I'd love to see PCB's enforce one "layer" per "layer" of the > board, tagging objects if necessary to implement similar functionality > to what we currently use "layers" and "layer groups" for. One layer per physical layer would imply that element pins (pads) are tagged shapes in this single layer too? And negative shapes as well? So each object (shape) on the layer needs a stacking order tag (implying sublayers), or shall each negative shape take precedence over positive shapes? > Mechanical drawing overlays could still sensibly be called "layers", > even if they are quite distinct from the physical representation of the > PCB board. I do not have a problem with the idea of single layer per physical layer, as long as the end result is no more than a separation of the plane in two subsets, all layers can be manipulated othogonally in the same way (at least with a text editor), and there are not too many assumtions about the semantics of the resulting layers. The tags on the objects that define the layers have several distinct purposes: - how does this object affect the plane (positive, negative, positive with clearance, stacking order, ...) - where did this object come from (routing, element pin, ...) - how may this object be modified (locked, grouped, ...) - verification (design rules, ...) - connectivity (vias, antenna, ...) - ... - user attributes Some of these tags exist today, some are requested features, some depend on what gets picked up from the long discussion we had a few months back. -- Stephan ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: An idea: rework design support
On Fri, 2011-05-13 at 11:16 -0700, Ouabache Designworks wrote: > Would it be useful. Yes >Would it be easy No. Indeed not. I was thinking you would work from the schematic first anyway, so you make a break where you want it on the schematic, then correct the PCB. PCB can already verify that you have got the correct connevtivity, so the worries below are not a big problem. True, until you've made the break track annotation(s), PCB would regard your board as shorting two nets together. We could really use some improvement in the way we locate probable locations for nets shorted against each other anyway though. >When you cut a trace you might split a node into two nodes. Or then >again you might not if there is a loop on the PCB. You would need to >extract connectivity from the layout to be sure. The cut on the PCB is >unlikely to map to a nice easy spot on the schematic where you could >make the equivalent cut. You may wind up having to redraw the >schematic. Netlist extraction from the PCB is possible with a little effort, but I was thinking of a schematic -> PCB flow here, not back-annotating board changes to the schematic. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: An idea: rework design support...
On Fri, 2011-05-13 at 11:09 -0600, John Doty wrote: > In ancient Greek astronomy, when the theory of planetary motion didn't > fit the data, they added "epicycles". "Layers" have become pcb's > epicycles: every time somebody wants a "feature", they propose a new > kind of layer. FWIW, I'd love to see PCB's enforce one "layer" per "layer" of the board, tagging objects if necessary to implement similar functionality to what we currently use "layers" and "layer groups" for. Mechanical drawing overlays could still sensibly be called "layers", even if they are quite distinct from the physical representation of the PCB board. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: An idea: rework design support
Would it be useful. Yes Would it be easy No. When you cut a trace you might split a node into two nodes. Or then again you might not if there is a loop on the PCB. You would need to extract connectivity from the layout to be sure. The cut on the PCB is unlikely to map to a nice easy spot on the schematic where you could make the equivalent cut. You may wind up having to redraw the schematic. John Eaton ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: An idea: rework design support...
On May 13, 2011, at 7:10 AM, Peter Clifton wrote: > Hi everyone, > > I just thought I'd document this idea in order to get some feedback. I > have no time to implement it for the foreseeable future, but it might > provide someone inspiration to get hacking on PCB. > > I sometimes find myself working within a particular generation of > prototype board, wanting to modify it in order to chance aspects of the > circuitry. > > I'm fairly confident this is a common task, since it is rare that a > prototype will work perfectly first time and NOT require modification, > nor would the designer always send a new spin of the board for > manufacture in order to test modifications which could be tested by > rework. > > > Rework may involve leaving components off the board, fitting blue-wires, > lifting pins or cutting traces. It may also involve adding components > "dead bug" style. > > Managing the build state and netlist of a reworked board is tedious > manual work. We should ideally support: > > 1. Updating schematics with changes (perhaps having a way to grey out or > dot-dash draw omitted components). > > 2. Forward those changes into PCB Two pieces here, that *must* be kept cleanly separated: A. To gnetlist, add a facility to allow a back end to figure this out. B. To gnet-pcb.scm, add the code to use such a facility. > > 3. Annotate on a "rework" layer (or layers), where modifications take > place to the board. In ancient Greek astronomy, when the theory of planetary motion didn't fit the data, they added "epicycles". "Layers" have become pcb's epicycles: every time somebody wants a "feature", they propose a new kind of layer. This pollutes the fundamental geometric significance of layers. It entangles design capture, geometry, and design export in complex and confusing ways. Geometry, composition, and constraint are different things and deserve fundamentally different mechanisms. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: An idea: rework design support...
On Fri, 2011-05-13 at 09:01 -0500, John Griessen wrote: > On 05/13/2011 08:10 AM, Peter Clifton wrote: > > Comments? > > Sounds close to the approach of Fritzing, where wiring is documented > as literal wires put in a plug-board. Your concept is different only > in keeping the as built prototype as a reference -- no plug-board. Good point ;) It could also be used to design plug-board layouts if your reference board was a model of the vero-board / plug board you were using. Not strictly a "PCB" any more, but I'm excited about the possibility of documenting one-off or prototype designs like this. This (and the blue-wire layers) would probably be similar to the kind of primitives we might require to add support for designing in arbitrary length wire-jumpers at PCB design time, rather than requiring schematic components with footprints for them. This would be very handy for people designing single layer (and some two-layer) boards. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: An idea: rework design support...
On 05/13/2011 08:10 AM, Peter Clifton wrote: Comments? Sounds close to the approach of Fritzing, where wiring is documented as literal wires put in a plug-board. Your concept is different only in keeping the as built prototype as a reference -- no plug-board. One step of getting the omitted components documented would be to reduce the instances of footprints to traces of the same shape, with no footprint data associated. Your concept of showing overlapping layers that do not create connectivity can be stated like this also: Create a second board, or daughter board view, with viewing similar to far side, but maybe in a less saturated view with colors instead of grey, which also creates a longer layer list where visibility can be turned on or off. You would also want a way to swap which board is the reference mother or daughter board, so you could focus on one or the other at a time. John -- EcosensoryAustin TX ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: An idea: rework design support...
I would definitely use this. I typically maintain a document of all patches whilst I'm bringing up the PCB for technicians to use then I use it myself to modify pcb/schematics. On Fri, May 13, 2011 at 2:10 PM, Peter Clifton wrote: > Hi everyone, > > I just thought I'd document this idea in order to get some feedback. I > have no time to implement it for the foreseeable future, but it might > provide someone inspiration to get hacking on PCB. > > I sometimes find myself working within a particular generation of > prototype board, wanting to modify it in order to chance aspects of the > circuitry. > > I'm fairly confident this is a common task, since it is rare that a > prototype will work perfectly first time and NOT require modification, > nor would the designer always send a new spin of the board for > manufacture in order to test modifications which could be tested by > rework. > ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: An idea: rework design support...
Hi everyone, I just thought I'd document this idea in order to get some feedback. I have no time to implement it for the foreseeable future, but it might provide someone inspiration to get hacking on PCB. I sometimes find myself working within a particular generation of prototype board, wanting to modify it in order to chance aspects of the circuitry. I'm fairly confident this is a common task, since it is rare that a prototype will work perfectly first time and NOT require modification, nor would the designer always send a new spin of the board for manufacture in order to test modifications which could be tested by rework. Rework may involve leaving components off the board, fitting blue-wires, lifting pins or cutting traces. It may also involve adding components "dead bug" style. Managing the build state and netlist of a reworked board is tedious manual work. We should ideally support: 1. Updating schematics with changes (perhaps having a way to grey out or dot-dash draw omitted components). 2. Forward those changes into PCB 3. Annotate on a "rework" layer (or layers), where modifications take place to the board. Rework layers depicting wiring would support curvilinear free-form routing, where overlaps don't cause short-circuits. Rework layers depicting cut tracks would probably be a negative layer overlay on the existing layer. I'm not quite sure how to implement it (or the UI), but support for lifting pins would require both annotation of the isolation between a pad and the component pin, AND a way to target the lifted pin for addition of a blue-wire route. Adding support for "dead-bug" components will also be required. The idea is that the rework layers / annotations be an extra step after the "as made" board geometry, which augments the connectivity PCB "understands", and allow the reworked design to match an updated schematic net-list whilst a link between your on-screen CAD and the board you have on the desk in front of you. I don't know of any other software tools which manage rework like this, but I think it would be an awesome feature for us to support. Bonus points for ability to spit out a list of rework instructions for a technician or board assembly house to follow and tick off as they are made. Comments? -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) signature.asc Description: This is a digitally signed message part ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
