gEDA-user: Support for heterogeneous symbols?

2007-02-08 Thread fricker

Hi All,

I am evaluating gEDA and came across one feature I am extensively  
using today with a commercial EDA tool when dealing with large  
components, like SOC, FPGAs and ASICs: heterogeneous symbols.


I searched the doc, the mailing lists and the Web but could not find  
how I could create and use such symbols with gschem and gnetlist.


As Roger Williams defines it in his post: http://www.geda.seul.org/ 
mailinglist/geda-dev6/msg3.html


 Heterogeneous devices are non-identical symbols that represent
 different parts of the same device for REFDES and layout purposes.
 They can be tied together by the same 'HETERO=DEVICE1,DEVICE2...'
 attribute on each device.  Typical examples include:

   - large complex logic devices split between multiple symbols
 because of space constraints;

   - multi-function devices split so that each different functional
 block has its own symbol (relays, for instance);

Does gschem support such a way to deal with large devices?
If the answer is yes, then how?
If the answer is no, then how are people dealing with it?

Thanks,
_jP


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Re: gEDA-user: Support for heterogeneous symbols?

2007-02-08 Thread Lares Moreau
Yes, gschem supports heterogeneous symbols.
Just set refdes (u101) the same for all parts of the same device.  Further, if 
you'd like to have different labels for different symbol parts you can append 
lower case characters which are ignored by everything but are there for user 
convenience. (U101a, U101b, U101ioports, U53power, etc)

-Lares

On Thu, 8 Feb 2007 15:13:52 +0100
fricker [EMAIL PROTECTED] wrote:

 Hi All,

 I am evaluating gEDA and came across one feature I am extensively
 using today with a commercial EDA tool when dealing with large
 components, like SOC, FPGAs and ASICs: heterogeneous symbols.

 I searched the doc, the mailing lists and the Web but could not find
 how I could create and use such symbols with gschem and gnetlist.

 As Roger Williams defines it in his post: http://www.geda.seul.org/
 mailinglist/geda-dev6/msg3.html

   Heterogeneous devices are non-identical symbols that represent
   different parts of the same device for REFDES and layout purposes.
   They can be tied together by the same 'HETERO=DEVICE1,DEVICE2...'
   attribute on each device.  Typical examples include:
  
 - large complex logic devices split between multiple symbols
   because of space constraints;
  
 - multi-function devices split so that each different functional
   block has its own symbol (relays, for instance);

 Does gschem support such a way to deal with large devices?
 If the answer is yes, then how?
 If the answer is no, then how are people dealing with it?

 Thanks,
 _jP


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 geda-user@moria.seul.org
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Re: gEDA-user: Support for heterogeneous symbols?

2007-02-08 Thread Michael Sokolov
fricker [EMAIL PROTECTED] wrote:

 I am evaluating gEDA and came across one feature I am extensively  
 using today with a commercial EDA tool when dealing with large  
 components, like SOC, FPGAs and ASICs: heterogeneous symbols.

 I searched the doc, the mailing lists and the Web but could not find  
 how I could create and use such symbols with gschem and gnetlist.

Ah yes, as the mailing list archives can attest, this was also one of my
first questions when I started using gEDA!  (No, I've never used any
commercial EDA tools because I refuse to use Weendoze or Solaris or
whatever other proprietary OS they require, but I've entered the HW eng
field from a software background after watching the HW engs I was
working with and wanting to do that too.  As my work has always been
with large microprocessor-based systems, all schematics I've ever seen
(for very complex microprocessor-based boards) use lots of heterogeneous
symbols.)

 Does gschem support such a way to deal with large devices?

Yes.  The schematics for the SDSL board that I've just captured and
getting ready to lay out make heavy use of heterogeneous symbols.  The
MC68302 microprocessor is split into 3 symbols, the SDSL transceiver
into 5, and the FLEX10K FPGA also into 5.

 If the answer is yes, then how?

Make separate and independent symbols.  Each symbol would cover a
subset of the device pins, and each pin would have its correct number,
so when this is done right each pin number will appear in exactly one of
the symbols.  Instantiate all these symbols on your schematic (can be
on the same page or different pages of a multipage non-hierarchical
schematic, the kind I'm used to) and give the same attributes,
particularly the refdes (and the footprint if you attach it at the
schematic level rather than in the symbol) to all symbol instances
describing parts of the same physical component.

HTH and welcome to Free EDA!

MS


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