Re: gEDA-user: gEDA flow for chip design?
On 01/16/2011 01:04 AM, Oliver King-Smith wrote: It was written specifically for my needs in a quick and dirty fashion. It also lacks any comments. Having issued my disclaimers, I am happy to post it. How do I do that? You can attach it to an email, but better would be the geda wiki, http://www.geda.seul.org/wiki/geda:documentation#gnetlist_-_netlister, Unlike Wikipedia there is no button to create a login by yourself. This is because nobody at the gEDA site has the nerves to deal with anonymous vandalism. Consequently, you have to write an email to the site admin (ahvezda AT geda.seul.org) to gain access. He will gladly send you a login. or ask for a user account for gedasymbols.org, where many tool scripts footprints and schematic symbols are gathered. http://www.gedasymbols.org/cvs.html John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA flow for chip design?
Oliver, First, this looks really, really cool. Congratulations! On Jan 16, 2011, at 4:04 PM, Oliver King-Smith wrote: I don't think it would be appropriate in its current form for distribution to the general public. It was written specifically for my needs in a quick and dirty fashion. It also lacks any comments. Have you considered github.com? I think that's a good place for an alpha project like this. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA flow for chip design?
On Jan 16, 2011, at 1:52 AM, Florian E. Teply wrote: I seem to recall that some guys here use gEDA for chip design. John Doty comes to mind, but i think there are others too. I'd be interested in the workflow as i will have to make up some clever test chips in the next few years for PhD work and i'm not in the position to be able to sell my grandma for a full-fledged cadence seat, nor am i willing to. I basically do schematic-level design and simulation, LVS simulation, and some testing of the physical chips. The project is based at Osaka University. They send my designs out to a layout contractor (Digian). Fab is either through MOSIS or via Cyber Shuttle at TSMC. The basics of the flow may be seen at http://research.kek.jp/people/ikeda/analogVLSI/. In gEDA, I turn off hierarchy expansion. I use gnetlist to create individual subcircuits under control of a Makefile. The Makefile also contains the cat command that assembles the complete design. Most design time is spent in the Simulation subdirectory, where the schematics for the various SPICE test fixtures reside. Again, a Makefile encodes construction of stimulus files, makes sure the right netlists have been built, and launches ngspice, either interactively or not, depending on the simulation. I use a slightly customized version of ngspice: it has the hspice semantics for the noise parameters used by TSMC. Unfortunately, the patch only works for the specific models TSMC provides: poor factoring of ngspice makes propagating that patch to the general case a large job. I have created gEDA symbols for a significant part of Professor Ikeda's Open-IP library. You may obtain these at http://www.gedasymbols.org/user/john_doty/. There you may also find the associated SPICE models, published under GPL with Professor Ikeda's (enthusiastic) permission. John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA flow for chip design?
On Jan 17, 2011, at 6:53 AM, John Doty wrote: I use a slightly customized version of ngspice: it has the hspice semantics for the noise parameters used by TSMC. Unfortunately, the patch only works for the specific models TSMC provides: poor factoring of ngspice makes propagating that patch to the general case a large job. Oh, I should also mention that I use a slightly customized version of John Sheahan's spicepp script. I should publish my version someday... John Doty Noqsi Aerospace, Ltd. http://www.noqsi.com/ j...@noqsi.com ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA flow for chip design?
John Griessen wrote: You can attach it to an email, but better would be the geda wiki, http://www.geda.seul.org/wiki/geda:documentation#gnetlist_-_netlister, or ask for a user account for gedasymbols.org, where many tool scripts footprints and schematic symbols are gathered. http://www.gedasymbols.org/cvs.html IMHO, gedasymbols.org is more appropriate in this case. The wiki is meant for documentation and for presentation. If the gnetlist back-end is ready for general usage, it should be added to the general distro. ---)kaimartin(--- -- Kai-Martin Knaak Email: k...@familieknaak.de Öffentlicher PGP-Schlüssel: http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: gEDA flow for chip design?
Hi folks, I seem to recall that some guys here use gEDA for chip design. John Doty comes to mind, but i think there are others too. I'd be interested in the workflow as i will have to make up some clever test chips in the next few years for PhD work and i'm not in the position to be able to sell my grandma for a full-fledged cadence seat, nor am i willing to. If reasonably possible, i'd want both simulation as well as generation of production-ready data (GDS or OASIS files, preferably OASIS), but have not the slightest idea on how to accomplish that or even if that's possible with open source software, let alone from whithin gEDA. Any suggestions? Thanks, Florian ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA flow for chip design?
Any suggestions? There is also Toped: http://code.google.com/p/toped/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA flow for chip design?
Hello Florian, I wish I could say that I could help, but instead I'd like to say I too am interested in learning what's involved in using gEDA for chip design. I'm not even sure where to begin, other than to share the few things I've thought about so far (however naive or clueless those thoughts may be). In no particular order... I think it would be nice if I could open up existing Cadence designs (Open Access versions) in gschem. To that end, I have signed a license agreement with Si2 to gain access to the OA documentation and API and have gotten shell shocked by the fact that the OA tutorial is over 1000 pages long. I'm not sure if I've bitten off more than I can chew or not. I think it would be nice if I could run some transistor level chip sims with gnucap. Being a digital guy, I have absolutely no idea what's involved in doing that, except to assume that there are other folks (folks at Analog Rails come to mind) who must know more about this than I ever will. I have no idea where to start on the backend -- generating a layout. --wpd On Sat, Jan 15, 2011 at 11:52 AM, Florian E. Teply use...@teply.info wrote: Hi folks, I seem to recall that some guys here use gEDA for chip design. John Doty comes to mind, but i think there are others too. I'd be interested in the workflow as i will have to make up some clever test chips in the next few years for PhD work and i'm not in the position to be able to sell my grandma for a full-fledged cadence seat, nor am i willing to. If reasonably possible, i'd want both simulation as well as generation of production-ready data (GDS or OASIS files, preferably OASIS), but have not the slightest idea on how to accomplish that or even if that's possible with open source software, let alone from whithin gEDA. Any suggestions? Thanks, Florian ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA flow for chip design?
On 01/15/2011 10:52 AM, Florian E. Teply wrote: Hi folks, I seem to recall that some guys here use gEDA for chip design. John Doty comes to mind, but i think there are others too. I'd be interested in the workflow as i will have to make up some clever test chips in the next few years for PhD work and i'm not in the position to be able to sell my grandma for a full-fledged cadence seat, nor am i willing to. If reasonably possible, i'd want both simulation as well as generation of production-ready data (GDS or OASIS files, preferably OASIS), but have not the slightest idea on how to accomplish that or even if that's possible with open source software, let alone from whithin gEDA. Any suggestions? http://opencircuitdesign.com/index.html It has been a while but Magic is what I used in grad school. (It outputs CIF and GDSII but not OASIS.) Since you are in grad school you should find the local guru/professor. They can tell you who will do the fab and any details specific to that. They probably even have access to the required tools. MOSIS is popular: http://www.mosis.com/design/flows/design-flow-scmos-kits.html -- David W. Schultz http://home.earthlink.net/~david.schultz Life without stock is barely worth living... Anthony Bourdain ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA flow for chip design?
On 01/15/2011 10:52 AM, Florian E. Teply wrote: Hi folks, I seem to recall that some guys here use gEDA for chip design. John Doty comes to mind, but i think there are others too. I'd be interested in the workflow as i will have to make up some clever test chips in the next few years for PhD work and i'm not in the position to be able to sell my grandma for a full-fledged cadence seat, nor am i willing to. If reasonably possible, i'd want both simulation as well as generation of production-ready data (GDS or OASIS files, preferably OASIS), but have not the slightest idea on how to accomplish that or even if that's possible with open source software, let alone from whithin gEDA. Any suggestions? Thanks, Florian Here is a EETimes article from 2009 about a guy who did a teach myself project. From the article intro: ... it describes how an experienced engineer undertook to teach himself analog IC design, including his planning, the tools, the sequence of events, and the actual IC fabrication process. Whether you are thinking about learning analog IC design yourself, or just want to see how you can use available resources as part of self-paced continuing education regardless of your engineering career stage, you'll find it of interest and with actionable lessons and take-away information you can use Hands-on: Get started in analog IC design and fab (Part 1 of 3) http://www.eetimes.com/design/analog-design/4010380/Hands-on-Get-started-in-analog-IC-design-and-fab-Part-1-of-3- -- Joe Chisolm Marble Falls, Tx. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA flow for chip design?
On 01/15/2011 10:52 AM, Florian E. Teply wrote: i'd want both simulation as well as generation of production-ready data (GDS or OASIS files, preferably OASIS), but have not the slightest idea on how to accomplish that or even if that's possible with open source software, let alone from within gEDA. Any suggestions? Thanks, Florian I've done chip logic and layout with Cadence tools and it was at a small start up at first -- Cadence didn't care much about our success and we had to do all kinds of self starting to get a working flow even though it cost tons of money. I've not done work with magic, http://opencircuitdesign.com/verilog/index.html , but from asking about it on its list, it can generate GDS2 output and you can extract capacitance from layout with it. If you sign up for its mail list you can ask Tim Edwards, the current maintainer and guru about feasibility for your project. John Doty mentioned his layout is hired out, but I can't remember what tools are used. He's going to be your resource for simulation. What will you make? some kind of sensor? John Griessen ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA flow for chip design?
On 01/15/2011 02:21 PM, Joe Chisolm - Gmail wrote: Hands-on: Get started in analog IC design and fab (Part 1 of 3) http://www.eetimes.com/design/analog-design/4010380/Hands-on-Get-started-in-analog-IC-design-and-fab-Part-1-of-3- It's nice to read about what he stressed as he went after his goal. He mentioned simulation taking the forefront and that's true -- I'd add characterization also. Those MOSIS runs could tell a lot with decent test structures along with the main circuit -- structures that don't take a big area, but include some amplification so you can accurately deduce some of the low level properties of your circuitry. Like a capacitor hooked up with some resistance and drive transistor chain so you can feed a signal through it and probe the response easily as a check on capacitance per area for the process. And long resistors with probe pads for checking R. per area of the process. And whatever else is crucial to your design. John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA flow for chip design?
http://www.eetimes.com/design/analog-design/4010382/Hands-on-Get-started-in-analog-IC-design-and-fab-Part-3-of-3-
an excerpt from above section:
==
Convergence and noise modeling were key issues. At each change, I had
to learn about the new tool and adapt the models and circuit files to
the new simulator. As you can imagine, all that cost a huge amount of
time, though I learned a lot. Different simulators have different
MOSFET models and adapting parameters from one to another can be difficult.
HSpice is the big bucks professional tool that the foundry's model
parameters often target. Fortunately, I was able to get temporary
access to it to complete the design.
He takes a pragmatic view, aiming for results where he could not afford to fail
by aiming at an easy commercial design, avoiding letting the scope enlarge
during his project, and choosing the mainstream proprietary tool based
on old open source Berkeley SPICE. It's tempting to fall into that
thinking and abandon open tools, but John Doty has a work flow figured out
with NG-SPICE and no proprietary tools except maybe layout.
Another way you might get around
the convergence problems and get even better performance than
Doty is to use gnucap. Al says he's done tests
on large circuits to make it perform well and converge better than
many versions of SPICE. Not yet tested by me though.
There are some hurdles to using gnucap -- I had a hard time
getting a wave viewer installed on my debian linux computer -- neither
gtkwave nor gwave are easy except on Red Hat due to some good packaging
effort by Chitlesh et al:
http://fedoraproject.org/wiki/Features/FedoraElectronicLab
debian has a new version of gtkwave since I last used it, so
I'm installing and... there aren't any examples for gnucap
I can find.
Would gnuplot work OK for gnucap? I've used it since forever and
it might even be fast now...
Here's a recipe I found searching for a gtkwave gnucap example
that suggests scripting gnuplot is less hassle than getting gwave to build...
So it could be used for gnucap as well as gwave or gtkwave, right?
John Griessen
no longer a chip designer, but thinking of down-to-the-material circuit design
for printable organic semiconductors soon. That will reset circuit density to
1978 levels,
but be throw away chp to print.
=http://chitlesh.wordpress.com/2007/07/11/life-without-gwave-when-using-gspiceui/=
A much simpler and more convenient way is using gnuplot, mimicking
gwave‘s behaviour for gspiceui.
Put the following into the file “/usr/bin/gwave”:
———-
#!/bin/bash
FILE=”$1″
HEAD=`head -n 1 “$FILE” | tr -s ‘ ‘`
COLS=`echo $HEAD | wc -w`
{
echo plot ‘\’
for x in `seq 2 $COLS`
do
echo -n ‘ ‘ \”$FILE\” using 1:$x with lines ti \”`echo $HEAD | cut -d ‘ ‘ -f
$x`\”
if [ ! $x -eq $COLS ]
then
echo -n ‘,\’
fi
echo
done
} | gnuplot -persist
—-
That way you simply can click the “plot” button. gnuplot‘s window will pop up
and show the plot automagically.
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Re: gEDA-user: gEDA flow for chip design?
On 01/15/2011 10:52 AM, Florian E. Teply wrote: Hi folks, I seem to recall that some guys here use gEDA for chip design. John Doty comes to mind, but i think there are others too. I'd be interested in the workflow as i will have to make up some clever test chips in the next few years for PhD work and i'm not in the position to be able to sell my grandma for a full-fledged cadence seat, nor am i willing to. If reasonably possible, i'd want both simulation as well as generation of production-ready data (GDS or OASIS files, preferably OASIS), but have not the slightest idea on how to accomplish that or even if that's possible with open source software, let alone from whithin gEDA. Any suggestions? I have just made my first ASIC. I used gEDA and LTSpice for the front end. To get from gschem to Magic I wrote a gnetlist translator. I did this by writing a small scheme back end that called into a standard C++ program to do the heavy lifting. Inside Magic I did the layout with a crude DRC based on the process I was using. I extracted back out of Magic and reran the extract circuit in LTSpice as my LVS checker. You can also run a simple LVS in Magic, but I did not find that entirely reliable. I then use a tool call KLayout and wrote scripts in ruby (the automation language for KLayout) to manipulate the layer data to get the resulting files I want. Klayout can export to OASIS if you wish to use that format. I myself used GDSII. So to summarize my flow: gschem - gnetlist spice-oks - LTSpice (I use my own spice back end as well) For doing the designing, and then gschem - gnetlist magic - C++ code - Magic - KLayout - Ruby - GDSII to do the layout. There is no need to use the C++ code if you are a whiz at scheme, but I really don't like LISP. I am not anti functional languages, I just don't like the syntax of LISP. I find it hard to maintain and read. Oliver ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA flow for chip design?
I looked at Toped quiet a bit and did not think it was as good as magic yet. I like the idea behind it, and it is much more modern feeling that Magic, but it is still pretty immature. Oliver __ From: Bob Paddock bob.padd...@gmail.com To: gEDA user mailing list geda-user@moria.seul.org Sent: Sat, January 15, 2011 9:45:05 AM Subject: Re: gEDA-user: gEDA flow for chip design? Any suggestions? There is also Toped: [1]http://code.google.com/p/toped/ ___ geda-user mailing list [2]geda-user@moria.seul.org [3]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. http://code.google.com/p/toped/ 2. mailto:geda-user@moria.seul.org 3. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA flow for chip design?
On 01/15/2011 07:39 PM, Oliver King-Smith wrote: I extracted back out of Magic and reran the extract circuit in LTSpice as my LVS checker. You can also run a simple LVS in Magic, but I did not find that entirely reliable. I'd like to hear more about this. Are you meaning functional simulation to decide on layout vs schematic match? You're saying the extract function of magic is fully reliable? John ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA flow for chip design?
I extracted back out of Magic and reran the extract circuit in LTSpice as my LVS checker. You can also run a simple LVS in Magic, but I did not find that entirely reliable. I'd like to hear more about this. Are you meaning functional simulation to decide on layout vs schematic match? You're saying the extract function of magic is fully reliable? I found the extraction from Magic to be very reliable, although getting the parasitics setup is hard. You can easily remove clearly bad parasitics. The LVS function in magic was a little buggy. Tim Edwards has some examples from me, and he is pondering why they might be failing. I reduced it to a pretty simple case. It unfortunately also breaks the auto-router so you should use that with care. Oliver ___ geda-user mailing list [1]geda-user@moria.seul.org [2]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:geda-user@moria.seul.org 2. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA flow for chip design?
Oliver King-Smith wrote: There is no need to use the C++ code if you are a whiz at scheme, but I really don't like LISP. You are not alone :-) Would you contribute the scheme glue script to the project? Maybe it can even be added to the main distro of gnetlist. What do ye developers think? ---)kaimartin(--- -- Kai-Martin Knaak Email: k...@familieknaak.de Öffentlicher PGP-Schlüssel: http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA flow for chip design?
On Sat, 15 Jan 2011 17:44:33 -0600 John Griessen j...@ecosensory.com wrote: On 01/15/2011 10:52 AM, Florian E. Teply wrote: i'd want both simulation as well as generation of production-ready data (GDS or OASIS files, preferably OASIS), but have not the slightest idea on how to accomplish that or even if that's possible with open source software, let alone from within gEDA. Any suggestions? Thanks, Florian I've done chip logic and layout with Cadence tools and it was at a small start up at first -- Cadence didn't care much about our success and we had to do all kinds of self starting to get a working flow even though it cost tons of money. I've not done work with magic, http://opencircuitdesign.com/verilog/index.html , but from asking about it on its list, it can generate GDS2 output and you can extract capacitance from layout with it. If you sign up for its mail list you can ask Tim Edwards, the current maintainer and guru about feasibility for your project. John Doty mentioned his layout is hired out, but I can't remember what tools are used. He's going to be your resource for simulation. What will you make? some kind of sensor? First, thanks to all for the contributions, they are much appreciated. What exactly i will make isn't entirely sure yet. My plans are to explore the degradation properties of some 0.25 micron and/or 0.13 micron BiCMOS processes of a small research fab in mixed radiation environments. But I'm still at a very early stage, mostly trying to digest the literature in order to find a small niche where genuinely new insights could be gained. In the long run I plan to integrate the findings into specialized models for simulation. After all the radiation testing and modeling, one might consider this a radiation sensor ;-) Greetings, Florian ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: gEDA flow for chip design?
There isn't much to the glue script, but now that I think about it I might be able to make it more useful and general purpose. I don't think it would be appropriate in its current form for distribution to the general public. It was written specifically for my needs in a quick and dirty fashion. It also lacks any comments. Having issued my disclaimers, I am happy to post it. How do I do that? Oliver Oliver King-Smith wrote: There is no need to use the C++ code if you are a whiz at scheme, but I really don't like LISP. You are not alone :-) Would you contribute the scheme glue script to the project? Maybe it can even be added to the main distro of gnetlist. What do ye developers think? ---)kaimartin(--- -- Kai-Martin Knaak Email: [1]k...@familieknaak.de Öffentlicher PGP-Schlüssel: [2]http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53 ___ geda-user mailing list [3]geda-user@moria.seul.org [4]http://www.seul.org/cgi-bin/mailman/listinfo/geda-user References 1. mailto:k...@familieknaak.de 2. http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53 3. mailto:geda-user@moria.seul.org 4. http://www.seul.org/cgi-bin/mailman/listinfo/geda-user ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
