Re: gEDA-user: overlapping via changes
kai-martin knaak k...@familieknaak.de writes: Armin Faltl wrote: you suggest it's good for something - what for? Mechanics. These deviant holes may be used to solder the pcb to a brass rod. Anyway, I don't know what use some rocket scientist may find for overlapping holes. PCB can do it, some fabs do it. So it should be documented. Rocket Scientist need to qualify everything that is even marginally unusual, over full temperature range, and mechanical loads, in vacuum. That will cost a thick branch of some big tree (10kg paperwork). Rocket science is the last place where you'll find those holes, if they can be avoided in any way :-) ---)kaimartin(--- -- Stephan Böttcher FAX: +49-431-85660 Extraterrestrische PhysikTel: +49-431-880-2508 I.f.Exp.u.Angew.Physik mailto:boettc...@physik.uni-kiel.de Leibnizstr. 11, 24118 Kiel, Germany ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: overlapping via changes
On Sun, 19 Dec 2010 22:12:30 -0500 DJ Delorie d...@delorie.com wrote: I changed the overlapping vias test in two ways... 1. Via copper is now allowed to overlap when vias are created. Via *drills* are not. 2. Vias which violate this rule in a *.pcb file are preserved at load time. Thus, PCB will make a modest attempt at preventing users from making vias that might be difficult to manufacture, but if the user finds a way around the restriction, PCB will let them get away with it. Simply moving an existing via is an adequate way around it. I think this should trigger a non-copper DRC error. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: overlapping via changes
Kai-Martin Knaak wrote: Thanks. I'll put this to the wiki. http://geda.seul.org/wiki/geda:pcb_tips?#i_want_to_draw_two_vias_very_close_to_each_other_but_pcb_won_t_let_me ---)kaimartin(-- -- Kai-Martin Knaak Öffentlicher PGP-Schlüssel: http://pgp.mit.edu:11371/pks/lookup?op=getsearch=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: overlapping via changes
Armin Faltl wrote: you suggest it's good for something - what for? Mechanics. These deviant holes may be used to solder the pcb to a brass rod. Anyway, I don't know what use some rocket scientist may find for overlapping holes. PCB can do it, some fabs do it. So it should be documented. ---)kaimartin(--- -- Kai-Martin Knaak Öffentlicher PGP-Schlüssel: http://pgp.mit.edu:11371/pks/lookup?op=getsearch=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: overlapping via changes
On Thu, 2010-12-23 at 00:40 +0100, kai-martin knaak wrote: Kai-Martin Knaak wrote: Thanks. I'll put this to the wiki. http://geda.seul.org/wiki/geda:pcb_tips?#i_want_to_draw_two_vias_very_close_to_each_other_but_pcb_won_t_let_me ---)kaimartin(-- Wiki writes: I want to draw two vias very close to each other, but PCB won't let me! Unfortunately, older versions of PCB not only prevent you from pacing overlapping vias but dropp them on load. In december 2010 this overly cautions behavior was fixed. If you really need overlapping vias, you have to install a version of pcb younger than that. The 2011 version of PCB still won't allow you to place vias so close that their holes overlap. However, it won't complain if you mangaged to work-around this restriction. E.g. place tiny vias and increase their size afterwards. One may write: PCB versions before xxx prevent you from placing overlapping vias and drop them on load. Since December 2010 overlapping of annular ring is allowed, but overlapping holes are still restricted. If you really want overlapping wholes, you can place small vias close together and then increase the diameter. Kai Martin, you your English is much better than mine, but please try to be not to verbose. And watch for typos, dropp and pacing. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: overlapping via changes
Kai-Martin Knaak wrote: 2. Vias which violate this rule in a *.pcb file are preserved at load time. Thus, PCB will make a modest attempt at preventing users from making vias that might be difficult to manufacture, but if the user finds a way around the restriction, PCB will let them get away with it. Simply moving an existing via is an adequate way around it. Thanks. I'll put this to the wiki. Back then when I used protel we actually had cases where overlapping were holes deliberate. The hole had to be non-round and clad with metal. So regular milling wouldn't do. Can you give a reason? - I can only imagine a mechanical one. When you put it on the Wiki, pleas also explain, that doing this is electrical and thermal nonsens, because the circumference of a hole is proportional to the diameter and 2 holes confined in a given length along the direction connecting the centers have maximum surface, if they are either identically 1 big hole or 2 holes that exactly touch each other. For the partial overlap, the normalized circumference u is given by: U/L = u = 2r * (pi - acos(1/2r - 1)) where r = R/L, L is the diameter of the overlapping holes and R is the drill-bit radius. This function is valid between r = 0.25 where the holes just touch and r = 0.5 where the holes melt to one big circular with R = L/2. It has a minimum at ca. 0.295 Hopefully I didn't foul the math, check it ;-) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: overlapping via changes
Armin Faltl wrote: The hole had to be non-round and clad with metal. So regular milling wouldn't do. Can you give a reason? - I can only imagine a mechanical one. You already guessed it. Mechanics was the main reason. Non round structures had to be soldered to the pcb and space was at premium. When you put it on the Wiki, pleas also explain, that doing this is electrical and thermal nonsens, There is no evidence for users falsely believing that overlapping metal clad holes are good for thermal or electrical conductivity. So there is no reason to preach to them. ---)kaimartin(--- -- Kai-Martin Knaak Öffentlicher PGP-Schlüssel: http://pgp.mit.edu:11371/pks/lookup?op=getsearch=0x6C0B9F53 ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: overlapping via changes
kai-martin knaak wrote: There is no evidence for users falsely believing that overlapping metal clad holes are good for thermal or electrical conductivity. So there is no reason to preach to them. By heuristic and gut feeling I thought that the presented result would be true. But I was unsure enough to actually do the math behind it. If you think it's preaching, leave it out. I just thought that others may have the same uncertainty, but not the math education. If you present this as a trick without explanation you suggest it's good for something - what for? ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: overlapping via changes
DJ Delorie wrote: 1. Via copper is now allowed to overlap when vias are created. Via drills are not. Does pcb complain if the user tries to overlap vias. Or does it just silently refuse to put the via? 2. Vias which violate this rule in a *.pcb file are preserved at load time. Thus, PCB will make a modest attempt at preventing users from making vias that might be difficult to manufacture, but if the user finds a way around the restriction, PCB will let them get away with it. Simply moving an existing via is an adequate way around it. Thanks. I'll put this to the wiki. Back then when I used protel we actually had cases where overlapping were holes deliberate. The hole had to be non-round and clad with metal. So regular milling wouldn't do. ---)kaimartin(--- -- Kai-Martin Knaak tel: +49-511-762-2895 Universität Hannover, Inst. für Quantenoptik fax: +49-511-762-2211 Welfengarten 1, 30167 Hannover http://www.iqo.uni-hannover.de GPG key:http://pgp.mit.edu:11371/pks/lookup?search=Knaak+kmkop=get ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: overlapping via changes
On Mon, 2010-12-20 at 14:39 +0100, Kai-Martin Knaak wrote: Thanks. I'll put this to the wiki. Back then when I used protel we actually had cases where overlapping were holes deliberate. The hole had to be non-round and clad with metal. So regular milling wouldn't do. That is OK so long as the vendor knows what you mean, and does whatever special processing is required. With regular drilling, I would imagine overlapping holes would quite often lead to snapped drills, or at least a badly drilled hole. Presumably they converted to some kind of routing operation? In the future(TM) I'd like to see PCB support this kind of thing specified more generally than kludging by overlapping drill holes. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: overlapping via changes
Kai-Martin Knaak kn...@iqo.uni-hannover.de writes: Does pcb complain if the user tries to overlap vias. Or does it just silently refuse to put the via? It does, and always has, printed a message to the message log. Back then when I used protel we actually had cases where overlapping were holes deliberate. The hole had to be non-round and clad with metal. Right. That's why we need to preserve these cheats once the user gets them into the pcb file. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: overlapping via changes
I changed the overlapping vias test in two ways... 1. Via copper is now allowed to overlap when vias are created. Via *drills* are not. 2. Vias which violate this rule in a *.pcb file are preserved at load time. Thus, PCB will make a modest attempt at preventing users from making vias that might be difficult to manufacture, but if the user finds a way around the restriction, PCB will let them get away with it. Simply moving an existing via is an adequate way around it. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
