Re: gEDA-user: pcb outline clarification
Am 25.10.2010 um 03:43 schrieb gene glick: My outline layer was labeled Outline. Changing it to all lower case fixed it. I'm about to offer a patch to allow upper case characters as well, and allow the outline to be on the solder side. The later would allow to mill the outline on single sided boards. Markus - - - - - - - - - - - - - - - - - - - Dipl. Ing. (FH) Markus Hitter http://www.jump-ing.de/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb outline clarification
On Mon, 2010-10-25 at 12:53 +0200, Markus Hitter wrote: Am 25.10.2010 um 03:43 schrieb gene glick: My outline layer was labeled Outline. Changing it to all lower case fixed it. I'm about to offer a patch to allow upper case characters as well, We did at one point have various code in PCB which accepted mixed case names, (strcasecmp rather than strcmp). Unfortunately, it wasn't consistent, and some code was still case sensitive. I committed a change which made everything support mixed case, but after some discussion, reverted it and made everything consistently case sensitive. That means less magic names to filter out when we convert (soon I hope) to more explicit layer type tagging. Since we're aiming for layer type tagging, patches introducing further special-casing for layer names will likely not be accepted. and allow the outline to be on the solder side. The later would allow to mill the outline on single sided boards. Do you mean flipping the outline layer so the router is effectively working from the underside of the board? Sounds like a potentially useful flag. Presumably the G-code exporter already flips the solder side. Adding a property to the exporter to flip the outline layer would probably be the easiest way to proceed for now. -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb outline clarification
Am Montag, den 25.10.2010, 12:53 +0200 schrieb Markus Hitter: Am 25.10.2010 um 03:43 schrieb gene glick: My outline layer was labeled Outline. Changing it to all lower case fixed it. I'm about to offer a patch to allow upper case characters as well, and allow the outline to be on the solder side. The later would allow to mill the outline on single sided boards. Well, and then I found this in the Changelog: 2009-11-12 Peter Clifton * pcjc2 AT cam dot ac dot uk * * src/draw.c, src/hid/common/flags.c, src/hid/gerber/gerber.c, src/hid/png/png.c, src/hid/ps/ps.c, src/print.c: Use strcmp() for special layer names, rather than strcasecmp() Before commit 086aa491fae18f1ec72da047b772fa3510f72d0b, we were using strcmp() and strcasecmp() in different places. That commit changed to strcasecmp(). Lets choose to keep the more restrictive option for now, which reduces the number of magic layer names PCB supports. Looks like coding simplification is favoured over user friendliness. OK, scratch that idea of a patch. Markus ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb outline clarification
Am 25.10.2010 um 13:13 schrieb Peter Clifton: I committed a change which made everything support mixed case, but after some discussion, reverted it and made everything consistently case sensitive. Found that in the ChangeLog and promtly raised the noise level of this list. :-/ and allow the outline to be on the solder side. The later would allow to mill the outline on single sided boards. Do you mean flipping the outline layer so the router is effectively working from the underside of the board? Sounds like a potentially useful flag. Presumably the G-code exporter already flips the solder side. Yes, yes and yes. It looks like it's sufficient to just not treat the outline layer when handling isolation milling, but in a then new feature of outline milling. If you want to mill the outline from the front side, add outline to the component side group, else add it to the solder side group. Markus - - - - - - - - - - - - - - - - - - - Dipl. Ing. (FH) Markus Hitter http://www.jump-ing.de/ ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb outline clarification
On Mon, 2010-10-25 at 17:20 +0200, Markus Hitter wrote: Am Montag, den 25.10.2010, 12:53 +0200 schrieb Markus Hitter: Looks like coding simplification is favoured over user friendliness. OK, scratch that idea of a patch. Markus Markus, please note: Clear, easy to understand code is user friendly -- it makes it possible to find bugs fast and prevent new bugs, and it makes it possible for new developers to join the project, understand how its works, and to contribute. Of course too simple code is not user friendly. You may know how many patches Linus rejects for the Linux kernel... For the layer stuff my impression was, that some of the developers intend a complete rewrite, so that we can have multiple layers of each type, new types like keepouts, and maybe routing styles and DRC specification bound direct to layers. My impression may be wrong, I am not involved in current PCB development. Best regards Stefan Salewski ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb outline clarification
On Mon, 2010-10-25 at 17:53 +0200, Stefan Salewski wrote: On Mon, 2010-10-25 at 17:20 +0200, Markus Hitter wrote: Am Montag, den 25.10.2010, 12:53 +0200 schrieb Markus Hitter: Looks like coding simplification is favoured over user friendliness. OK, scratch that idea of a patch. applying s/strcmp/strcasecmp/ is no more simple than what we have now, just not something we considered desirable when reflecting upon it. Currently outline and route have special meaning, and any layer witih that name is treated differently when exporting. Existing users will have boards with these layer names (assuming they are relying on the special handling). If we add more magic layer names, either by strcasecmp, or introducing more synonyms, special handling for mechanical / notes / whatever.. we risk breaking boards of users who might inadvertently have used those names for non-special things. Whilst I grant you that the risk of damage is probably low, with CAD tools it is generally very important not to have a new version of the tool change fundamental handling of old design files. This might mean complicating the code to make the new layer names active only for new files. [snip] For the layer stuff my impression was, that some of the developers intend a complete rewrite, so that we can have multiple layers of each type, new types like keepouts, and maybe routing styles and DRC specification bound direct to layers. My impression may be wrong, I am not involved in current PCB development. The layer types work has been planned for quite a while now. The intention is to remove all special casing based on layer name (internally at least), and make the handling based on layer attributes / flags. We would of course retain code to auto-apply the appropriate flags to old boards which feature the old special-cased names. I don't have any idea when the new functionality will appear, and I'm not working on it myself. My only involvement before was to clear up the ambiguity where some pieces of code accepted layer names case insensitively and others did not. Regards, -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
gEDA-user: pcb outline clarification
My design creates an outline layer. The rectangle the represents the outline of my board is about 11 X 11. The drawing area is about 20 X 14. In the fab.gbr layer, there is a note at the very bottom stating Board outline is the centerline of this 10 mil rectangle - 0,0 to 2,14000 mils. Is that going to confuse the PCB manufacturer? I want them to cut along the lines on the outline layer, not the fab layer. thanks ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb outline clarification
If you do the outline right, PCB should print Board Outline is the centerline of this path on the fab layer. I can peek at your .pcb if you want to send me a copy. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
Re: gEDA-user: pcb outline clarification
DJ Delorie wrote: If you do the outline right, PCB should print Board Outline is the centerline of this path on the fab layer. I can peek at your .pcb if you want to send me a copy. Thanks for the offer! I see what was wrong, though. My outline layer was labeled Outline. Changing it to all lower case fixed it. Now the output is precisely as you said. ___ geda-user mailing list geda-user@moria.seul.org http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
