Re: [gem5-dev] Review Request 2619: cpu: Add L-TAGE branch predictor

2015-02-28 Thread Nilay Vaish via gem5-dev


> On Feb. 3, 2015, 9:37 a.m., Andreas Hansson wrote:
> > Something is still not quite right with the diffs.
> 
> Dibakar Gope wrote:
> I was not using the reviewboard extension. I will re-upload that patch 
> through mercurial patchqueues soon. Sorry for the slow response.

The problem still exists.


- Nilay


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On Feb. 27, 2015, 3:31 p.m., Dibakar Gope wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/2619/
> ---
> 
> (Updated Feb. 27, 2015, 3:31 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> It is the L-TAGE predictor from the Branch Prediction Championship, 
> originally coded by Vignyan Reddy, and modified by me.
> 
> 
> Diffs
> -
> 
>   src/cpu/pred/2bit_local.hh 2051d6b87b53 
>   src/cpu/pred/2bit_local.cc 2051d6b87b53 
>   src/cpu/pred/BranchPredictor.py 2051d6b87b53 
>   src/cpu/pred/SConscript 2051d6b87b53 
>   src/cpu/pred/bi_mode.hh 2051d6b87b53 
>   src/cpu/pred/bi_mode.cc 2051d6b87b53 
>   src/cpu/pred/bpred_unit.hh 2051d6b87b53 
>   src/cpu/pred/bpred_unit.cc 2051d6b87b53 
>   src/cpu/pred/bpred_unit_impl.hh 2051d6b87b53 
>   src/cpu/pred/ltage.hh PRE-CREATION 
>   src/cpu/pred/ltage.cc PRE-CREATION 
>   src/cpu/pred/tournament.hh 2051d6b87b53 
>   src/cpu/pred/tournament.cc 2051d6b87b53 
> 
> Diff: http://reviews.gem5.org/r/2619/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Dibakar Gope
> 
>

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[gem5-dev] Review Request 2677: cpu: o3: commit: mark pipeline delay variable as consts

2015-02-28 Thread Nilay Vaish via gem5-dev

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http://reviews.gem5.org/r/2677/
---

Review request for Default.


Repository: gem5


Description
---

Changeset 10713:175c1dba1179
---
cpu: o3: commit: mark pipeline delay variable as consts


Diffs
-

  src/cpu/o3/commit.hh 4206946d60fe 

Diff: http://reviews.gem5.org/r/2677/diff/


Testing
---


Thanks,

Nilay Vaish

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[gem5-dev] Review Request 2676: cpu: o3: remove unused stat variables.

2015-02-28 Thread Nilay Vaish via gem5-dev

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---

Review request for Default.


Repository: gem5


Description
---

Changeset 10712:bb6de70c386f
---
cpu: o3: remove unused stat variables.


Diffs
-

  src/cpu/o3/commit.hh 4206946d60fe 
  src/cpu/o3/commit_impl.hh 4206946d60fe 

Diff: http://reviews.gem5.org/r/2676/diff/


Testing
---


Thanks,

Nilay Vaish

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[gem5-dev] Review Request 2675: cpu: o3: combine if with same condition

2015-02-28 Thread Nilay Vaish via gem5-dev

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Review request for Default.


Repository: gem5


Description
---

Changeset 10711:fde343df1e97
---
cpu: o3: combine if with same condition


Diffs
-

  src/cpu/o3/commit_impl.hh 4206946d60fe 

Diff: http://reviews.gem5.org/r/2675/diff/


Testing
---


Thanks,

Nilay Vaish

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[gem5-dev] Review Request 2674: cpu: o3: remove member variable squashCounter

2015-02-28 Thread Nilay Vaish via gem5-dev

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---

Review request for Default.


Repository: gem5


Description
---

Changeset 10709:e490e8f78f64
---
cpu: o3: remove member variable squashCounter
The variable is used in only one place and a whole new function setNextStatus()
has been defined just to compute the value of the variable.  Instead of calling
the function, the value is now computed in the loop that preceded the function
call.


Diffs
-

  src/cpu/o3/commit.hh 4206946d60fe 
  src/cpu/o3/commit_impl.hh 4206946d60fe 

Diff: http://reviews.gem5.org/r/2674/diff/


Testing
---


Thanks,

Nilay Vaish

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[gem5-dev] Review Request 2673: cpu: o3: remove unused function annotateMemoryUnits()

2015-02-28 Thread Nilay Vaish via gem5-dev

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Review request for Default.


Repository: gem5


Description
---

Changeset 10708:a440c1e9ccfb
---
cpu: o3: remove unused function annotateMemoryUnits()


Diffs
-

  src/cpu/o3/fu_pool.hh 4206946d60fe 
  src/cpu/o3/fu_pool.cc 4206946d60fe 

Diff: http://reviews.gem5.org/r/2673/diff/


Testing
---


Thanks,

Nilay Vaish

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[gem5-dev] Review Request 2672: x86: implements x87 mult/div instructions

2015-02-28 Thread Nilay Vaish via gem5-dev

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---

Review request for Default.


Repository: gem5


Description
---

Changeset 10707:c4d9cbb17fa9
---
x86: implements x87 mult/div instructions


Diffs
-

  src/arch/x86/isa/decoder/x87.isa 4206946d60fe 
  src/arch/x86/isa/insts/x87/arithmetic/division.py 4206946d60fe 
  src/arch/x86/isa/insts/x87/arithmetic/multiplication.py 4206946d60fe 

Diff: http://reviews.gem5.org/r/2672/diff/


Testing
---


Thanks,

Nilay Vaish

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Re: [gem5-dev] Review Request 2664: mem: Add byte mask to Packet::checkFunctional

2015-02-28 Thread Steve Reinhardt via gem5-dev

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Ship it!


Ship It!

- Steve Reinhardt


On Feb. 23, 2015, 5:04 a.m., Andreas Hansson wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/2664/
> ---
> 
> (Updated Feb. 23, 2015, 5:04 a.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 10722:366b2fa691b7
> ---
> mem: Add byte mask to Packet::checkFunctional
> 
> This patch changes the valid-bytes start/end to a proper byte
> mask. With the changes in timing introduced in previous patches there
> are more packets waiting in queues, and there are regressions using
> the checker CPU failing due to non-contigous read data being found in
> the various cache queues.
> 
> This patch also adds some more comments explaining what is going on,
> and adds the fourth and missing case to Packet::checkFunctional.
> 
> 
> Diffs
> -
> 
>   src/mem/packet.cc c6cb94a14fea 
>   src/mem/packet.hh c6cb94a14fea 
> 
> Diff: http://reviews.gem5.org/r/2664/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Andreas Hansson
> 
>

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Re: [gem5-dev] Review Request 2670: mem: Fix cache MSHR conflict determination

2015-02-28 Thread Steve Reinhardt via gem5-dev

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Ship it!


Ship It!

- Steve Reinhardt


On Feb. 23, 2015, 5:05 a.m., Andreas Hansson wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/2670/
> ---
> 
> (Updated Feb. 23, 2015, 5:05 a.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 10723:a8355eea658c
> ---
> mem: Fix cache MSHR conflict determination
> 
> This patch fixes a rather subtle issue in the sending of MSHR requests
> in the cache, where the logic previously did not check for conflicts
> between the MSRH queue and the write queue when requests were not
> ready. The correct thing to do is to always check, since not having a
> ready MSHR does not guarantee that there is no conflict.
> 
> The underlying problem seems to have slipped past due to the symmetric
> timings used for the write queue and MSHR queue. However, with the
> recent timing changes the bug caused regressions to fail.
> 
> 
> Diffs
> -
> 
>   src/mem/cache/cache_impl.hh c6cb94a14fea 
> 
> Diff: http://reviews.gem5.org/r/2670/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Andreas Hansson
> 
>

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[gem5-dev] Cron /z/m5/regression/do-regression quick

2015-02-28 Thread Cron Daemon via gem5-dev
scons: *** [build/POWER/gem5.debug] Error 1
scons: *** 
[build/ALPHA_MOESI_CMP_directory/python/m5/internal/param_ProbeListenerObject.py.fo]
 Error 1
scons: *** [build/MIPS/gem5.fast.unstripped] Error 1
scons: *** 
[build/ALPHA_MOESI_CMP_directory/python/m5/internal/param_ProbeListenerObject.py.o]
 Error 1
scons: *** [build/NULL/gem5.opt] Error 1
scons: *** [build/POWER/gem5.opt] Error 1
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing passed.
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* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing passed.
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