[gem5-dev] x86 MinorCPU Branch Prediction

2016-11-22 Thread Ayaz Akram 
Hi,

I had posted a problem that I faced with x86 minor cpu regarding branch
prediction on gem5 users mailing list (link of that post is given below):

https://www.mail-archive.com/gem5-users@gem5.org/msg13325.html

I could not look into it later and now have got a chance to work on it
again. Based on my observations I had put some code lines (just a rough
hack) in fetch2.cc file (in Fetch2::predictBranch):

  std::string  x86Instruction = inst->staticInst->disassemble(
inst->pc.instAddr());


  char * cstrx86 = new char [x86Instruction.length()+1];
  std::strcpy (cstrx86, x86Instruction.c_str());

  char *TempToken = strtok(cstrx86," ");

   if( strncmp(TempToken,"jnz",3)==0 || strncmp(TempToken,"jz",2)==0 ||
strncmp(TempToken,"jb",2)==0 || strncmp(TempToken,"jnb",3)==0 ||
strncmp(TempToken,"jbe",3)==0 )
 inst->staticInst->flags.set(11);  //Control flag

if( strncmp(TempToken,"jnbe",4)==0 || strncmp(TempToken,"js",2)==0
|| strncmp(TempToken,"jns",3)==0 || strncmp(TempToken,"jp",2)==0 ||
strncmp(TempToken,"jnp",3)==0 )
inst->staticInst->flags.set(11);

if( strncmp(TempToken,"jl",2)==0 || strncmp(TempToken,"jnl",3)==0
|| strncmp(TempToken,"jle",3)==0 || strncmp(TempToken,"jnle",4)==0 ||
strncmp(TempToken,"jo",2)==0 )
inst->staticInst->flags.set(11);


if( strncmp(TempToken,"jno",3)==0 || strncmp(TempToken,"jrcx",4)==0
|| strncmp(TempToken,"iret",4)==0 || strncmp(TempToken,"iretd",4)==0 ||
strncmp(TempToken,"loop",2)==0 )
   inst->staticInst->flags.set(11);

if( strncmp(TempToken,"loopne",6)==0 ||
strncmp(TempToken,"loope",5)==0 || strncmp(TempToken,"ret",3)==0 ||
strncmp(TempToken,"call",4)==0)
   inst->staticInst->flags.set(11);


if(strncmp(TempToken,"jmp",3)==0)
{
inst->staticInst->flags.set(11);
inst->staticInst->flags.set(15); //UnCondControl

}

if(strncmp(TempToken,"call",4)==0)
{  inst->staticInst->flags.set(16); //set IsCall
inst->staticInst->flags.set(11);
inst->staticInst->flags.set(15);
}


if((strncmp(TempToken,"ret",3)==0) ||
(strncmp(TempToken,"iret",4)==0))//
|| strncmp(TempToken,"iretd",3)==0)
{ inst->staticInst->flags.set(17); //set IsReturn
inst->staticInst->flags.set(11);
   inst->staticInst->flags.set(15); //UnCOndControl

}


// Next lines are existing already

 if (inst->staticInst->isControl() ||
inst->staticInst->isSyscall())
{
/* Tried to predict */
inst->triedToPredict = true;

DPRINTF(Branch, "Trying to predict for inst: %s\n", *inst);

if (branchPredictor.predict(inst->staticInst,
inst->id.fetchSeqNum, inst_pc,
inst->id.threadId))
{ 
...

// 
##//

After adding these lines  it seems that branch predictor is working for x86
minor cpu. I have tested many benchmarks, most of them work, but this hack
fails for some.
I wonder if minor cpu developers can take a look into this issue ?


Thanks for your time
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Re: [gem5-dev] Review Request 3743: cpu: implement L-TAGE branch predictor

2016-11-22 Thread Arthur Perais 
Jason, thanks for the feedback, 

I'll do my best to address everything tomorrow, but I've added some replies to 
your comments inline. 

- Mail original -

> De: "Jason Lowe-Power" 
> À: "Default" , "Jason Lowe-Power" ,
> "Arthur Perais" 
> Envoyé: Mardi 22 Novembre 2016 19:15:03
> Objet: Re: Review Request 3743: cpu: implement L-TAGE branch predictor

> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3743/

> A few thing below. Overall, could you please add more comments? No need to
> write the entire TAGE paper in the comments, but a little high-level
> information would help new people coming to this code a lot.

Will do. 

> src/cpu/o3/O3CPU.py (Diff revision 1)
> def support_take_over(cls):
> 142
> branchPred = Param . BranchPredictor ( TournamentBP ( numThreads =
> 142
> branchPred = Param . BranchPredictor ( LTAGE ( numThreads =

> I'm not sure we want to make the TAGE predictor the default. Are there any
> products that use something like the TAGE predictor?

> Alternatively, if the tournamentBP is much worse than current products, I can
> see the argument for make the TAGE predictor the default.

Well, officially no, but then again, Seznec is the only guy that has an Intel 
Research Impact Medal so maybe :) In addition, perceptron is known to be in AMD 
(Zen I think?) and Samsung (Mongoose, which is mobile-class) CPUs, and its 
performance is ~comparable to TAGE, so in that sense, it is reasonable to have 
a high performing branch predictor as the default for the out-of-order CPU. I'm 
not pushing for it though, totally fine to keep the tournament as default. 

> src/cpu/pred/BranchPredictor.py (Diff revision 1) 99
> histBufferSize = Param . MemorySize ( "128MB" ,

> Is the global history really 128 megabytes?

> I'm not very familiar with the TAGE predictor. Does a real implementation
> somehow reduce this size and you're making a simplifying assumtion here?

I'm not quite sure what is happening here, but 128MB is way overkill. TAGE 
typically tracks the past ~100 - ~1000 last outcomes. Will look into it. 

> src/cpu/pred/ltage.hh (Diff revision 1) 181
> int bindex ( Addr pc_in ) const ;

> Can you add some comments on all of these functions? Doxygen comments would
> be best.

> src/cpu/pred/ltage.cc (Diff revision 1) 68
> history . globalHistory = new uint8_t [ histBufferSize ];
> I'm not sure if you're really using "histBufferSize" as a "MemorySize". This
> seems to just be a count that defaults to 2**27. Is this really a
> MemorySize?

Shouldn't be. Will look into it as well. 

> - Jason Lowe-Power

> On November 22nd, 2016, 2:31 p.m. UTC, Arthur Perais wrote:
> Review request for Default.
> By Arthur Perais.

> Updated Nov. 22, 2016, 2:31 p.m.
> Repository: gem5
> Description
> Changeset 11707:1d085f66c4ca

> cpu: implement an L-TAGE branch predictor

> This patch implements an L-TAGE predictor, based on André Seznec's code
> available from CBP-2
> (http://hpca23.cse.tamu.edu/taco/camino/cbp2/cbp-src/realistic-seznec.h).
> The patch also changes the default branch predictor of o3 from the
> tournament predictor to L-TAGE.

> This patch requires patch #3727 (http://reviews.gem5.org/r/3727/) to compile.
> Diffs

> * src/cpu/o3/O3CPU.py (1d085f66c4ca)
> * src/cpu/pred/BranchPredictor.py (1d085f66c4ca)
> * src/cpu/pred/SConscript (1d085f66c4ca)
> * src/cpu/pred/ltage.hh (PRE-CREATION)
> * src/cpu/pred/ltage.cc (PRE-CREATION)

> View Diff
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Re: [gem5-dev] Review Request 3743: cpu: implement L-TAGE branch predictor

2016-11-22 Thread Jason Lowe-Power 

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---


A few thing below. Overall, could you please add more comments? No need to 
write the entire TAGE paper in the comments, but a little high-level 
information would help new people coming to this code a lot.


src/cpu/o3/O3CPU.py (line 142)


I'm not sure we want to make the TAGE predictor the default. Are there any 
products that use something like the TAGE predictor?

Alternatively, if the tournamentBP is *much* worse than current products, I 
can see the argument for make the TAGE predictor the default.



src/cpu/pred/BranchPredictor.py (line 99)


Is the global history really 128 megabytes?

I'm not very familiar with the TAGE predictor. Does a real implementation 
somehow reduce this size and you're making a simplifying assumtion here?



src/cpu/pred/ltage.hh (line 181)


Can you add some comments on all of these functions? Doxygen comments would 
be best.



src/cpu/pred/ltage.cc (line 68)


I'm not sure if you're really using "histBufferSize" as a "MemorySize". 
This seems to just be a count that defaults to 2**27. Is this really a 
MemorySize?


- Jason Lowe-Power


On Nov. 22, 2016, 2:31 p.m., Arthur Perais wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3743/
> ---
> 
> (Updated Nov. 22, 2016, 2:31 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11707:1d085f66c4ca
> ---
> 
> cpu: implement an L-TAGE branch predictor
> 
> This patch implements an L-TAGE predictor, based on André Seznec's code 
> available from 
> CBP-2 
> (http://hpca23.cse.tamu.edu/taco/camino/cbp2/cbp-src/realistic-seznec.h). The
> patch also changes the default branch predictor of o3 from the tournament 
> predictor
> to L-TAGE.
> 
> This patch requires patch #3727 (http://reviews.gem5.org/r/3727/) to compile.
> 
> 
> Diffs
> -
> 
>   src/cpu/o3/O3CPU.py 1d085f66c4ca 
>   src/cpu/pred/BranchPredictor.py 1d085f66c4ca 
>   src/cpu/pred/SConscript 1d085f66c4ca 
>   src/cpu/pred/ltage.hh PRE-CREATION 
>   src/cpu/pred/ltage.cc PRE-CREATION 
> 
> Diff: http://reviews.gem5.org/r/3743/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Arthur Perais
> 
>

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Re: [gem5-dev] Review Request 3722: cpu: change comments in tournament branch predictor to reflect what the code does

2016-11-22 Thread Jason Lowe-Power 

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---

Ship it!


Ship It!

- Jason Lowe-Power


On Nov. 18, 2016, 1:01 p.m., Arthur Perais wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3722/
> ---
> 
> (Updated Nov. 18, 2016, 1:01 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11707:1d085f66c4ca
> ---
> 
> cpu: correct comments in tournament branch predictor to reflect what the code 
> does.
> 
> The tournament predictor is presented as doing speculative 
> update of the global history and non-speculative update
> of the local history used to generate the branch prediction.
> However, the code does speculative update of both histories.
> 
> 
> Diffs
> -
> 
>   src/cpu/pred/tournament.hh 1d085f66c4ca 
>   src/cpu/pred/tournament.cc 1d085f66c4ca 
> 
> Diff: http://reviews.gem5.org/r/3722/diff/
> 
> 
> Testing
> ---
> 
> Modifying comments only.
> 
> 
> Thanks,
> 
> Arthur Perais
> 
>

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Re: [gem5-dev] Review Request 3710: cpu: Resolve targets of predicted 'taken' conditional direct branches at decode (o3)

2016-11-22 Thread Jason Lowe-Power 

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---

Ship it!


The error you're seeing is because you don't have Google's protobuf library 
installed. Though it has no affect on what you're seeing.

Can you run the full system linux boot regression with O3 to be sure that it 
still works correctly? This is a more rigorous test than any SE mode tests.

- Jason Lowe-Power


On Nov. 18, 2016, 3:21 p.m., Arthur Perais wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3710/
> ---
> 
> (Updated Nov. 18, 2016, 3:21 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11707:1d085f66c4ca
> ---
> cpu: Resolve targets of predicted 'taken' conditional direct branches at 
> decode (o3)
> 
> The target of taken conditional direct branches does not 
> need to be resolved in IEW: the target can be computed at 
> decode, usually using the decoded instruction word and the PC.
> 
> The higher-than-necessary penalty is taken only on conditional
> branches that are predicted taken but miss in the BTB. Thus, 
> this is mostly inconsequential on IPC if the BTB is big/associative 
> enough (fewer capacity/conflict misses). Nonetheless, what gem5 
> simulates is not representative of how conditional branch targets 
> can be handled.
> 
> 
> Diffs
> -
> 
>   src/cpu/o3/decode_impl.hh c38fcdaa5fe5 
> 
> Diff: http://reviews.gem5.org/r/3710/diff/
> 
> 
> Testing
> ---
> 
> util/regress --modes=se
> 
> build/NULL/tests/opt/quick/se/51.memcheck/null/none/memcheck: FAILED! (Python 
> says "NameError: name 'TrafficGen' is not defined"). I'm guessing this is OK 
> as I get the same error without my patch.
> 
> 
> Thanks,
> 
> Arthur Perais
> 
>

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[gem5-dev] Review Request 3743: cpu: implement L-TAGE branch predictor

2016-11-22 Thread Arthur Perais 

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---

Review request for Default.


Repository: gem5


Description
---

Changeset 11707:1d085f66c4ca
---

cpu: implement an L-TAGE branch predictor

This patch implements an L-TAGE predictor, based on André Seznec's code 
available from 
CBP-2 (http://hpca23.cse.tamu.edu/taco/camino/cbp2/cbp-src/realistic-seznec.h). 
The
patch also changes the default branch predictor of o3 from the tournament 
predictor
to L-TAGE.

This patch requires patch #3727 (http://reviews.gem5.org/r/3727/) to compile.


Diffs
-

  src/cpu/o3/O3CPU.py 1d085f66c4ca 
  src/cpu/pred/BranchPredictor.py 1d085f66c4ca 
  src/cpu/pred/SConscript 1d085f66c4ca 
  src/cpu/pred/ltage.hh PRE-CREATION 
  src/cpu/pred/ltage.cc PRE-CREATION 

Diff: http://reviews.gem5.org/r/3743/diff/


Testing
---


Thanks,

Arthur Perais

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Re: [gem5-dev] Review Request 3722: cpu: change comments in tournament branch predictor to reflect what the code does

2016-11-22 Thread Nathanael Premillieu 

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Ship it!


Ship It!

- Nathanael Premillieu


On Nov. 18, 2016, 1:01 p.m., Arthur Perais wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3722/
> ---
> 
> (Updated Nov. 18, 2016, 1:01 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11707:1d085f66c4ca
> ---
> 
> cpu: correct comments in tournament branch predictor to reflect what the code 
> does.
> 
> The tournament predictor is presented as doing speculative 
> update of the global history and non-speculative update
> of the local history used to generate the branch prediction.
> However, the code does speculative update of both histories.
> 
> 
> Diffs
> -
> 
>   src/cpu/pred/tournament.hh 1d085f66c4ca 
>   src/cpu/pred/tournament.cc 1d085f66c4ca 
> 
> Diff: http://reviews.gem5.org/r/3722/diff/
> 
> 
> Testing
> ---
> 
> Modifying comments only.
> 
> 
> Thanks,
> 
> Arthur Perais
> 
>

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Re: [gem5-dev] Review Request 3727: cpu: disallow speculative update of the conditional branch predictor tables (o3)

2016-11-22 Thread Nathanael Premillieu 

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---

Ship it!


Ship It!

- Nathanael Premillieu


On Nov. 18, 2016, 3:14 p.m., Arthur Perais wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3727/
> ---
> 
> (Updated Nov. 18, 2016, 3:14 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11707:1d085f66c4ca
> ---
> 
> cpu: disallow speculative update of the conditional branch predictor tables 
> (o3)
> 
> The Minor and o3 cpu models share the branch prediction 
> code. Minor relies on the BPredUnit::squash() function 
> to update the branch predictor tables on a branch mispre-
> diction. This is fine because Minor executes in-order, so 
> the update is on the correct path. However, this causes the 
> branch predictor to be updated on out-of-order branch 
> mispredictions when using the o3 model, which should not 
> be the case. 
> 
> This patch guards against speculative update of the branch 
> prediction tables. On a branch misprediction, BPredUnit::squash() 
> calls BpredUnit::update(..., squashed = true). The underlying
> branch predictor tests against the value of squashed. If it is 
> true, it restores any speculatively updated internal state
> it might have (e.g., global/local branch history), then returns. 
> If false, it updates its prediction tables. Previously, exist-
> ing predictors did not test against the "squashed" parameter.
> 
> To accomodate for this change, the Minor model must now call
> BPredUnit::squash() then BPredUnit::update(..., squashed = false)
> on branch mispredictions. Before, calling BpredUnit::squash()
> performed the prediction tables update.
> 
> The effect is a slight MPKI improvement when using the o3
> model. A further patch should perform the same modifications
> for the indirect target predictor and BTB (less critical).
> 
> 
> Diffs
> -
> 
>   src/cpu/minor/fetch2.cc 1d085f66c4ca 
>   src/cpu/pred/2bit_local.hh 1d085f66c4ca 
>   src/cpu/pred/2bit_local.cc 1d085f66c4ca 
>   src/cpu/pred/bi_mode.hh 1d085f66c4ca 
>   src/cpu/pred/bi_mode.cc 1d085f66c4ca 
>   src/cpu/pred/bpred_unit.hh 1d085f66c4ca 
>   src/cpu/pred/bpred_unit.cc 1d085f66c4ca 
>   src/cpu/pred/tournament.hh 1d085f66c4ca 
>   src/cpu/pred/tournament.cc 1d085f66c4ca 
> 
> Diff: http://reviews.gem5.org/r/3727/diff/
> 
> 
> Testing
> ---
> 
> Fast regressions (SE)
> booting Linux (FS)
> 
> 
> Thanks,
> 
> Arthur Perais
> 
>

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[gem5-dev] Cron <m5test@zizzer> /z/m5/regression/do-regression quick

2016-11-22 Thread Cron Daemon 
* build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO: 
CHANGED!
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level:
 passed.
 * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: 
passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: passed.
* 
build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple:
 passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: passed.
* build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: 
passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: 
passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: 
passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual:
 passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: 
passed.
* 
build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual:
 passed.
* build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby: 
passed.
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple:
 passed.
* 
build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level:
 passed.* 
build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: passed.
* build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: passed.
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: passed.
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: passed.
* build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter: passed.
* build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest: passed.
* build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: passed.
* build/NULL/tests/opt/quick/se/51.memcheck/null/none/memcheck: passed.
* 
build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer:
 passed.
* 
build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level:
 passed.
* 
build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory:
 passed.
* 
build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token:
 passed.
* build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: passed.
* build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: passed.
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: passed.
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: passed.
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp:
 passed.
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp:
 passed.
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level:
 passed.
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic: 
passed.
* 
build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp:
 passed.
* 
build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple:
 passed.
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic: passed.
* build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: 
passed.
* build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: 
passed.
* 
build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic:
 passed.
* build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: 
passed.
* build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic: passed.
* build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic: passed.
* build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: 
passed.
* 
build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level:
 passed.
* build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing: passed.
* build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic: passed.
* build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby: 
passed.
* 
build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple:
 passed.
* build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing: passed.
* build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing: passed.
* build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic: passed.
*

Re: [gem5-dev] Review Request 3710: cpu: Resolve targets of predicted 'taken' conditional direct branches at decode (o3)

2016-11-22 Thread Nathanael Premillieu 

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Ship it!


Ship It!

- Nathanael Premillieu


On Nov. 18, 2016, 3:21 p.m., Arthur Perais wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3710/
> ---
> 
> (Updated Nov. 18, 2016, 3:21 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11707:1d085f66c4ca
> ---
> cpu: Resolve targets of predicted 'taken' conditional direct branches at 
> decode (o3)
> 
> The target of taken conditional direct branches does not 
> need to be resolved in IEW: the target can be computed at 
> decode, usually using the decoded instruction word and the PC.
> 
> The higher-than-necessary penalty is taken only on conditional
> branches that are predicted taken but miss in the BTB. Thus, 
> this is mostly inconsequential on IPC if the BTB is big/associative 
> enough (fewer capacity/conflict misses). Nonetheless, what gem5 
> simulates is not representative of how conditional branch targets 
> can be handled.
> 
> 
> Diffs
> -
> 
>   src/cpu/o3/decode_impl.hh c38fcdaa5fe5 
> 
> Diff: http://reviews.gem5.org/r/3710/diff/
> 
> 
> Testing
> ---
> 
> util/regress --modes=se
> 
> build/NULL/tests/opt/quick/se/51.memcheck/null/none/memcheck: FAILED! (Python 
> says "NameError: name 'TrafficGen' is not defined"). I'm guessing this is OK 
> as I get the same error without my patch.
> 
> 
> Thanks,
> 
> Arthur Perais
> 
>

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Re: [gem5-dev] Review Request 3740: commit 8606171b2c2e65d0b9931ccb4bd2ebc533c55d60

2016-11-22 Thread Pierre-Yves Péneau 

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This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/3740/#review9148
---

Ship it!


Ship It!

- Pierre-Yves Péneau


On Nov. 21, 2016, 8:03 p.m., Rahul Thakur wrote:
> 
> ---
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/3740/
> ---
> 
> (Updated Nov. 21, 2016, 8:03 p.m.)
> 
> 
> Review request for Default.
> 
> 
> Repository: gem5
> 
> 
> Description
> ---
> 
> Changeset 11708:33c0089caa50
> ---
> commit 8606171b2c2e65d0b9931ccb4bd2ebc533c55d60
> Author: Rahul Thakur 
> Date:   Thu Oct 27 20:36:16 2016 -0700
> 
> mem: Refactor CommMonitor stats, add basic atomic mode stats
> 
> Change-Id: I978f1155873b3882e16d9cd74e86400efd9c5e3b
> 
> 
> Diffs
> -
> 
>   src/mem/comm_monitor.hh 1d085f66c4ca 
>   src/mem/comm_monitor.cc 1d085f66c4ca 
> 
> Diff: http://reviews.gem5.org/r/3740/diff/
> 
> 
> Testing
> ---
> 
> 
> Thanks,
> 
> Rahul Thakur
> 
>

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