[gem5-dev] Change in gem5/gem5[master]: mem-cache: Handle data expansion
Hello Daniel Carvalho, Jason Lowe-Power, Nikos Nikoleris, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/12087 to look at the new patch set (#6). Change subject: mem-cache: Handle data expansion .. mem-cache: Handle data expansion When a block in compressed form is overwriten, it may change its size. If the new compressed size is bigger, and the total size becomes bigger than the block size, one or more blocks will have to be evicted. This is called data expansion, or fat writes. This patch adds the functionality to handle data expansions by evicting the co-allocated blocks to make room for an expanded block. As a side effect, cmpAndSwap() and satisfyRequest() must now return writebacks. Change-Id: I0bd77bf6446bfae336889940b2f75d6f0c87e533 Signed-off-by: Daniel R. Carvalho --- M src/mem/cache/base.cc M src/mem/cache/base.hh M src/mem/cache/cache.cc M src/mem/cache/cache.hh M src/mem/cache/noncoherent_cache.cc M src/mem/cache/noncoherent_cache.hh M src/mem/cache/tags/compressed_tags.cc M src/mem/cache/tags/compressed_tags.hh 8 files changed, 247 insertions(+), 29 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/12087 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I0bd77bf6446bfae336889940b2f75d6f0c87e533 Gerrit-Change-Number: 12087 Gerrit-PatchSet: 6 Gerrit-Owner: Daniel Carvalho Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Add compression and decompression calls
Hello Daniel Carvalho, Jason Lowe-Power, Nikos Nikoleris, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/11410 to look at the new patch set (#9). Change subject: mem-cache: Add compression and decompression calls .. mem-cache: Add compression and decompression calls Add a compressor to the base cache class and compress within block allocation and decompress on writebacks. This change does not implement data expansion (fat writes) yet, nor it adds the compression latency to the block write time. Change-Id: Ie36db65f7487c9b05ec4aedebc2c7651b4cb4821 --- M src/mem/cache/Cache.py M src/mem/cache/base.cc M src/mem/cache/base.hh M src/mem/cache/compressors/base.cc M src/mem/cache/compressors/base.hh M src/mem/cache/tags/compressed_tags.cc M src/mem/cache/tags/compressed_tags.hh 7 files changed, 110 insertions(+), 5 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/11410 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ie36db65f7487c9b05ec4aedebc2c7651b4cb4821 Gerrit-Change-Number: 11410 Gerrit-PatchSet: 9 Gerrit-Owner: Daniel Carvalho Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-CC: Daniel Carvalho Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Add co-allocation function to compressed tags
Hello Daniel Carvalho, Jason Lowe-Power, Nikos Nikoleris, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/11411 to look at the new patch set (#9). Change subject: mem-cache: Add co-allocation function to compressed tags .. mem-cache: Add co-allocation function to compressed tags Implement a co-allocation function in compressed tags, so that compressed blocks can be co-allocated in a superblock. Co-allocation is possible when compression ratio (CR) blocks that share a superblock tag can be compressed to up to (100/CR)% of their size. Change-Id: I937cc1fcbb488e70309cb5478c12db65f1b4b23f --- M src/mem/cache/tags/compressed_tags.cc M src/mem/cache/tags/compressed_tags.hh 2 files changed, 102 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/11411 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I937cc1fcbb488e70309cb5478c12db65f1b4b23f Gerrit-Change-Number: 11411 Gerrit-PatchSet: 9 Gerrit-Owner: Daniel Carvalho Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Stub compression framework
Hello Daniel Carvalho, Jason Lowe-Power, Nikos Nikoleris, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/10763 to look at the new patch set (#12). Change subject: mem-cache: Stub compression framework .. mem-cache: Stub compression framework Create a stub of a compression framework where we can have multiple data blocks per tag entry. Only consecutive blocks can share a tag as of now. For each tag entry there can be multiple data blocks. We have the same number of tags a conventional cache would have, but we instantiate the maximum number of data blocks (according to the compression ratio) per tag, to virtually implement compression without increasing the complexity of the simulator. Change-Id: I549940c7afb2f744ab293ff8bb283967e7551a11 --- M src/mem/cache/tags/SConscript M src/mem/cache/tags/Tags.py A src/mem/cache/tags/compressed_tags.cc A src/mem/cache/tags/compressed_tags.hh M src/mem/cache/tags/sector_blk.hh M src/mem/cache/tags/sector_tags.cc M src/mem/cache/tags/sector_tags.hh A src/mem/cache/tags/super_blk.cc A src/mem/cache/tags/super_blk.hh 9 files changed, 386 insertions(+), 10 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/10763 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I549940c7afb2f744ab293ff8bb283967e7551a11 Gerrit-Change-Number: 10763 Gerrit-PatchSet: 12 Gerrit-Owner: Daniel Carvalho Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Nikos Nikoleris Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: mem-cache: Irregular Stream Buffer Prefetcher
Javier Bueno Hedo has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/15215
Change subject: mem-cache: Irregular Stream Buffer Prefetcher
..
mem-cache: Irregular Stream Buffer Prefetcher
Based in the description of the following publication:
Akanksha Jain and Calvin Lin. 2013. Linearizing irregar memory accesses
for improved correlated prefetching. In Proceedings of the 46th Annual
IEEE/ACM International Symposium on Microarchitecture (MICRO-46). ACM,
New York, NY, USA, 247-259.
Change-Id: Ibeb6abc93ca40ad634df6ed5cf8becb0a49d1165
---
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/prefetch/SConscript
A src/mem/cache/prefetch/associative_set.hh
A src/mem/cache/prefetch/associative_set_impl.hh
A src/mem/cache/prefetch/irregular_stream_buffer.cc
A src/mem/cache/prefetch/irregular_stream_buffer.hh
6 files changed, 667 insertions(+), 1 deletion(-)
diff --git a/src/mem/cache/prefetch/Prefetcher.py
b/src/mem/cache/prefetch/Prefetcher.py
index df547ed..ec650b5 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -44,6 +44,7 @@
from m5.params import *
from m5.proxy import *
from ReplacementPolicies import *
+from IndexingPolicies import *
class HWPProbeEvent(object):
def __init__(self, prefetcher, obj, *listOfNames):
@@ -139,3 +140,47 @@
cxx_header = "mem/cache/prefetch/tagged.hh"
degree = Param.Int(2, "Number of prefetches to generate")
+
+class IrregularStreamBufferPrefetcher(QueuedPrefetcher):
+type = "IrregularStreamBufferPrefetcher"
+cxx_class = "IrregularStreamBufferPrefetcher"
+cxx_header = "mem/cache/prefetch/irregular_stream_buffer.hh"
+
+max_counter_value = Param.Unsigned(3,
+"Maximum value of the confidence counter")
+chunk_size = Param.Unsigned(256,
+"Maximum number of addresses in a temporal stream")
+degree = Param.Unsigned(4, "Number of prefetches to generate")
+training_unit_assoc = Param.Unsigned(128,
+"Associativity of the training unit")
+training_unit_entries = Param.MemorySize("128",
+"Number of entries of the training unit")
+training_unit_indexing_policy = Param.BaseIndexingPolicy(
+SetAssociative(entry_size = 1, assoc = Parent.training_unit_assoc,
+size = Parent.training_unit_entries),
+"Indexing policy of the training unit")
+training_unit_replacement_policy = Param.BaseReplacementPolicy(LRURP(),
+"Replacement policy of the training unit")
+
+prefetch_candidates_per_entry = Param.Unsigned(16,
+"Number of prefetch candidates stored in a SP-AMC entry")
+address_map_cache_assoc = Param.Unsigned(128,
+"Associativity of the PS/SP AMCs")
+address_map_cache_entries = Param.MemorySize("128",
+"Number of entries of the PS/SP AMCs")
+ps_address_map_cache_indexing_policy = Param.BaseIndexingPolicy(
+SetAssociative(entry_size = 1,
+assoc = Parent.address_map_cache_assoc,
+size = Parent.address_map_cache_entries),
+"Indexing policy of the Physical-to-Structural Address Map Cache")
+ps_address_map_cache_replacement_policy = Param.BaseReplacementPolicy(
+LRURP(),
+"Replacement policy of the Physical-to-Structural Address Map
Cache")
+sp_address_map_cache_indexing_policy = Param.BaseIndexingPolicy(
+SetAssociative(entry_size = 1,
+assoc = Parent.address_map_cache_assoc,
+size = Parent.address_map_cache_entries),
+"Indexing policy of the Structural-to-Physical Address Mao Cache")
+sp_address_map_cache_replacement_policy = Param.BaseReplacementPolicy(
+LRURP(),
+"Replacement policy of the Structural-to-Physical Address Map
Cache")
diff --git a/src/mem/cache/prefetch/SConscript
b/src/mem/cache/prefetch/SConscript
index 2665d18..00e1dac 100644
--- a/src/mem/cache/prefetch/SConscript
+++ b/src/mem/cache/prefetch/SConscript
@@ -36,4 +36,4 @@
Source('queued.cc')
Source('stride.cc')
Source('tagged.cc')
-
+Source('irregular_stream_buffer.cc')
diff --git a/src/mem/cache/prefetch/associative_set.hh
b/src/mem/cache/prefetch/associative_set.hh
new file mode 100644
index 000..f2314d9
--- /dev/null
+++ b/src/mem/cache/prefetch/associative_set.hh
@@ -0,0 +1,195 @@
+/**
+ * Copyright (c) 2018 Metempsy Technology Consulting
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of
