[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Fixing Topology
Pouya Fotouhi has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/15716 )
Change subject: mem-ruby: Fixing Topology
..
mem-ruby: Fixing Topology
The constructor assumes the number of nodes (i.e. controllers) equal to
the number of external nodes.
This is a not necessarily valid for all cases (e.g MESI_Three_Level -
where L0s are directly connected to L1s).
MachineType_base_number(MachineType_NUM) provides the total number of
controllers.
Signed-off-by: Pouya Fotouhi
Change-Id: Id906099dc967ec70aa34dedb0b55351031ff242c
Reviewed-on: https://gem5-review.googlesource.com/c/15716
Reviewed-by: Jason Lowe-Power
Reviewed-by: Nikos Nikoleris
Maintainer: Jason Lowe-Power
---
M src/mem/ruby/network/Topology.cc
1 file changed, 2 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved
diff --git a/src/mem/ruby/network/Topology.cc
b/src/mem/ruby/network/Topology.cc
index f7afffd..6da251e 100644
--- a/src/mem/ruby/network/Topology.cc
+++ b/src/mem/ruby/network/Topology.cc
@@ -51,7 +51,8 @@
Topology::Topology(uint32_t num_routers,
const vector _links,
const vector _links)
-: m_nodes(ext_links.size()), m_number_of_switches(num_routers),
+: m_nodes(MachineType_base_number(MachineType_NUM)),
+ m_number_of_switches(num_routers),
m_ext_link_vector(ext_links), m_int_link_vector(int_links)
{
// Total nodes/controllers in network
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Id906099dc967ec70aa34dedb0b55351031ff242c
Gerrit-Change-Number: 15716
Gerrit-PatchSet: 2
Gerrit-Owner: Pouya Fotouhi
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: Pouya Fotouhi
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: mem-ruby: Fixing MESI Three Level
Pouya Fotouhi has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/15715 )
Change subject: mem-ruby: Fixing MESI Three Level
..
mem-ruby: Fixing MESI Three Level
Adding back some changes done in patch 676ae57827.
Transient state IS_I, STALE_DATA, Data_Stale event are necessary.
Issue: (cacheline A, initial state for P0 and P1 is I)
| P0 | P1 |
|GETX (A)||
||GETS (A)|
|Inv_All ||
P1 never sends the ACK - deadlock
It should ACK, later upon data use it as stale data, and got to I.
Solution:
P1(A):
GETS:I->IS
Inv_All: IS->IS_I, Send ACK
Data:IS_I->I, STALE_DATA to L0
Signed-off-by: Pouya Fotouhi
Change-Id: I1e7b2c05439d08579c68d8eb444e0f332e75e07f
Reviewed-on: https://gem5-review.googlesource.com/c/15715
Reviewed-by: Jason Lowe-Power
Reviewed-by: Nikos Nikoleris
Maintainer: Jason Lowe-Power
---
M src/mem/protocol/MESI_Three_Level-L0cache.sm
M src/mem/protocol/MESI_Three_Level-L1cache.sm
M src/mem/protocol/MESI_Three_Level-msg.sm
3 files changed, 70 insertions(+), 4 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Nikos Nikoleris: Looks good to me, approved
diff --git a/src/mem/protocol/MESI_Three_Level-L0cache.sm
b/src/mem/protocol/MESI_Three_Level-L0cache.sm
index 4950d63..a87a3d9 100644
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm
@@ -101,6 +101,7 @@
Data, desc="Data for processor";
Data_Exclusive, desc="Data for processor";
+Data_Stale, desc="Data for processor, but not for storage";
Ack,desc="Ack for processor";
Ack_all, desc="Last ack for processor";
@@ -268,6 +269,8 @@
trigger(Event:Data_Exclusive, in_msg.addr, cache_entry, tbe);
} else if(in_msg.Class == CoherenceClass:DATA) {
trigger(Event:Data, in_msg.addr, cache_entry, tbe);
+} else if(in_msg.Class == CoherenceClass:STALE_DATA) {
+trigger(Event:Data_Stale, in_msg.addr, cache_entry, tbe);
} else if (in_msg.Class == CoherenceClass:ACK) {
trigger(Event:Ack, in_msg.addr, cache_entry, tbe);
} else if (in_msg.Class == CoherenceClass:WB_ACK) {
@@ -732,6 +735,15 @@
kd_wakeUpDependents;
}
+ transition(IS, Data_Stale, I) {
+u_writeDataToCache;
+hx_load_hit;
+s_deallocateTBE;
+ff_deallocateCacheBlock;
+o_popIncomingResponseQueue;
+kd_wakeUpDependents;
+ }
+
transition(Inst_IS, Data, S) {
u_writeInstToCache;
hx_ifetch_hit;
@@ -748,6 +760,15 @@
kd_wakeUpDependents;
}
+ transition(Inst_IS, Data_Stale, I) {
+u_writeInstToCache;
+hx_ifetch_hit;
+s_deallocateTBE;
+ff_deallocateCacheBlock;
+o_popIncomingResponseQueue;
+kd_wakeUpDependents;
+ }
+
transition({IM,SM}, Data_Exclusive, M) {
u_writeDataToCache;
hhx_store_hit;
diff --git a/src/mem/protocol/MESI_Three_Level-L1cache.sm
b/src/mem/protocol/MESI_Three_Level-L1cache.sm
index e960486..6db35ce 100644
--- a/src/mem/protocol/MESI_Three_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm
@@ -71,6 +71,7 @@
IS, AccessPermission:Busy, desc="L1 idle, issued GETS, have not seen
response yet";
IM, AccessPermission:Busy, desc="L1 idle, issued GETX, have not seen
response yet";
SM, AccessPermission:Read_Only, desc="L1 idle, issued GETX, have not
seen response yet";
+IS_I, AccessPermission:Busy, desc="L1 idle, issued GETS, saw Inv
before data because directory doesn't block on GETS hit";
M_I, AccessPermission:Busy, desc="L1 replacing, waiting for ACK";
SINK_WB_ACK, AccessPermission:Busy, desc="This is to sink WB_Acks from
L2";
@@ -278,7 +279,8 @@
if(in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
trigger(Event:Data_Exclusive, in_msg.addr, cache_entry, tbe);
} else if(in_msg.Type == CoherenceResponseType:DATA) {
- if (getState(tbe, cache_entry, in_msg.addr) == State:IS &&
+ if ((getState(tbe, cache_entry, in_msg.addr) == State:IS ||
+ getState(tbe, cache_entry, in_msg.addr) == State:IS_I) &&
machineIDToMachineType(in_msg.Sender) ==
MachineType:L1Cache) {
trigger(Event:DataS_fromL1, in_msg.addr, cache_entry, tbe);
@@ -626,6 +628,20 @@
}
}
+ action(h_stale_data_to_l0, "hs", desc="If not prefetch, send data to the
L0 cache.") {
+ enqueue(bufferToL0_out, CoherenceMsg, l1_response_latency) {
+ assert(is_valid(cache_entry));
+
+ out_msg.addr := address;
+ out_msg.Class := CoherenceClass:STALE_DATA;
+ out_msg.Sender := machineID;
+ out_msg.Dest := createMachineID(MachineType:L0Cache, version);
+ out_msg.DataBlk := cache_entry.DataBlk;
+ out_msg.Dirty := cache_entry.Dirty;
[gem5-dev] Change in gem5/gem5[master]: systemc: config: Don't inject a custom argv[0] in sc_main.py.
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/16342 )
Change subject: systemc: config: Don't inject a custom argv[0] in
sc_main.py.
..
systemc: config: Don't inject a custom argv[0] in sc_main.py.
argv[0] is already part of sys.argv, so we don't need to add an
additional argument in front of sys.argv.
The argv[0] which is used in gem5 config scripts is the name of the
config script itself. While it might seem a little odd for the name of
a systemc program to end in .py, it's as arbitrary as any other name,
and generally shouldn't cause a problem. If some other more
sophisticated mechanism for setting argv[0] is necessary, then the user
can write a very slightly more complicated version of this script with
additional logic.
Change-Id: Ifd5d8a02d3cd5db76054151ed6c7a7b1f8495fa8
Reviewed-on: https://gem5-review.googlesource.com/c/16342
Reviewed-by: Jason Lowe-Power
Maintainer: Gabe Black
---
M configs/example/sc_main.py
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Gabe Black: Looks good to me, approved
diff --git a/configs/example/sc_main.py b/configs/example/sc_main.py
index dad987b..293c76e 100755
--- a/configs/example/sc_main.py
+++ b/configs/example/sc_main.py
@@ -37,7 +37,7 @@
kernel = SystemC_Kernel()
root = Root(full_system=True, systemc_kernel=kernel)
-kernel.sc_main('gem5_systemc', *sys.argv)
+kernel.sc_main(*sys.argv)
m5.instantiate(None)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ifd5d8a02d3cd5db76054151ed6c7a7b1f8495fa8
Gerrit-Change-Number: 16342
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthias Jung
Gerrit-Reviewer: Weiping Liao
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: systemc: config: Don't inject a custom argv[0] in sc_main.py.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/16342
Change subject: systemc: config: Don't inject a custom argv[0] in
sc_main.py.
..
systemc: config: Don't inject a custom argv[0] in sc_main.py.
argv[0] is already part of sys.argv, so we don't need to add an
additional argument in front of sys.argv.
The argv[0] which is used in gem5 config scripts is the name of the
config script itself. While it might seem a little odd for the name of
a systemc program to end in .py, it's as arbitrary as any other name,
and generally shouldn't cause a problem. If some other more
sophisticated mechanism for setting argv[0] is necessary, then the user
can write a very slightly more complicated version of this script with
additional logic.
Change-Id: Ifd5d8a02d3cd5db76054151ed6c7a7b1f8495fa8
---
M configs/example/sc_main.py
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/example/sc_main.py b/configs/example/sc_main.py
index dad987b..293c76e 100755
--- a/configs/example/sc_main.py
+++ b/configs/example/sc_main.py
@@ -37,7 +37,7 @@
kernel = SystemC_Kernel()
root = Root(full_system=True, systemc_kernel=kernel)
-kernel.sc_main('gem5_systemc', *sys.argv)
+kernel.sc_main(*sys.argv)
m5.instantiate(None)
--
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Gerrit-Change-Number: 16342
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Cron /z/m5/regression/do-regression quick
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: FAILED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: CHANGED! * build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED! * build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer: CHANGED! * build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level: CHANGED! * build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory: CHANGED! * build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing: CHANGED! *
[gem5-dev] Change in gem5/gem5[master]: misc: Segmentation Fault during O3PipeView execution
Andrea Mondelli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/16322
Change subject: misc: Segmentation Fault during O3PipeView execution
..
misc: Segmentation Fault during O3PipeView execution
During the O3PipeView execution, a potential invalid iterator is used to
Update the instruction storeTick field.
If the store_idx iterator is the first() of the StoreQueue, the
corresponding instruction is removed from the queue, leaving the iterator
invalid and not usable in the TRACING_ON block.
This patch uses the store_inst variable to access (and update) the
instruction tick, instead of the (potential) invalid one.
Change-Id: I671052ef282b9048e5239da8629b89e8afa86bf0
---
M src/cpu/o3/lsq_unit_impl.hh
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 48179ce..4ce050f 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -999,8 +999,8 @@
#if TRACING_ON
if (DTRACE(O3PipeView)) {
-store_idx->instruction()->storeTick =
-curTick() - store_idx->instruction()->fetchTick;
+store_inst->storeTick =
+curTick() - store_inst->fetchTick;
}
#endif
--
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Gerrit-Owner: Andrea Mondelli
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[gem5-dev] Change in gem5/gem5[master]: python: Switch to using open instead of file
Andreas Sandberg has uploaded a new patch set (#3). ( https://gem5-review.googlesource.com/c/public/gem5/+/15985 ) Change subject: python: Switch to using open instead of file .. python: Switch to using open instead of file Python 3 doesn't support the file(name, mode) syntax which has been deprecated in favour of open. Change-Id: I35ef8690d97a5243860a64ff985fd22fa86253f1 Signed-off-by: Andreas Sandberg --- M src/python/importer.py M src/python/m5/main.py M src/python/m5/simulate.py M src/python/m5/util/code_formatter.py M src/python/m5/util/grammar.py 5 files changed, 7 insertions(+), 6 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/15985 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I35ef8690d97a5243860a64ff985fd22fa86253f1 Gerrit-Change-Number: 15985 Gerrit-PatchSet: 3 Gerrit-Owner: Andreas Sandberg Gerrit-CC: Giacomo Travaglini Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-mips: Remove unused Python file
Andreas Sandberg has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/16302 Change subject: arch-mips: Remove unused Python file .. arch-mips: Remove unused Python file Change-Id: I7155915fccdec1d9f116f2a8617474188a91165b Signed-off-by: Andreas Sandberg --- D src/arch/mips/MipsCPU.py 1 file changed, 0 insertions(+), 92 deletions(-) diff --git a/src/arch/mips/MipsCPU.py b/src/arch/mips/MipsCPU.py deleted file mode 100644 index 48ee417..000 --- a/src/arch/mips/MipsCPU.py +++ /dev/null @@ -1,92 +0,0 @@ -# -*- mode:python -*- - -# Copyright (c) 2007 MIPS Technologies, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Jaidev Patwardhan -# Korey Sewell - -from m5.defines import buildEnv -from m5.params import * - -from BaseCPU import BaseCPU - -class BaseMipsCPU(BaseCPU) -if buildEnv['TARGET_ISA'] == 'mips': -CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description") -CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description") -CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description") -CP0_EBase_CPUNum = Param.Unsigned(0,"No Description") -CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register") -CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register") -CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company") -CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register") -CP0_Config_BE = Param.Unsigned(0,"Big Endian?") -CP0_Config_AT = Param.Unsigned(0,"No Description") -CP0_Config_AR = Param.Unsigned(0,"No Description") -CP0_Config_MT = Param.Unsigned(0,"No Description") -CP0_Config_VI = Param.Unsigned(0,"No Description") -CP0_Config1_M = Param.Unsigned(0,"Config2 Implemented?") -CP0_Config1_MMU = Param.Unsigned(0,"MMU Type") -CP0_Config1_IS = Param.Unsigned(0,"No Description") -CP0_Config1_IL = Param.Unsigned(0,"No Description") -CP0_Config1_IA = Param.Unsigned(0,"No Description") -CP0_Config1_DS = Param.Unsigned(0,"No Description") -CP0_Config1_DL = Param.Unsigned(0,"No Description") -CP0_Config1_DA = Param.Unsigned(0,"No Description") -CP0_Config1_C2 = Param.Bool(False,"No Description") -CP0_Config1_MD = Param.Bool(False,"No Description") -CP0_Config1_PC = Param.Bool(False,"No Description") -CP0_Config1_WR = Param.Bool(False,"No Description") -CP0_Config1_CA = Param.Bool(False,"No Description") -CP0_Config1_EP = Param.Bool(False,"No Description") -CP0_Config1_FP = Param.Bool(False,"FPU Implemented?") -CP0_Config2_M = Param.Bool(False,"Config3 Implemented?") -CP0_Config2_TU = Param.Unsigned(0,"No Description") -CP0_Config2_TS = Param.Unsigned(0,"No Description") -CP0_Config2_TL = Param.Unsigned(0,"No Description") -CP0_Config2_TA = Param.Unsigned(0,"No Description") -CP0_Config2_SU = Param.Unsigned(0,"No Description") -CP0_Config2_SS = Param.Unsigned(0,"No Description") -CP0_Config2_SL = Param.Unsigned(0,"No Description") -CP0_Config2_SA = Param.Unsigned(0,"No Description") -CP0_Config3_M = Param.Bool(False,"Config4 Implemented?") -CP0_Config3_DSPP = Param.Bool(False,"DSP Extensions
Re: [gem5-dev] register API thoughts
Hi Gabe, yes I can open the document now. Will have a closer look at it today Regards Giacomo From: gem5-dev on behalf of Gabe Black Sent: 09 February 2019 00:23 To: gem5 Developer List Subject: Re: [gem5-dev] register API thoughts Hi folks. Could you please confirm you can open this document now? Some feedback would be appreciated! Gabe On Tue, Feb 5, 2019 at 5:57 PM Gabe Black wrote: > Bump > > On Fri, Feb 1, 2019 at 1:27 AM Gabe Black wrote: > >> Apparently I can't share things publicly from my work account, so here's >> a copy of it I made on my personal account: >> >> >> https://docs.google.com/document/d/1O_u_Xq14TgreYThuZcbM3kuXFCrKvaFHA2O9poCeHSk/edit?usp=sharing >> >> On Fri, Feb 1, 2019 at 1:23 AM Gabe Black wrote: >> >>> Ok, it looks like "publish to the web" just translates it into a web >>> page but doesn't actually make it public like the name would suggest. I'll >>> see if I can figure out how to share it publicly, and if not I'll move it >>> to my personal account and try from there. Stay tuned. >>> >>> Gabe >>> >>> On Thu, Jan 31, 2019 at 11:37 PM Giacomo Travaglini < >>> giacomo.travagl...@arm.com> wrote: >>> Hi Gabe, I've tried, but I cannot follow the link, since google docs asks for permissions: You need permission to access this published document. Thanks Giacomo From: gem5-dev on behalf of Gabe Black < gabebl...@google.com> Sent: 01 February 2019 01:07:34 To: gem5 Developer List Subject: [gem5-dev] register API thoughts Hi folks. I wrote up a document talking about the register API here: https://docs.google.com/a/google.com/document/d/e/2PACX-1vSTZIUgzFVSFt25Bqxl5bJ8MjZ0xpldvWJi--I1WxNay3I5-ADt_o6Bgn8jXObR92mprBGQR1KpPVnv/pub This is the first time I've tried sharing a document by "publishing it to the web" so I'm not sure what it will look like to you, but please give it a look if you're interested. I'd say my ideas there are about 80-90% baked, and there are definitely some gaps to fill in. There's some high level info about register indexing on gem5.org as well, if you want some background reading: http://gem5.org/Architectural_State http://gem5.org/Register_Indexing Gabe ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev >>> >>> ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
