[gem5-dev] Cron /z/m5/regression/do-regression quick
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing-ruby: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-atomic: FAILED! * build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64f/o3-timing: FAILED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby: CHANGED! * build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing: CHANGED! * build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual: CHANGED! * build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing: CHANGED! * build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level: CHANGED! * build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby: CHANGED! * build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp: CHANGED! * build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem: CHANGED! * build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl: CHANGED! * build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer: CHANGED! * build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level: CHANGED! * build/NULL_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_directory: CHANGED! * build/NULL_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_CMP_token: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic: CHANGED! * build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple: CHANGED! * build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing: CHANGED! * build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp: CHANGED! * build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp: CHANGED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing: CHANGED! * build/SPARC/tests/opt/quick/se/10.mcf/sparc/linux/simple-atomic: CHANGED! * build/SPARC/tests/opt/quick/se/70.twolf/sparc/linux/simple-timing: CHANGED! * build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic: CHANGED! * build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple: CHANGED! *
[gem5-dev] Change in gem5/gem5[master]: arch-generic: Making base TLB class a MemObject
Ivan Pizarro has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/14117 )
Change subject: arch-generic: Making base TLB class a MemObject
..
arch-generic: Making base TLB class a MemObject
Allow configuring a TLB hierarchy using ports
Change-Id: I1f791829d4e072a9104e67eacf69a69de9543634
Reviewed-on: https://gem5-review.googlesource.com/c/14117
Reviewed-by: Andreas Sandberg
Reviewed-by: Anthony Gutierrez
Maintainer: Andreas Sandberg
---
M src/arch/generic/BaseTLB.py
M src/arch/generic/tlb.hh
2 files changed, 11 insertions(+), 5 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Anthony Gutierrez: Looks good to me, approved
diff --git a/src/arch/generic/BaseTLB.py b/src/arch/generic/BaseTLB.py
index 6a8a972..b98b993 100644
--- a/src/arch/generic/BaseTLB.py
+++ b/src/arch/generic/BaseTLB.py
@@ -1,4 +1,5 @@
# Copyright (c) 2008 The Hewlett-Packard Development Company
+# Copyright (c) 2018 Metempsy Technology Consulting
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -25,10 +26,15 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
+# Ivan Pizarro
-from m5.SimObject import SimObject
+from m5.params import *
+from MemObject import MemObject
-class BaseTLB(SimObject):
+class BaseTLB(MemObject):
type = 'BaseTLB'
abstract = True
cxx_header = "arch/generic/tlb.hh"
+# Ports to connect with other TLB levels
+slave = VectorSlavePort("Port closer to the CPU side")
+master = MasterPort("Port closer to memory side")
diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh
index 8918034..91f8f86 100644
--- a/src/arch/generic/tlb.hh
+++ b/src/arch/generic/tlb.hh
@@ -44,17 +44,17 @@
#define __ARCH_GENERIC_TLB_HH__
#include "base/logging.hh"
+#include "mem/mem_object.hh"
#include "mem/request.hh"
-#include "sim/sim_object.hh"
class ThreadContext;
class BaseMasterPort;
-class BaseTLB : public SimObject
+class BaseTLB : public MemObject
{
protected:
BaseTLB(const Params *p)
-: SimObject(p)
+: MemObject(p)
{}
public:
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14117
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I1f791829d4e072a9104e67eacf69a69de9543634
Gerrit-Change-Number: 14117
Gerrit-PatchSet: 5
Gerrit-Owner: Ivan Pizarro
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Ivan Pizarro
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: Move GICv3 detection at startup time
Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/16483 )
Change subject: arch-arm: Move GICv3 detection at startup time
..
arch-arm: Move GICv3 detection at startup time
At the moment the haveGicV3 parameter is used only to signal its
presence when reading the MISCREG_ID_AA64PFR0_EL1 register. It depends
on the system->getGIC pointing to a GICv3 model. However this pointer
is set in the System only at init time (after construction), which means
that the haveGICv3CPUInterface will always be false.
This patch is fixing this by moving the parameter initialization at
startup time, together with the cpu interface registration.
Change-Id: I8da6711ea741ecd0f78ec8ca60a8c3ae3bca2421
Signed-off-by: Giacomo Travaglini
Reviewed-by: Anouk Van Laer
Reviewed-on: https://gem5-review.googlesource.com/c/16483
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
---
M src/arch/arm/isa.cc
1 file changed, 2 insertions(+), 7 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 97de97e..3b10f68 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -64,6 +64,7 @@
_decoderFlavour(p->decoderFlavour),
_vecRegRenameMode(Enums::Full),
pmu(p->pmu),
+ haveGICv3CPUInterface(false),
impdefAsNop(p->impdef_nop)
{
miscRegs[MISCREG_SCTLR_RST] = 0;
@@ -96,13 +97,6 @@
physAddrRange = 32; // dummy value
}
-// GICv3 CPU interface system registers are supported
-haveGICv3CPUInterface = false;
-
-if (system && dynamic_cast(system->getGIC())) {
-haveGICv3CPUInterface = true;
-}
-
// Initial rename mode depends on highestEL
const_cast(_vecRegRenameMode) =
highestELIs64 ? Enums::Full : Enums::Elem;
@@ -388,6 +382,7 @@
if (system) {
Gicv3 *gicv3 = dynamic_cast(system->getGIC());
if (gicv3) {
+haveGICv3CPUInterface = true;
gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
gicv3CpuInterface->setISA(this);
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16483
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I8da6711ea741ecd0f78ec8ca60a8c3ae3bca2421
Gerrit-Change-Number: 16483
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Anouk Van Laer
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: dev-arm: LPI support for GICv3. This doesn't include an ITS model.
Hello Giacomo Travaglini, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/16142 to look at the new patch set (#6). Change subject: dev-arm: LPI support for GICv3. This doesn't include an ITS model. .. dev-arm: LPI support for GICv3. This doesn't include an ITS model. Change-Id: Ia2c02cca4f95672d6361fba16201a56e2047ddb7 --- M src/dev/arm/gic_v3_cpu_interface.cc M src/dev/arm/gic_v3_distributor.cc M src/dev/arm/gic_v3_redistributor.cc M src/dev/arm/gic_v3_redistributor.hh 4 files changed, 276 insertions(+), 8 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16142 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ia2c02cca4f95672d6361fba16201a56e2047ddb7 Gerrit-Change-Number: 16142 Gerrit-PatchSet: 6 Gerrit-Owner: Jairo Balart Gerrit-Reviewer: Giacomo Travaglini Gerrit-Reviewer: Jairo Balart Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: base: Fix enums checkpointing
Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/16382 )
Change subject: base: Fix enums checkpointing
..
base: Fix enums checkpointing
Creating an extra version of string to number converters (__to_number)
in base/str.hh; it will be used by enums only when unserializing
them. The reason not to have a single helper for both enums and
integers is that std::numeric_limits trait is not specialized for enums.
We fix this by using the std::underlying_type trait.
Change-Id: I819e35c0df8c094de7b7a6390152964fa47d513d
Signed-off-by: Giacomo Travaglini
Reviewed-by: Ciro Santilli
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/16382
Reviewed-by: Daniel Carvalho
Reviewed-by: Andreas Sandberg
Maintainer: Jason Lowe-Power
---
M src/base/str.hh
1 file changed, 11 insertions(+), 4 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
diff --git a/src/base/str.hh b/src/base/str.hh
index 61022bd..1ea18b7 100644
--- a/src/base/str.hh
+++ b/src/base/str.hh
@@ -40,6 +40,7 @@
#include
#include
#include
+#include
#include
#include "base/logging.hh"
@@ -108,8 +109,7 @@
* integeral type, as well as enums and floating-point types.
*/
template
-typename std::enable_if<(std::is_integral::value ||
-std::is_enum::value) &&
+typename std::enable_if::value &&
std::is_signed::value, T>::type
__to_number(const std::string )
{
@@ -121,8 +121,7 @@
}
template
-typename std::enable_if<(std::is_integral::value ||
-std::is_enum::value) &&
+typename std::enable_if::value &&
!std::is_signed::value, T>::type
__to_number(const std::string )
{
@@ -134,6 +133,14 @@
}
template
+typename std::enable_if::value, T>::type
+__to_number(const std::string )
+{
+auto r = __to_number::type>(value);
+return static_cast(r);
+}
+
+template
typename std::enable_if::value, T>::type
__to_number(const std::string )
{
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16382
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I819e35c0df8c094de7b7a6390152964fa47d513d
Gerrit-Change-Number: 16382
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-MessageType: merged
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