[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: mem-ruby: Deep renaming of Prefetcher to RubyPrefetcher
Ayaz Akram has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28667 )
Change subject: mem-ruby: Deep renaming of Prefetcher to RubyPrefetcher
..
mem-ruby: Deep renaming of Prefetcher to RubyPrefetcher
A recent change (https://gem5-review.googlesource.com/c/
public/gem5/+/27949) updated the ruby prefetcher name,
which breaks the use of old name in some SLICC files.
This change makes sure that the new name is used at all
places.
JIRA: https://gem5.atlassian.net/browse/GEM5-498
Change-Id: Ic667b61eac13dc7c267cee7dce3aa970f7ae9a8b
---
M src/mem/ruby/SConscript
M src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
M src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
M src/mem/ruby/protocol/RubySlicc_Types.sm
R src/mem/ruby/structures/RubyPrefetcher.cc
R src/mem/ruby/structures/RubyPrefetcher.hh
M src/mem/ruby/structures/RubyPrefetcher.py
M src/mem/ruby/structures/SConscript
M src/mem/slicc/symbols/StateMachine.py
9 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/src/mem/ruby/SConscript b/src/mem/ruby/SConscript
index 8c22ae4..fc90f8a 100644
--- a/src/mem/ruby/SConscript
+++ b/src/mem/ruby/SConscript
@@ -126,7 +126,7 @@
MakeInclude('structures/DirectoryMemory.hh')
MakeInclude('structures/PerfectCacheMemory.hh')
MakeInclude('structures/PersistentTable.hh')
-MakeInclude('structures/Prefetcher.hh')
+MakeInclude('structures/RubyPrefetcher.hh')
MakeInclude('structures/TBETable.hh')
MakeInclude('structures/TimerTable.hh')
MakeInclude('structures/WireBuffer.hh')
diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
index 3639ef2..4de4a29 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
@@ -46,7 +46,7 @@
Cycles response_latency := 2;
bool send_evictions;
- Prefetcher * prefetcher;
+ RubyPrefetcher * prefetcher;
bool enable_prefetch := "False";
// From this node's L0 cache to the network
diff --git a/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
index 7c83478..3e3580f 100644
--- a/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/ruby/protocol/MESI_Two_Level-L1cache.sm
@@ -30,7 +30,7 @@
: Sequencer * sequencer;
CacheMemory * L1Icache;
CacheMemory * L1Dcache;
- Prefetcher * prefetcher;
+ RubyPrefetcher * prefetcher;
int l2_select_num_bits;
Cycles l1_request_latency := 2;
Cycles l1_response_latency := 2;
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm
b/src/mem/ruby/protocol/RubySlicc_Types.sm
index 66d84fc..6ab0f3f 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -246,7 +246,7 @@
bool isSet(Addr);
}
-structure (Prefetcher, external = "yes") {
+structure (RubyPrefetcher, external = "yes") {
void observeMiss(Addr, RubyRequestType);
void observePfHit(Addr);
void observePfMiss(Addr);
diff --git a/src/mem/ruby/structures/Prefetcher.cc
b/src/mem/ruby/structures/RubyPrefetcher.cc
similarity index 99%
rename from src/mem/ruby/structures/Prefetcher.cc
rename to src/mem/ruby/structures/RubyPrefetcher.cc
index 0602115..8646b99 100644
--- a/src/mem/ruby/structures/Prefetcher.cc
+++ b/src/mem/ruby/structures/RubyPrefetcher.cc
@@ -38,7 +38,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "mem/ruby/structures/Prefetcher.hh"
+#include "mem/ruby/structures/RubyPrefetcher.hh"
#include "base/bitfield.hh"
#include "debug/RubyPrefetcher.hh"
@@ -46,7 +46,7 @@
#include "mem/ruby/system/RubySystem.hh"
RubyPrefetcher*
-PrefetcherParams::create()
+RubyPrefetcherParams::create()
{
return new RubyPrefetcher(this);
}
diff --git a/src/mem/ruby/structures/Prefetcher.hh
b/src/mem/ruby/structures/RubyPrefetcher.hh
similarity index 98%
rename from src/mem/ruby/structures/Prefetcher.hh
rename to src/mem/ruby/structures/RubyPrefetcher.hh
index 4d2513f..b691d3d 100644
--- a/src/mem/ruby/structures/Prefetcher.hh
+++ b/src/mem/ruby/structures/RubyPrefetcher.hh
@@ -51,7 +51,7 @@
#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "mem/ruby/slicc_interface/RubyRequest.hh"
#include "mem/ruby/system/RubySystem.hh"
-#include "params/Prefetcher.hh"
+#include "params/RubyPrefetcher.hh"
#include "sim/sim_object.hh"
#include "sim/system.hh"
@@ -93,7 +93,7 @@
class RubyPrefetcher : public SimObject
{
public:
-typedef PrefetcherParams Params;
+typedef RubyPrefetcherParams Params;
RubyPrefetcher(const Params *p);
~RubyPrefetcher();
diff --git a/src/mem/ruby/structures/RubyPrefetcher.py
b/src/mem/ruby/structures/RubyPrefetcher.py
index d762ba5..38397c3 100644
--- a/src/mem/ruby/structures/RubyPrefetcher.py
+++ b/src/mem/ruby/structures/RubyPrefetcher.py
@@ -42,10 +42,10 @@
from
[gem5-dev] Change in gem5/gem5[develop]: stats: refactor ScalarPrint and VectorPrint constructors
Ciro Santilli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28630 )
Change subject: stats: refactor ScalarPrint and VectorPrint constructors
..
stats: refactor ScalarPrint and VectorPrint constructors
This commit is only a refactoring to improve code quality after the need
was felt in the previous commits.
It creates constructors for those classes, and define the parameters that
don't change often across calls in the constructors.
Parameters that change often across calls such as value and name are now
passed to the operator() call directly.
Change-Id: Ibc12ed354e8e949d5a8b9ca23c6958c713f58800
---
M src/base/stats/text.cc
1 file changed, 148 insertions(+), 152 deletions(-)
diff --git a/src/base/stats/text.cc b/src/base/stats/text.cc
index aabcc0c..0ae7953 100644
--- a/src/base/stats/text.cc
+++ b/src/base/stats/text.cc
@@ -223,8 +223,6 @@
struct ScalarPrint
{
-Result value;
-string name;
string desc;
Flags flags;
bool descriptions;
@@ -238,7 +236,24 @@
int pdfstrSpaces;
int cdfstrSpaces;
-ScalarPrint(bool spaces) : spaces(spaces) {
+ScalarPrint(
+const string ,
+const Flags ,
+bool descriptions,
+bool spaces,
+bool names,
+int precision,
+const Result ,
+const Result
+) : desc(desc),
+flags(flags),
+descriptions(descriptions),
+spaces(spaces),
+names(names),
+precision(precision),
+pdf(pdf),
+cdf(cdf)
+{
if (spaces) {
nameSpaces = 40;
valueSpaces = 12;
@@ -251,24 +266,34 @@
cdfstrSpaces = 0;
}
}
-void update(Result val, Result total);
-void operator()(ostream , bool oneLine = false,
-bool firstBegin = false) const;
+void update(const Result , const Result );
+void operator()(
+ostream ,
+const string ,
+const Result ,
+bool oneLine = false,
+bool firstBegin = false) const;
};
void
-ScalarPrint::update(Result val, Result total)
-{
-value = val;
+ScalarPrint::update(
+const Result ,
+const Result
+) {
if (total) {
-pdf = val / total;
+pdf = value / total;
cdf += pdf;
}
}
void
-ScalarPrint::operator()(ostream , bool oneLine, bool firstBegin)
const
-{
+ScalarPrint::operator()(
+ostream ,
+const string ,
+const Result ,
+bool oneLine,
+bool firstBegin
+) const {
if (names && (
(flags.isSet(nozero) && (!oneLine) && value == 0.0) ||
(flags.isSet(nonan) && std::isnan(value))
@@ -306,7 +331,6 @@
struct VectorPrint
{
-string name;
string separatorString;
string desc;
vector subnames;
@@ -316,24 +340,50 @@
bool spaces;
bool names;
int precision;
-VResult vec;
-Result total;
bool forceSubnames;
int nameSpaces;
-VectorPrint() = delete;
-VectorPrint(bool spaces) : spaces(spaces) {
+VectorPrint(
+const string ,
+const string ,
+const Flags ,
+bool descriptions,
+bool spaces,
+bool names,
+int precision,
+bool forceSubnames
+) : separatorString(separatorString),
+desc(desc),
+flags(flags),
+descriptions(descriptions),
+spaces(spaces),
+names(names),
+precision(precision),
+forceSubnames(forceSubnames)
+{
if (spaces) {
nameSpaces = 40;
} else {
nameSpaces = 0;
}
}
-void operator()(ostream , bool firstBegin) const;
+void operator()(
+ostream ,
+const string ,
+const VResult ,
+const Result ,
+bool firstBegin
+) const;
};
void
-VectorPrint::operator()(std::ostream , bool firstBegin) const
+VectorPrint::operator()(
+ostream ,
+const string ,
+const VResult ,
+const Result ,
+bool firstBegin
+) const
{
size_type _size = vec.size();
Result _total = 0.0;
@@ -346,15 +396,16 @@
string base = name + separatorString;
-ScalarPrint print(spaces);
-print.name = name;
-print.names = names;
-print.desc = desc;
-print.precision = precision;
-print.descriptions = descriptions;
-print.flags = flags;
-print.pdf = _total ? 0.0 : NAN;
-print.cdf = _total ? 0.0 : NAN;
+ScalarPrint print(
+desc,
+flags,
+descriptions,
+spaces,
+names,
+precision,
+_total ? 0.0 : NAN,
+_total ? 0.0 : NAN
+);
bool havesub = !subnames.empty();
@@ -362,10 +413,14 @@
// If forceSubnames is set, get the first subname (or index in
// the case where there are no subnames) and append it to the
// base name.
-if (forceSubnames)
-print.name = base +
[gem5-dev] Change in gem5/gem5[develop]: stats: add --stats-root option to dump only under some SimObjects
Ciro Santilli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28628 )
Change subject: stats: add --stats-root option to dump only under some
SimObjects
..
stats: add --stats-root option to dump only under some SimObjects
This commit makes it possible to make invocations such as:
gem5.opt --stats-root 'system.cpu[:].dtb' --stats-root 'system.membus'
When --stats-root is given, only stats that are under any of the root
SimObjects get dumped. E.g. the above invocation would dump stats such as:
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED
system.membus.pwrStateResidencyTicks::UNDEFINED
system.membus.trans_dist::ReadReq
but not for example `system.clk_domain.clock`.
If the --stats-root is given, only new stats as defined at:
Idc8ff448b9f70a796427b4a5231e7371485130b4 get dumped, and old ones are
ignored. The commits following that one have done some initial conversion
work, but many stats are still in the old format.
Change-Id: Iadaef26edf9a678b39f774515600884fbaeec497
---
M src/python/m5/SimObject.py
M src/python/m5/main.py
M src/python/m5/simulate.py
M src/python/m5/stats/__init__.py
4 files changed, 52 insertions(+), 20 deletions(-)
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index a045fb7..561e4b8 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2017-2019 ARM Limited
+# Copyright (c) 2017-2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -1071,6 +1071,9 @@
out.extend(sim_object[i] for i in _range)
return SimObjectCliWrapper(out)
+def getSimObjects(self):
+return self._sim_objects
+
# The SimObject class is the root of the special hierarchy. Most of
# the code in this class deals with the configuration hierarchy itself
# (parent/child node relationships).
@@ -1695,6 +1698,10 @@
for param in params:
exec(param, d)
+def get_simobj(self, simobj_path):
+d = self._apply_config_get_dict()
+return eval(simobj_path, d).getSimObjects()
+
# Function to provide to C++ so it can look up instances based on paths
def resolveSimObject(name):
obj = instanceDict[name]
diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index 6fe9218..781f3a9 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016, 2019 Arm Limited
+# Copyright (c) 2016, 2019-2020 Arm Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -118,6 +118,14 @@
option("--stats-help",
action="callback", callback=_stats_help,
help="Display documentation for available stat visitors")
+option("--stats-root", action="append", default=[], help=
+"If given, dump only stats of objects under the given SimObject. "
+"SimObjects are identified with Python notation as in: "
+"system.cpu[0].dtb. All elements of an array can be selected at "
+"once with: system.cpu[:].dtb. If given multiple times, dump
stats "
+"that are present under any of the roots. If not given, dump all "
+"stats. "
+)
# Configuration Options
group("Configuration Options")
diff --git a/src/python/m5/simulate.py b/src/python/m5/simulate.py
index 3317ae8..629c054 100644
--- a/src/python/m5/simulate.py
+++ b/src/python/m5/simulate.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012,2019 ARM Limited
+# Copyright (c) 2012,2019-2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -52,6 +52,7 @@
from . import SimObject
from . import ticks
from . import objects
+import m5
from m5.util.dot_writer import do_dot, do_dvfs_dot
from m5.util.dot_writer_ruby import do_ruby_dot
@@ -139,6 +140,12 @@
# We're done registering statistics. Enable the stats package now.
stats.enable()
+# Setup global stat filtering.
+stat_root_simobjs = []
+for stat_root_str in m5.options.stats_root:
+stat_root_simobjs.extend(root.get_simobj(stat_root_str))
+m5.stats.global_dump_roots = stat_root_simobjs
+
# Restore checkpoint (if any)
if ckpt_dir:
_drain_manager.preCheckpointRestore()
diff --git a/src/python/m5/stats/__init__.py
b/src/python/m5/stats/__init__.py
index 1e37a14..6c4a42c 100644
--- a/src/python/m5/stats/__init__.py
+++ b/src/python/m5/stats/__init__.py
@@ -326,35 +326,45 @@
# New stats
_visit_stats(lambda g, s: s.prepare())
-def _dump_to_visitor(visitor, root=None):
-# Legacy stats
-if root is None:
-for stat in stats_list:
-stat.visit(visitor)
-
+def _dump_to_visitor(visitor, roots=None):
# New stats
def dump_group(group):
[gem5-dev] Change in gem5/gem5[develop]: stats: add option to remove names from all stats but first dump
Ciro Santilli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28629 )
Change subject: stats: add option to remove names from all stats but first
dump
..
stats: add option to remove names from all stats but first dump
With:
--stats-file stats.txt?names=False
names are only printed on the first dump of the run, e.g.:
-- Begin Simulation Statistics --
system.cpu0.Branches 21667
system.cpu0.committedInsts 105034
-- End Simulation Statistics --
-- Begin Simulation Statistics --
21673
105054
-- End Simulation Statistics --
-- Begin Simulation Statistics --
21683
105094
-- End Simulation Statistics --
For this to work, stats that were omitted due to the nozero and nonan must
always be printed however to have the same number of lines per dump, but I
have observed a 5x reduction in dump sizes in a simple se.py loop setup, so
it is still highly worth it in that setup.
The use case is for users that are already post-processing the dumps after
the run is over to datamine it, so they don't need the names every time
for visual inspection.
Change-Id: Ibe589997511536bdc9f510e78b5e99bd09fff0bc
---
M src/base/stats/hdf5.cc
M src/base/stats/hdf5.hh
M src/base/stats/output.hh
M src/base/stats/text.cc
M src/base/stats/text.hh
M src/python/m5/stats/__init__.py
6 files changed, 85 insertions(+), 51 deletions(-)
diff --git a/src/base/stats/hdf5.cc b/src/base/stats/hdf5.cc
index 963be6e..ca1ce22 100644
--- a/src/base/stats/hdf5.cc
+++ b/src/base/stats/hdf5.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019 Arm Limited
+ * Copyright (c) 2016-2020 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -83,7 +83,7 @@
}
void
-Hdf5::end()
+Hdf5::doEnd()
{
assert(valid());
diff --git a/src/base/stats/hdf5.hh b/src/base/stats/hdf5.hh
index 8944a55..89be2c9 100644
--- a/src/base/stats/hdf5.hh
+++ b/src/base/stats/hdf5.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019 Arm Limited
+ * Copyright (c) 2016-2020 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -63,7 +63,7 @@
public: // Output interface
void begin() override;
-void end() override;
+void doEnd() override;
bool valid() const override;
void beginGroup(const char *name) override;
diff --git a/src/base/stats/output.hh b/src/base/stats/output.hh
index 6ff4a5d..df70f27 100644
--- a/src/base/stats/output.hh
+++ b/src/base/stats/output.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited
+ * Copyright (c) 2019-2020 Arm Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -57,10 +57,19 @@
struct Output
{
+ protected:
+bool firstBegin;
+
+ public:
+Output() : firstBegin(true) {}
virtual ~Output() {}
virtual void begin() = 0;
-virtual void end() = 0;
+void end() {
+doEnd();
+firstBegin = false;
+}
+virtual void doEnd() = 0;
virtual bool valid() const = 0;
virtual void beginGroup(const char *name) = 0;
diff --git a/src/base/stats/text.cc b/src/base/stats/text.cc
index fa342a2..aabcc0c 100644
--- a/src/base/stats/text.cc
+++ b/src/base/stats/text.cc
@@ -95,7 +95,8 @@
std::list ();
Text::Text()
-: mystream(false), stream(NULL), descriptions(false), spaces(false)
+: mystream(false), stream(NULL), descriptions(false), spaces(false),
+ names(false)
{
}
@@ -155,7 +156,7 @@
}
void
-Text::end()
+Text::doEnd()
{
ccprintf(*stream, "\n-- End Simulation Statistics
--\n");
stream->flush();
@@ -228,6 +229,7 @@
Flags flags;
bool descriptions;
bool spaces;
+bool names;
int precision;
Result pdf;
Result cdf;
@@ -250,7 +252,8 @@
}
}
void update(Result val, Result total);
-void operator()(ostream , bool oneLine = false) const;
+void operator()(ostream , bool oneLine = false,
+bool firstBegin = false) const;
};
void
@@ -264,10 +267,12 @@
}
void
-ScalarPrint::operator()(ostream , bool oneLine) const
+ScalarPrint::operator()(ostream , bool oneLine, bool firstBegin)
const
{
-if ((flags.isSet(nozero) && (!oneLine) && value == 0.0) ||
-(flags.isSet(nonan) && std::isnan(value)))
+if (names && (
+(flags.isSet(nozero) && (!oneLine) && value == 0.0) ||
+(flags.isSet(nonan) && std::isnan(value))
+))
return;
stringstream pdfstr, cdfstr;
@@ -281,7 +286,9 @@
if (oneLine) {
ccprintf(stream, " |");
} else {
-ccprintf(stream, "%-*s ", nameSpaces, name);
+if (names || firstBegin) {
+ccprintf(stream, "%-*s ", nameSpaces, name);
+}
}
ccprintf(stream,
[gem5-dev] Change in gem5/gem5[develop]: stats: add option to disable alignment spaces in stats.txt file
Ciro Santilli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28627 )
Change subject: stats: add option to disable alignment spaces in stats.txt
file
..
stats: add option to disable alignment spaces in stats.txt file
The alignment spaces in stats.txt takes up a lot of space and increases
simulation time, this commit adds the option to disable them with:
--stats-file stats.txt?spaces=False
Sample old lines with ?desc=False:
system.cpu.op_class::FloatMultAcc 0 0.00% 65.92%
system.cpu.op_class::FloatDiv 0 0.00% 65.92%
Sample new lines with ?desc=False;spaces=False:
system.cpu.op_class::FloatMultAcc 0 0.00% 65.92%
system.cpu.op_class::FloatDiv 0 0.00% 65.92%
On a 1000 dumpstats m5op loop spaces=False reduces:
* size: from 38MB to 20MB
* time: from 4.5s to 3.5s
Change-Id: Ib738b996b5646c329094cf61aaa1d977e844e759
---
M src/base/stats/text.cc
M src/base/stats/text.hh
M src/python/m5/stats/__init__.py
3 files changed, 71 insertions(+), 28 deletions(-)
diff --git a/src/base/stats/text.cc b/src/base/stats/text.cc
index 96cbe34..fa342a2 100644
--- a/src/base/stats/text.cc
+++ b/src/base/stats/text.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 Arm Limited
+ * Copyright (c) 2019-2020 Arm Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -95,18 +95,16 @@
std::list ();
Text::Text()
-: mystream(false), stream(NULL), descriptions(false)
+: mystream(false), stream(NULL), descriptions(false), spaces(false)
{
}
-Text::Text(std::ostream )
-: mystream(false), stream(NULL), descriptions(false)
+Text::Text(std::ostream ) : Text()
{
open(stream);
}
-Text::Text(const std::string )
-: mystream(false), stream(NULL), descriptions(false)
+Text::Text(const std::string ) : Text()
{
open(file);
}
@@ -229,10 +227,28 @@
string desc;
Flags flags;
bool descriptions;
+bool spaces;
int precision;
Result pdf;
Result cdf;
+int nameSpaces;
+int valueSpaces;
+int pdfstrSpaces;
+int cdfstrSpaces;
+ScalarPrint(bool spaces) : spaces(spaces) {
+if (spaces) {
+nameSpaces = 40;
+valueSpaces = 12;
+pdfstrSpaces = 10;
+cdfstrSpaces = 10;
+} else {
+nameSpaces = 0;
+valueSpaces = 0;
+pdfstrSpaces = 0;
+cdfstrSpaces = 0;
+}
+}
void update(Result val, Result total);
void operator()(ostream , bool oneLine = false) const;
};
@@ -263,12 +279,16 @@
ccprintf(cdfstr, "%.2f%%", cdf * 100.0);
if (oneLine) {
-ccprintf(stream, " |%12s %10s %10s",
- ValueToString(value, precision), pdfstr.str(),
cdfstr.str());
+ccprintf(stream, " |");
} else {
-ccprintf(stream, "%-40s %12s %10s %10s", name,
- ValueToString(value, precision), pdfstr.str(),
cdfstr.str());
-
+ccprintf(stream, "%-*s ", nameSpaces, name);
+}
+ccprintf(stream, "%*s", valueSpaces, ValueToString(value, precision));
+if (spaces || pdfstr.rdbuf()->in_avail())
+ccprintf(stream, " %*s", pdfstrSpaces, pdfstr.str());
+if (spaces || cdfstr.rdbuf()->in_avail())
+ccprintf(stream, " %*s", cdfstrSpaces, cdfstr.str());
+if (!oneLine) {
if (descriptions) {
if (!desc.empty())
ccprintf(stream, " # %s", desc);
@@ -286,11 +306,21 @@
vector subdescs;
Flags flags;
bool descriptions;
+bool spaces;
int precision;
VResult vec;
Result total;
bool forceSubnames;
+int nameSpaces;
+VectorPrint() = delete;
+VectorPrint(bool spaces) : spaces(spaces) {
+if (spaces) {
+nameSpaces = 40;
+} else {
+nameSpaces = 0;
+}
+}
void operator()(ostream ) const;
};
@@ -308,7 +338,7 @@
string base = name + separatorString;
-ScalarPrint print;
+ScalarPrint print(spaces);
print.name = name;
print.desc = desc;
print.precision = precision;
@@ -332,7 +362,7 @@
if ((!flags.isSet(nozero)) || (total != 0)) {
if (flags.isSet(oneline)) {
-ccprintf(stream, "%-40s", name);
+ccprintf(stream, "%-*s", nameSpaces, name);
print.flags = print.flags & (~nozero);
}
@@ -373,7 +403,9 @@
string desc;
Flags flags;
bool descriptions;
+bool spaces;
int precision;
+int nameSpaces;
const DistData
@@ -389,8 +421,8 @@
init(text, info);
}
-DistPrint::DistPrint(const Text *text, const VectorDistInfo , int i)
-: data(info.data[i])
+DistPrint::DistPrint(const Text *text, const VectorDistInfo ,
+int i) : data(info.data[i])
{
init(text, info);
@@ -411,6 +443,12 @@
flags = info.flags;
[gem5-dev] Change in gem5/gem5[release-staging-v20.0.0.0]: python: Manually convert float to int when using %x
Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/28607 ) Change subject: python: Manually convert float to int when using %x .. python: Manually convert float to int when using %x This is required by python3.5 which is not allowing a floating point value to be printed in hex and will trigger a TypeError assertion: TypeError: %X format: an integer is required, not float Change-Id: I2033366751924579cc87e7fccda8fdb33a31412d Signed-off-by: Giacomo Travaglini --- M src/python/m5/util/dot_writer.py 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/python/m5/util/dot_writer.py b/src/python/m5/util/dot_writer.py index e6de3f3..c66108d 100644 --- a/src/python/m5/util/dot_writer.py +++ b/src/python/m5/util/dot_writer.py @@ -267,7 +267,7 @@ return dot_rgb_to_html(r, g, b) def dot_rgb_to_html(r, g, b): -return "#%.2x%.2x%.2x" % (r, g, b) +return "#%.2x%.2x%.2x" % (int(r), int(g), int(b)) # We need to create all of the clock domains. We abuse the alpha channel to get # the correct domain colouring. -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28607 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: release-staging-v20.0.0.0 Gerrit-Change-Id: I2033366751924579cc87e7fccda8fdb33a31412d Gerrit-Change-Number: 28607 Gerrit-PatchSet: 1 Gerrit-Owner: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim-se: ignore all scheduler related syscalls for arm
Ciro Santilli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28591 )
Change subject: sim-se: ignore all scheduler related syscalls for arm
..
sim-se: ignore all scheduler related syscalls for arm
With the simplistic syscall emulation fork algorithm that we currently have
of running one thread per call, those calls simply cannot be reasonably
implemented.
However, content can often still work without them.
Change-Id: Iac88dfd055564c47b7a7b6898b7582cf4087f708
---
M src/arch/arm/linux/process.cc
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc
index 55141ba..4c679b3 100644
--- a/src/arch/arm/linux/process.cc
+++ b/src/arch/arm/linux/process.cc
@@ -290,14 +290,14 @@
{ base + 151, "munlock" },
{ base + 152, "mlockall" },
{ base + 153, "munlockall" },
-{ base + 154, "sched_setparam" },
-{ base + 155, "sched_getparam" },
-{ base + 156, "sched_setscheduler" },
-{ base + 157, "sched_getscheduler" },
-{ base + 158, "sched_yield" },
-{ base + 159, "sched_get_priority_max" },
-{ base + 160, "sched_get_priority_min" },
-{ base + 161, "sched_rr_get_interval" },
+{ base + 154, "sched_setparam", ignoreWarnOnceFunc },
+{ base + 155, "sched_getparam", ignoreWarnOnceFunc },
+{ base + 156, "sched_setscheduler", ignoreWarnOnceFunc },
+{ base + 157, "sched_getscheduler", ignoreWarnOnceFunc },
+{ base + 158, "sched_yield", ignoreWarnOnceFunc },
+{ base + 159, "sched_get_priority_max", ignoreWarnOnceFunc },
+{ base + 160, "sched_get_priority_min", ignoreWarnOnceFunc },
+{ base + 161, "sched_rr_get_interval", ignoreWarnOnceFunc },
{ base + 162, "nanosleep", ignoreWarnOnceFunc },
{ base + 163, "mremap", mremapFunc }, // ARM-specific
{ base + 164, "setresuid" },
@@ -375,7 +375,7 @@
{ base + 238, "tkill" },
{ base + 239, "sendfile64" },
{ base + 240, "futex", futexFunc },
-{ base + 241, "sched_setaffinity" },
+{ base + 241, "sched_setaffinity", ignoreWarnOnceFunc },
{ base + 242, "sched_getaffinity", ignoreFunc },
{ base + 243, "io_setup" },
{ base + 244, "io_destroy" },
@@ -631,16 +631,16 @@
{ base + 115, "clock_nanosleep" },
{ base + 116, "syslog" },
{ base + 117, "ptrace" },
-{ base + 118, "sched_setparam" },
-{ base + 119, "sched_setscheduler" },
-{ base + 120, "sched_getscheduler" },
-{ base + 121, "sched_getparam" },
-{ base + 122, "sched_setaffinity" },
+{ base + 118, "sched_setparam", ignoreWarnOnceFunc },
+{ base + 119, "sched_setscheduler", ignoreWarnOnceFunc },
+{ base + 120, "sched_getscheduler", ignoreWarnOnceFunc },
+{ base + 121, "sched_getparam", ignoreWarnOnceFunc },
+{ base + 122, "sched_setaffinity", ignoreWarnOnceFunc },
{ base + 123, "sched_getaffinity", ignoreFunc },
-{ base + 124, "sched_yield" },
-{ base + 125, "sched_get_priority_max" },
-{ base + 126, "sched_get_priority_min" },
-{ base + 127, "sched_rr_get_interval" },
+{ base + 124, "sched_yield", ignoreWarnOnceFunc },
+{ base + 125, "sched_get_priority_max", ignoreWarnOnceFunc },
+{ base + 126, "sched_get_priority_min", ignoreWarnOnceFunc },
+{ base + 127, "sched_rr_get_interval", ignoreWarnOnceFunc },
{ base + 128, "restart_syscall" },
{ base + 129, "kill", ignoreFunc },
{ base + 130, "tkill" },
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iac88dfd055564c47b7a7b6898b7582cf4087f708
Gerrit-Change-Number: 28591
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim-se: implement the getcpu syscall
Ciro Santilli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28590 )
Change subject: sim-se: implement the getcpu syscall
..
sim-se: implement the getcpu syscall
Change-Id: I63a1384646829b8cf68453c42aed6a7d12172787
---
M src/arch/arm/linux/process.cc
M src/arch/x86/linux/process.cc
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
4 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc
index b5b6553..55141ba 100644
--- a/src/arch/arm/linux/process.cc
+++ b/src/arch/arm/linux/process.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2013, 2015 ARM Limited
+ * Copyright (c) 2010-2013, 2015, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -476,7 +476,7 @@
{ base + 342, "tee" },
{ base + 343, "vmsplice" },
{ base + 344, "move_pages" },
-{ base + 345, "getcpu" },
+{ base + 345, "getcpu", getcpuFunc },
{ base + 346, "epoll_pwait" },
{ base + 347, "sys_kexec_load" },
{ base + 348, "sys_utimensat" },
@@ -681,7 +681,7 @@
{ base + 165, "getrusage", getrusageFunc },
{ base + 166, "umask" },
{ base + 167, "prctl" },
-{ base + 168, "getcpu" },
+{ base + 168, "getcpu", getcpuFunc },
{ base + 169, "gettimeofday", gettimeofdayFunc },
{ base + 170, "settimeofday" },
{ base + 171, "adjtimex" },
diff --git a/src/arch/x86/linux/process.cc b/src/arch/x86/linux/process.cc
index 6b50dbf..2c594e7 100644
--- a/src/arch/x86/linux/process.cc
+++ b/src/arch/x86/linux/process.cc
@@ -566,7 +566,7 @@
{ 306, "syncfs" },
{ 307, "sendmmsg" },
{ 308, "setns" },
-{ 309, "getcpu" },
+{ 309, "getcpu", getcpuFunc },
{ 310, "proess_vm_readv" },
{ 311, "proess_vm_writev" },
{ 312, "kcmp" },
@@ -914,7 +914,7 @@
{ 315, "tee" },
{ 316, "vmsplice" },
{ 317, "move_pages" },
-{ 318, "getcpu" },
+{ 318, "getcpu", getcpuFunc },
{ 319, "epoll_pwait" },
{ 320, "utimensat" },
{ 321, "signalfd" },
diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc
index bffedfd..918a7bd 100644
--- a/src/sim/syscall_emul.cc
+++ b/src/sim/syscall_emul.cc
@@ -1633,3 +1633,15 @@
return (status == -1) ? -errno : status;
}
+SyscallReturn
+getcpuFunc(SyscallDesc *desc, ThreadContext *tc,
+ Addr cpu_ptr, Addr node_ptr, Addr tcache_ptr)
+{
+// unsigned is the same size (4) on all Linux supported ISAs.
+uint32_t result = htog(tc->contextId(),
+tc->getSystemPtr()->getGuestByteOrder());
+BufferArg result_buf(cpu_ptr, sizeof(result));
+memcpy(result_buf.bufferPtr(), , sizeof(result));
+result_buf.copyOut(tc->getVirtProxy());
+return 0;
+}
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 5bd9f54..bb3b418 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013, 2015, 2019 ARM Limited
+ * Copyright (c) 2012-2013, 2015, 2019-2020 ARM Limited
* Copyright (c) 2015 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -354,6 +354,9 @@
int tgt_fd, int level, int optname,
Addr valPtr, socklen_t len);
+SyscallReturn getcpuFunc(SyscallDesc *desc, ThreadContext *tc,
+Addr cpu_ptr, Addr node_ptr, Addr tcache_ptr);
+
// Target getsockname() handler.
SyscallReturn getsocknameFunc(SyscallDesc *desc, ThreadContext *tc,
int tgt_fd, Addr addrPtr, Addr lenPtr);
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I63a1384646829b8cf68453c42aed6a7d12172787
Gerrit-Change-Number: 28590
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: show names on --debug-flags MiscRegs write:
Ciro Santilli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/28467 )
Change subject: arch-arm: show names on --debug-flags MiscRegs write:
..
arch-arm: show names on --debug-flags MiscRegs write:
Before this commit it would show only numbers:
Writing to misc reg 19 (19) : 0x74178
and now it also shows the name:
Writing MiscReg lockaddr (19 19) : 0x74178
MiscReg reads were already showing names and are unchanged, e.g.:
Reading MiscReg sctlr_el1 with clear res1 bits: 0x18100800
Change-Id: If46da88359ce4a549a6a50080a2b13077d41e373
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28467
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/isa.cc
1 file changed, 4 insertions(+), 4 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b3d6726..b18bbb0 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -787,12 +787,12 @@
if (upper > 0) {
miscRegs[lower] = bits(v, 31, 0);
miscRegs[upper] = bits(v, 63, 32);
-DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
-misc_reg, lower, upper, v);
+DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d:%d) : %#x\n",
+miscRegName[misc_reg], misc_reg, lower, upper, v);
} else {
miscRegs[lower] = v;
-DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
-misc_reg, lower, v);
+DPRINTF(MiscRegs, "Writing MiscReg %s (%d %d) : %#x\n",
+miscRegName[misc_reg], misc_reg, lower, v);
}
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If46da88359ce4a549a6a50080a2b13077d41e373
Gerrit-Change-Number: 28467
Gerrit-PatchSet: 2
Gerrit-Owner: Ciro Santilli
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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