[gem5-dev] Change in gem5/gem5[develop]: cpu: differentiate snoop DPRINTF messages for AtomicSimpleCPU
Ciro Santilli has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30694 )
Change subject: cpu: differentiate snoop DPRINTF messages for
AtomicSimpleCPU
..
cpu: differentiate snoop DPRINTF messages for AtomicSimpleCPU
Those three snoop messages were the same, which made interpreting logs
harder.
Change-Id: Ibff092932bc6d2ef0c5f15bf5f7ce031d1f1956b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30694
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/cpu/simple/atomic.cc
1 file changed, 6 insertions(+), 6 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index c57fe14..d7a914a 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -125,8 +125,8 @@
void
AtomicSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender)
{
-DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n",
pkt->getAddr(),
-pkt->cmdString());
+DPRINTF(SimpleCPU, "%s received snoop pkt for addr:%#x %s\n",
+__func__, pkt->getAddr(), pkt->cmdString());
for (ThreadID tid = 0; tid < numThreads; tid++) {
if (tid != sender) {
@@ -280,8 +280,8 @@
Tick
AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt)
{
-DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n",
pkt->getAddr(),
-pkt->cmdString());
+DPRINTF(SimpleCPU, "%s received atomic snoop pkt for addr:%#x %s\n",
+__func__, pkt->getAddr(), pkt->cmdString());
// X86 ISA: Snooping an invalidation for monitor/mwait
AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner);
@@ -310,8 +310,8 @@
void
AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt)
{
-DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n",
pkt->getAddr(),
-pkt->cmdString());
+DPRINTF(SimpleCPU, "%s received functional snoop pkt for
addr:%#x %s\n",
+__func__, pkt->getAddr(), pkt->cmdString());
// X86 ISA: Snooping an invalidation for monitor/mwait
AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibff092932bc6d2ef0c5f15bf5f7ce031d1f1956b
Gerrit-Change-Number: 30694
Gerrit-PatchSet: 2
Gerrit-Owner: Ciro Santilli
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Ciro Santilli
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add System register trap check for EL1
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31694 )
Change subject: arch-arm: Add System register trap check for EL1
..
arch-arm: Add System register trap check for EL1
This change adds and refactors the register trap checks
for EL1 in the same function, unifying the registry trapping
Change-Id: Ief3e0a9f70cc8cd44c1c8215515f36168927362d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31694
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/insts/misc64.cc
M src/arch/arm/isa/insts/data64.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs_types.hh
4 files changed, 36 insertions(+), 25 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 51e6028..49cc6b0 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -114,9 +114,26 @@
uint32_t &immediate) const
{
const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
+const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
+const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
bool trap_to_sup = false;
switch (misc_reg) {
+ case MISCREG_DAIF:
+trap_to_sup = !scr.ns && !scr.eel2 && !sctlr.uma && el == EL0;
+trap_to_sup = trap_to_sup ||
+(el == EL0 && (scr.ns || scr.eel2) && !hcr.tge && !sctlr.uma);
+break;
+ case MISCREG_DC_ZVA_Xt:
+// In syscall-emulation mode, this test is skipped and DCZVA is
always
+// allowed at EL0
+trap_to_sup = el == EL0 && !sctlr.dze && FullSystem;
+break;
+ case MISCREG_DC_CIVAC_Xt:
+ case MISCREG_DC_CVAC_Xt:
+trap_to_sup = el == EL0 && !sctlr.uci;
+break;
case MISCREG_FPCR:
case MISCREG_FPSR:
case MISCREG_FPEXC32_EL2:
@@ -127,6 +144,24 @@
immediate = 0x1E0;
}
break;
+ case MISCREG_DC_CVAU_Xt:
+trap_to_sup = !sctlr.uci && (!hcr.tge || (!scr.ns && !scr.eel2)) &&
+el == EL1;
+break;
+ case MISCREG_CTR_EL0:
+trap_to_sup = el == EL0 && !sctlr.uct &&
+(!hcr.tge || (!scr.ns && !scr.eel2));
+break;
+ case MISCREG_MDCCSR_EL0:
+ {
+ DBGDS32 mdscr = tc->readMiscReg(MISCREG_MDSCR_EL1);
+ trap_to_sup = el == EL0 && mdscr.tdcc &&
+ (hcr.tge == 0x0 || ( scr.ns == 0x0));
+ }
+ break;
+ case MISCREG_ZCR_EL1:
+trap_to_sup = el == EL1 && ((cpacr.zen & 0x1) == 0x0);
+break;
// Generic Timer
case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
trap_to_sup = el == EL0 &&
diff --git a/src/arch/arm/isa/insts/data64.isa
b/src/arch/arm/isa/insts/data64.isa
index 3c1e941..1b099bf 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -312,14 +312,6 @@
msrMrs64EnabledCheckCode = '''
// Check for read/write access right
if (!can%sAArch64SysReg(flat_idx, Hcr64, Scr64, cpsr,
xc->tcBase())) {
-if (flat_idx == MISCREG_DAIF ||
-flat_idx == MISCREG_DC_ZVA_Xt ||
-flat_idx == MISCREG_DC_CVAC_Xt ||
-flat_idx == MISCREG_DC_CIVAC_Xt
-)
-return std::make_shared(
-machInst, 0, EC_TRAPPED_MSR_MRS_64,
-mnemonic);
return std::make_shared(machInst, false,
mnemonic);
}
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index cc451c6..525fbcd 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -1415,23 +1415,6 @@
if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
return false;
ExceptionLevel el = currEL(cpsr);
-if (reg == MISCREG_DAIF) {
-SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
-if (el == EL0 && !sctlr.uma)
-return false;
-}
-if (FullSystem && reg == MISCREG_DC_ZVA_Xt) {
-// In syscall-emulation mode, this test is skipped and DCZVA is
always
-// allowed at EL0
-SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
-if (el == EL0 && !sctlr.dze)
-return false;
-}
-if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
-SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
-if (el == EL0 && !sctlr.uci)
-return false;
-}
bool secure = ArmSystem::haveSecurity(tc) && !scr.ns;
bool el2_host = EL2Enabled(tc) && hcr.e2h;
diff --git a/src/arch/arm/miscregs_types.hh
[gem5-dev] Change in gem5/gem5[develop]: util,tests: Enable passing of build args to compiler-tests.sh
Bobby R. Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31734 )
Change subject: util,tests: Enable passing of build args to
compiler-tests.sh
..
util,tests: Enable passing of build args to compiler-tests.sh
Previously we passed "-j `nproc`" to the scons. This a greedy approach
that should not be default. This change was introduced so the "-j" flag
may be passed via the "util/compiler-tests.sh" script.
Change-Id: I2e891ae3a9819770bd3ef15b95b81b7f5b71f7fa
---
M util/compiler-tests.sh
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/util/compiler-tests.sh b/util/compiler-tests.sh
index c586c27..c8fce4b 100755
--- a/util/compiler-tests.sh
+++ b/util/compiler-tests.sh
@@ -8,7 +8,6 @@
dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )"
gem5_root="${dir}/.."
build_dir="${gem5_root}/build"
-num_cores=`nproc`
# All Docker images in the gem5 testing GCR which we want to compile with.
images=("gcc-version-10"
@@ -61,7 +60,7 @@
base_url="gcr.io/gem5-test"
# Arguments passed into scons on every build target test.
-build_args="-j ${num_cores}"
+build_args="$@"
# Testing directory variables
mkdir -p "${build_dir}" # Create the build directory if it doesn't exist.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2e891ae3a9819770bd3ef15b95b81b7f5b71f7fa
Gerrit-Change-Number: 31734
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Gicv3 maintenance interrupt never cleared
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31614 )
Change subject: dev-arm: Gicv3 maintenance interrupt never cleared
..
dev-arm: Gicv3 maintenance interrupt never cleared
The maintenance interrupt is a level sensitive interrupt though it has
been treated as edge triggered so far.
In order to be level sensitive, it needs to be cleared once the condition
which led to its generation are not valid anymore.
Change-Id: I9af9f4bf27622a7961393b00a145d6c9835d738b
Signed-off-by: Giacomo Travaglini
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31614
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/dev/arm/gic_v3_cpu_interface.cc
1 file changed, 9 insertions(+), 4 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc
b/src/dev/arm/gic_v3_cpu_interface.cc
index 5e1f871..5499e38 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -79,6 +79,8 @@
Gicv3CPUInterface::setThreadContext(ThreadContext *tc)
{
maintenanceInterrupt = gic->params()->maint_int->get(tc);
+fatal_if(maintenanceInterrupt->num() >=
redistributor->irqPending.size(),
+"Invalid maintenance interrupt number\n");
}
bool
@@ -2078,10 +2080,13 @@
ICH_HCR_EL2 ich_hcr_el2 =
isa->readMiscRegNoEffect(MISCREG_ICH_HCR_EL2);
-if (ich_hcr_el2.En) {
-if (maintenanceInterruptStatus()) {
-maintenanceInterrupt->raise();
-}
+const bool maint_pending = redistributor->irqPending[
+maintenanceInterrupt->num()];
+
+if (ich_hcr_el2.En && !maint_pending && maintenanceInterruptStatus()) {
+maintenanceInterrupt->raise();
+} else if (maint_pending) {
+maintenanceInterrupt->clear();
}
if (signal_IRQ) {
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9af9f4bf27622a7961393b00a145d6c9835d738b
Gerrit-Change-Number: 31614
Gerrit-PatchSet: 5
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Nikos Nikoleris
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Implement LevelSensitive SPIs in GICv3
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31515 )
Change subject: dev-arm: Implement LevelSensitive SPIs in GICv3
..
dev-arm: Implement LevelSensitive SPIs in GICv3
Change-Id: If918a8aea934f0037818cc64bf458076bfd0251d
Signed-off-by: Giacomo Travaglini
Reviewed-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31515
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/dev/arm/gic_v3.cc
M src/dev/arm/gic_v3_distributor.cc
M src/dev/arm/gic_v3_distributor.hh
3 files changed, 48 insertions(+), 7 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc
index 5751940..8e75b1c 100644
--- a/src/dev/arm/gic_v3.cc
+++ b/src/dev/arm/gic_v3.cc
@@ -177,9 +177,10 @@
}
void
-Gicv3::clearInt(uint32_t number)
+Gicv3::clearInt(uint32_t int_id)
{
-distributor->deassertSPI(number);
+DPRINTF(Interrupt, "Gicv3::clearInt(): received SPI %d\n", int_id);
+distributor->clearInt(int_id);
}
void
diff --git a/src/dev/arm/gic_v3_distributor.cc
b/src/dev/arm/gic_v3_distributor.cc
index f8605da..27f404b 100644
--- a/src/dev/arm/gic_v3_distributor.cc
+++ b/src/dev/arm/gic_v3_distributor.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 ARM Limited
+ * Copyright (c) 2019-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -74,6 +74,7 @@
irqGroup(it_lines, 0),
irqEnabled(it_lines, false),
irqPending(it_lines, false),
+ irqPendingIspendr(it_lines, false),
irqActive(it_lines, false),
irqPriority(it_lines, 0xAA),
irqConfig(it_lines, Gicv3::INT_LEVEL_SENSITIVE),
@@ -608,6 +609,7 @@
DPRINTF(GIC, "Gicv3Distributor::write() (GICD_ISPENDR): "
"int_id %d (SPI) pending bit set\n", int_id);
irqPending[int_id] = true;
+irqPendingIspendr[int_id] = true;
}
}
@@ -634,7 +636,7 @@
bool clear = data & (1 << i) ? 1 : 0;
-if (clear) {
+if (clear && treatAsEdgeTriggered(int_id)) {
irqPending[int_id] = false;
clearIrqCpuInterface(int_id);
}
@@ -1000,12 +1002,23 @@
panic_if(int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX, "Invalid SPI!");
panic_if(int_id > itLines, "Invalid SPI!");
irqPending[int_id] = true;
+irqPendingIspendr[int_id] = false;
DPRINTF(GIC, "Gicv3Distributor::sendInt(): "
"int_id %d (SPI) pending bit set\n", int_id);
update();
}
void
+Gicv3Distributor::clearInt(uint32_t int_id)
+{
+// Edge-triggered interrupts remain pending until software
+// writes GICD_ICPENDR, GICD_CLRSPI_* or activates them via ICC_IAR
+if (isLevelSensitive(int_id)) {
+deassertSPI(int_id);
+}
+}
+
+void
Gicv3Distributor::deassertSPI(uint32_t int_id)
{
panic_if(int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX, "Invalid SPI!");
@@ -1145,7 +1158,9 @@
void
Gicv3Distributor::activateIRQ(uint32_t int_id)
{
-irqPending[int_id] = false;
+if (treatAsEdgeTriggered(int_id)) {
+irqPending[int_id] = false;
+}
irqActive[int_id] = true;
}
@@ -1166,6 +1181,7 @@
SERIALIZE_CONTAINER(irqGroup);
SERIALIZE_CONTAINER(irqEnabled);
SERIALIZE_CONTAINER(irqPending);
+SERIALIZE_CONTAINER(irqPendingIspendr);
SERIALIZE_CONTAINER(irqActive);
SERIALIZE_CONTAINER(irqPriority);
SERIALIZE_CONTAINER(irqConfig);
@@ -1185,6 +1201,7 @@
UNSERIALIZE_CONTAINER(irqGroup);
UNSERIALIZE_CONTAINER(irqEnabled);
UNSERIALIZE_CONTAINER(irqPending);
+UNSERIALIZE_CONTAINER(irqPendingIspendr);
UNSERIALIZE_CONTAINER(irqActive);
UNSERIALIZE_CONTAINER(irqPriority);
UNSERIALIZE_CONTAINER(irqConfig);
diff --git a/src/dev/arm/gic_v3_distributor.hh
b/src/dev/arm/gic_v3_distributor.hh
index 62bed18..99b65ed 100644
--- a/src/dev/arm/gic_v3_distributor.hh
+++ b/src/dev/arm/gic_v3_distributor.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 ARM Limited
+ * Copyright (c) 2019-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -151,6 +151,7 @@
std::vector irqGroup;
std::vector irqEnabled;
std::vector irqPending;
+std::vector irqPendingIspendr;
std::vector irqActive;
std::vector irqPriority;
std::vector irqConfig;
@@ -222,6 +223,27 @@
}
}
+bool isLevelSensitive(uint32_t int_id) const
+{
+return irqConfig[int_id] == Gicv3::INT_LEVEL_SENSITIVE;
+}
+
+/**
+ * This helper is used to check if an interrupt should be treated as
+ * edge triggered in the following scenarios:
+ *
+ *
[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Implement LevelSensitive PPIs in GICv3
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31516 )
Change subject: dev-arm: Implement LevelSensitive PPIs in GICv3
..
dev-arm: Implement LevelSensitive PPIs in GICv3
Change-Id: I7f28408eff7d502427c4486518c83506893f4a7a
Signed-off-by: Giacomo Travaglini
Reviewed-by: Nikos Nikoleris
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31516
Reviewed-by: Andreas Sandberg
Maintainer: Andreas Sandberg
Tested-by: kokoro
---
M src/dev/arm/gic_v3.cc
M src/dev/arm/gic_v3_redistributor.cc
M src/dev/arm/gic_v3_redistributor.hh
3 files changed, 53 insertions(+), 5 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc
index 8e75b1c..83f2c83 100644
--- a/src/dev/arm/gic_v3.cc
+++ b/src/dev/arm/gic_v3.cc
@@ -193,8 +193,12 @@
}
void
-Gicv3::clearPPInt(uint32_t num, uint32_t cpu)
+Gicv3::clearPPInt(uint32_t int_id, uint32_t cpu)
{
+panic_if(cpu >= redistributors.size(), "Invalid cpuID clearing PPI!");
+DPRINTF(Interrupt, "Gicv3::clearPPInt(): received PPI %d
cpuTarget %#x\n",
+int_id, cpu);
+redistributors[cpu]->clearPPInt(int_id);
}
void
diff --git a/src/dev/arm/gic_v3_redistributor.cc
b/src/dev/arm/gic_v3_redistributor.cc
index 5fceed5..3390393 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 ARM Limited
+ * Copyright (c) 2019-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -58,6 +58,7 @@
irqGroup(Gicv3::SGI_MAX + Gicv3::PPI_MAX, 0),
irqEnabled(Gicv3::SGI_MAX + Gicv3::PPI_MAX, false),
irqPending(Gicv3::SGI_MAX + Gicv3::PPI_MAX, false),
+ irqPendingIspendr(Gicv3::SGI_MAX + Gicv3::PPI_MAX, false),
irqActive(Gicv3::SGI_MAX + Gicv3::PPI_MAX, false),
irqPriority(Gicv3::SGI_MAX + Gicv3::PPI_MAX, 0),
irqConfig(Gicv3::SGI_MAX + Gicv3::PPI_MAX,
Gicv3::INT_EDGE_TRIGGERED),
@@ -509,6 +510,7 @@
"(GICR_ISPENDR0): int_id %d (PPI) "
"pending bit set\n", int_id);
irqPending[int_id] = true;
+irqPendingIspendr[int_id] = true;
}
}
@@ -526,7 +528,7 @@
bool clear = data & (1 << int_id) ? 1 : 0;
-if (clear) {
+if (clear && treatAsEdgeTriggered(int_id)) {
irqPending[int_id] = false;
}
}
@@ -710,12 +712,24 @@
assert((int_id >= Gicv3::SGI_MAX) &&
(int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX));
irqPending[int_id] = true;
+irqPendingIspendr[int_id] = false;
DPRINTF(GIC, "Gicv3Redistributor::sendPPInt(): "
"int_id %d (PPI) pending bit set\n", int_id);
updateDistributor();
}
void
+Gicv3Redistributor::clearPPInt(uint32_t int_id)
+{
+assert((int_id >= Gicv3::SGI_MAX) &&
+ (int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX));
+
+if (isLevelSensitive(int_id)) {
+irqPending[int_id] = false;
+}
+}
+
+void
Gicv3Redistributor::sendSGI(uint32_t int_id, Gicv3::GroupId group, bool ns)
{
assert(int_id < Gicv3::SGI_MAX);
@@ -747,6 +761,7 @@
if (!forward) return;
irqPending[int_id] = true;
+irqPendingIspendr[int_id] = false;
DPRINTF(GIC, "Gicv3ReDistributor::sendSGI(): "
"int_id %d (SGI) pending bit set\n", int_id);
updateDistributor();
@@ -977,7 +992,9 @@
void
Gicv3Redistributor::activateIRQ(uint32_t int_id)
{
-irqPending[int_id] = false;
+if (treatAsEdgeTriggered(int_id)) {
+irqPending[int_id] = false;
+}
irqActive[int_id] = true;
}
@@ -1037,6 +1054,7 @@
SERIALIZE_CONTAINER(irqGroup);
SERIALIZE_CONTAINER(irqEnabled);
SERIALIZE_CONTAINER(irqPending);
+SERIALIZE_CONTAINER(irqPendingIspendr);
SERIALIZE_CONTAINER(irqActive);
SERIALIZE_CONTAINER(irqPriority);
SERIALIZE_CONTAINER(irqConfig);
@@ -1058,6 +1076,7 @@
UNSERIALIZE_CONTAINER(irqGroup);
UNSERIALIZE_CONTAINER(irqEnabled);
UNSERIALIZE_CONTAINER(irqPending);
+UNSERIALIZE_CONTAINER(irqPendingIspendr);
UNSERIALIZE_CONTAINER(irqActive);
UNSERIALIZE_CONTAINER(irqPriority);
UNSERIALIZE_CONTAINER(irqConfig);
diff --git a/src/dev/arm/gic_v3_redistributor.hh
b/src/dev/arm/gic_v3_redistributor.hh
index ee92bc7..7def1a2 100644
--- a/src/dev/arm/gic_v3_redistributor.hh
+++ b/src/dev/arm/gic_v3_redistributor.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019 ARM Limited
+ * Copyright (c) 2019-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -153,6 +153,7 @@
std::vector irqGroup;
std::vector irqEnabled;
std::vector irqPending;
[gem5-dev] Change in gem5/gem5[develop]: util: Move the m5 utility ABIs into a subdir.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27552 )
Change subject: util: Move the m5 utility ABIs into a subdir.
..
util: Move the m5 utility ABIs into a subdir.
Change-Id: Ia268fad950c8e7ad9ccfe69af72b57d33f6787b9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27552
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M util/m5/SConstruct
M util/m5/src/SConscript
R util/m5/src/abi/aarch64/SConsopts
R util/m5/src/abi/aarch64/m5op.S
R util/m5/src/abi/aarch64/m5op_addr.S
R util/m5/src/abi/aarch64/m5op_semi.S
R util/m5/src/abi/arm/SConsopts
R util/m5/src/abi/arm/m5op.S
R util/m5/src/abi/sparc/SConsopts
R util/m5/src/abi/sparc/m5op.S
R util/m5/src/abi/thumb/SConsopts
R util/m5/src/abi/thumb/m5op.S
R util/m5/src/abi/x86/SConsopts
R util/m5/src/abi/x86/m5op.S
R util/m5/src/abi/x86/m5op_addr.S
15 files changed, 23 insertions(+), 23 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/util/m5/SConstruct b/util/m5/SConstruct
index 8ff6aea..e539d8d 100644
--- a/util/m5/SConstruct
+++ b/util/m5/SConstruct
@@ -84,31 +84,31 @@
}
for root, dirs, files in os.walk(abspath(src_dir)):
-# Each SConsopts file describes a variant of the m5 utility.
+# Each SConsopts file describes an ABI of the m5 utility.
if 'SConsopts' in files:
env = main.Clone()
env['CALL_TYPE'] = copy.deepcopy(call_types)
-# The user may override variant settings by setting environment
-# variables of the form ${VARIANT}.${OPTION}. For instance, to set
the
-# CROSS_COMPILE prefix for variant foo to bar-, the user would set
an
+# The user may override ABI settings by setting environment
+# variables of the form ${ABI}.${OPTION}. For instance, to set the
+# CROSS_COMPILE prefix for abi foo to bar-, the user would set an
# environment variable foo.CROSS_COMPILE=bar-.
#
# This also considers scons command line settings which may look
like
# environment variables, but are set after "scons" on the command
line.
-def get_variant_opt(name, default):
-var_name = env.subst('${VARIANT}.%s' % name)
+def get_abi_opt(name, default):
+var_name = env.subst('${ABI}.%s' % name)
env[name] = os.environ.get(
var_name, ARGUMENTS.get(var_name, default))
-# Process the variant's settings in the SConsopts file, storing
them
+# Process the ABI's settings in the SConsopts file, storing them
# in a copy of the primary environment.
env.SConscript(Dir(root).File('SConsopts'),
- exports=[ 'env', 'get_variant_opt' ])
+ exports=[ 'env', 'get_abi_opt' ])
# Once all the options have been configured, set up build targets
for
-# this variant.
-variant_dir = build_dir.Dir(env.subst('${VARIANT}'))
+# this abi.
+abi_dir = build_dir.Dir(env.subst('${ABI}'))
env.SConscript(src_dir.File('SConscript'),
- variant_dir=variant_dir, exports='env')
+ variant_dir=abi_dir, exports='env')
diff --git a/util/m5/src/SConscript b/util/m5/src/SConscript
index ee725fd..0082ebc 100644
--- a/util/m5/src/SConscript
+++ b/util/m5/src/SConscript
@@ -42,12 +42,12 @@
all_call_types = list(env['CALL_TYPE'].values())
call_types = list([ ct for ct in all_call_types if ct.enabled ])
-m5ops = list([ '${VARIANT}/%s' % ct.impl_file for ct in call_types ])
+m5ops = list([ 'abi/${ABI}/%s' % ct.impl_file for ct in call_types ])
default_call_type = list([ ct for ct in call_types if ct.default ])
assert len(default_call_type) == 1, \
'There should be exactly one default call type for %s, found %d' %
\
-(env['VARIANT'], len(default_call_type))
+(env['ABI'], len(default_call_type))
default_call_type = default_call_type[0]
static_env = env.Clone()
diff --git a/util/m5/src/aarch64/SConsopts
b/util/m5/src/abi/aarch64/SConsopts
similarity index 95%
rename from util/m5/src/aarch64/SConsopts
rename to util/m5/src/abi/aarch64/SConsopts
index 6032aea..938a866 100644
--- a/util/m5/src/aarch64/SConsopts
+++ b/util/m5/src/abi/aarch64/SConsopts
@@ -25,8 +25,8 @@
Import('*')
-env['VARIANT'] = 'aarch64'
-get_variant_opt('CROSS_COMPILE', 'aarch64-linux-gnu-')
+env['ABI'] = 'aarch64'
+get_abi_opt('CROSS_COMPILE', 'aarch64-linux-gnu-')
env['CALL_TYPE']['inst'].impl('m5op.S', default=True)
env['CALL_TYPE']['addr'].impl('m5op_addr.S')
diff --git a/util/m5/src/aarch64/m5op.S b/util/m5/src/abi/aarch64/m5op.S
similarity index 100%
rename from util/m5/src/aarch64/m5op.S
rename to util/m5/src/abi/aarch64/m5op.S
diff --git a/util/m5/src/aarch64/m5op_addr.S
b/util/m5/sr
[gem5-dev] Change in gem5/gem5[develop]: util: Further consolidate the Args interface in the m5 utility.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27553 )
Change subject: util: Further consolidate the Args interface in the m5
utility.
..
util: Further consolidate the Args interface in the m5 utility.
Create static methods to convert any string to an integer or to pack it
into an array of integers. Create non-static methdos named pop() to
pop() the first element and simultaneously convert it. If the conversion
fails, the argument is not popped.
Change-Id: I55d98b3971e7abb7b6206d06ec7fcf046e828d29
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27553
Reviewed-by: Jason Lowe-Power
Reviewed-by: Daniel Carvalho
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M util/m5/src/args.cc
M util/m5/src/args.hh
M util/m5/src/call_type/addr.cc
M util/m5/src/commands.cc
4 files changed, 150 insertions(+), 53 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
kokoro: Regressions pass
diff --git a/util/m5/src/args.cc b/util/m5/src/args.cc
index b6bd1c8..1caad43 100644
--- a/util/m5/src/args.cc
+++ b/util/m5/src/args.cc
@@ -38,39 +38,20 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include
-#include
#include
#include "args.hh"
bool
-parse_int_args(Args &args, uint64_t ints[], int len)
-{
-// On 32 bit platforms we need to use strtoull to do the conversion
-#ifdef __LP64__
-#define strto64 strtoul
-#else
-#define strto64 strtoull
-#endif
-for (int i = 0; i < len; ++i)
-ints[i] = strto64(args.pop("0").c_str(), NULL, 0);
-
-#undef strto64
-return true;
-}
-
-bool
-pack_arg_into_regs(Args &args, uint64_t regs[], int num_regs)
+Args::pack(const std::string &str, uint64_t regs[], int num_regs)
{
const size_t RegSize = sizeof(regs[0]);
const size_t MaxLen = num_regs * RegSize;
-const std::string &sarg = args.pop();
-const char *arg = sarg.c_str();
+const char *arg = str.c_str();
memset(regs, 0, MaxLen);
-size_t len = sarg.size();
+size_t len = str.size();
if (len > MaxLen)
return false;
diff --git a/util/m5/src/args.hh b/util/m5/src/args.hh
index 1afd2f2..b541533 100644
--- a/util/m5/src/args.hh
+++ b/util/m5/src/args.hh
@@ -41,9 +41,9 @@
#ifndef __ARGS_HH__
#define __ARGS_HH__
-#include
#include
#include
+#include
#include
#include
@@ -61,19 +61,115 @@
}
Args(std::initializer_list strings) : args(strings) {}
+/*
+ * Attempt to convert str into an integer.
+ *
+ * Return whether that succeeded.
+ */
+static bool
+stoi(const std::string &str, uint64_t &val)
+{
+try {
+val = std::stoi(str, nullptr, 0);
+return true;
+} catch (const std::invalid_argument &e) {
+return false;
+} catch (const std::out_of_range &e) {
+return false;
+}
+}
+
+/*
+ * Attempt to convert str into an integer.
+ *
+ * Return whether that suceeded. If not, val will be set to def.
+ */
+static bool
+stoi(const std::string &str, uint64_t &val, uint64_t def)
+{
+val = def;
+return stoi(str, val);
+}
+
+/*
+ * Attempt to pack str as a sequence of bytes in to regs in little
endian
+ * byte order.
+ *
+ * Return whether that succeeded.
+ */
+static bool pack(const std::string &str, uint64_t regs[], int
num_regs);
+
+/*
+ * If there are any arguments in the list, remove and return the first
+ * one. If not, return def instead.
+ */
const std::string &
-pop(const std::string &def = "") {
+pop(const std::string &def = "")
+{
if (!size())
return def;
return args[offset++];
}
+/*
+ * If there are any arguments in the list, attempt to convert the first
+ * one to an integer. If successful, remove it and store its value in
val.
+ *
+ * Return whether that succeeded.
+ */
+bool
+pop(uint64_t &val)
+{
+if (!size() || !stoi(args[offset], val)) {
+return false;
+} else {
+offset++;
+return true;
+}
+}
+
+/*
+ * If there are any arguments in the list, attempt to convert the first
+ * one to an integer. If successful, remove it and store its value in
val.
+ * If there are no arguments or the conversion failed, set val to def.
+ *
+ * Return true if there were no arguments, or there were and the
conversion
+ * succeeded.
+ */
+bool
+pop(uint64_t &val, uint64_t def)
+{
+val = def;
+if (!size())
+return true;
+if (stoi(args[offset], val)) {
+offset++;
+return true;
+}
+return false;
+}
+
+/*
+ * If
[gem5-dev] Change in gem5/gem5[develop]: base,scons: `-wno-deprecated-copy` added for hdf5.cc with GCC 9+
Bobby R. Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31754 )
Change subject: base,scons: `-wno-deprecated-copy` added for hdf5.cc with
GCC 9+
..
base,scons: `-wno-deprecated-copy` added for hdf5.cc with GCC 9+
As highlighted by Ciro here:
https://gem5-review.googlesource.com/c/public/gem5/+/31216, and
here: https://gem5.atlassian.net/browse/GEM5-365, It appears that GCC
versions >= 9 require the `-wno-deprecated-copy` which was removed in
commit: https://gem5-review.googlesource.com/c/public/gem5/+/31216.
This commit ensures the correct flag is set for the each compiler.
Change-Id: I233b32aa945d479dd429bb5591272608ba342d8d
---
M src/base/SConscript
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/base/SConscript b/src/base/SConscript
index 657528c..7db46f8 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -28,6 +28,8 @@
Import('*')
+from m5.util import compareVersions
+
if env['CP_ANNOTATE']:
SimObject('CPA.py')
Source('cp_annotate.cc')
@@ -91,7 +93,10 @@
Source('stats/group.cc')
Source('stats/text.cc')
if env['USE_HDF5']:
-Source('stats/hdf5.cc', append={'CXXFLAGS': '-Wno-deprecated'})
+if main['GCC'] and compareVersions(main['GCC_VERSION'], '9.0') >= 0:
+Source('stats/hdf5.cc',
append={'CXXFLAGS': '-Wno-deprecated-copy'})
+else:
+Source('stats/hdf5.cc', append={'CXXFLAGS': '-Wno-deprecated'})
GTest('addr_range.test', 'addr_range.test.cc')
GTest('addr_range_map.test', 'addr_range_map.test.cc')
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31754
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I233b32aa945d479dd429bb5591272608ba342d8d
Gerrit-Change-Number: 31754
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: util: c++-ify the commands in the m5 utility.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27554 )
Change subject: util: c++-ify the commands in the m5 utility.
..
util: c++-ify the commands in the m5 utility.
Change-Id: I6755892c42aa418aed64f1aafcdb8c1290b2e8d5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27554
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M util/m5/src/commands.cc
M util/m5/src/commands.hh
M util/m5/src/m5.cc
M util/m5/src/usage.cc
4 files changed, 120 insertions(+), 142 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/util/m5/src/commands.cc b/util/m5/src/commands.cc
index b59633b..c779e80 100644
--- a/util/m5/src/commands.cc
+++ b/util/m5/src/commands.cc
@@ -26,88 +26,90 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include
-#include
-#include
-
-#include
-#include
-#include
#include
+#include
#include
#include "args.hh"
#include "commands.hh"
#include "usage.hh"
-static int
-read_file(const DispatchTable &dt, int dest_fid)
+void
+Command::run(const DispatchTable &dt, Args &args)
{
-uint8_t buf[256*1024];
-int offset = 0;
-int len, ret;
+const int num_args = args.size();
+if (num_args < minArgs || num_args > maxArgs)
+usage();
+
+func(dt, args);
+}
+
+
+static int
+read_file(const DispatchTable &dt, std::ostream &os)
+{
+char buf[256 * 1024];
// Touch all buffer pages to ensure they are mapped in the
// page table. This is required in the case of X86_FS, where
// Linux does demand paging.
memset(buf, 0, sizeof(buf));
+int len;
+int offset = 0;
while ((len = (*dt.m5_read_file)(buf, sizeof(buf), offset)) > 0) {
-uint8_t *base = buf;
+os.write(buf, len);
+os.flush();
+if (!os) {
+std::cerr << "Failed to write file" << std::endl;
+exit(2);
+}
offset += len;
-do {
-ret = write(dest_fid, base, len);
-if (ret < 0) {
-perror("Failed to write file");
-exit(2);
-} else if (ret == 0) {
-fprintf(stderr, "Failed to write file: "
-"Unhandled short write\n");
-exit(2);
-}
-
-base += ret;
-len -= ret;
-} while (len);
}
return offset;
}
static void
-write_file(const DispatchTable &dt, const char *filename,
- const char *host_filename)
+write_file(const DispatchTable &dt, const std::string &filename,
+ const std::string &host_filename)
{
-fprintf(stderr, "opening %s\n", filename);
-int src_fid = open(filename, O_RDONLY);
+std::cerr << "opening " << filename << std::endl;
+std::ifstream src(filename, std::ios_base::in | std::ios_base::binary);
-if (src_fid < 0) {
-fprintf(stderr, "error opening %s\n", filename);
+if (!src) {
+std::cerr << "error opening " << filename << std::endl;
return;
}
-char buf[256*1024];
+char buf[256 * 1024];
int offset = 0;
-int len;
-int bytes = 0;
memset(buf, 0, sizeof(buf));
-while ((len = read(src_fid, buf, sizeof(buf))) > 0) {
-bytes += (*dt.m5_write_file)(buf, len, offset, host_filename);
-offset += len;
+while (true) {
+src.seekg(offset);
+src.read(buf, sizeof(buf));
+int len = src.gcount();
+if (!src && !src.eof())
+break;
+char *wbuf = buf;
+while (len) {
+int bytes = (*dt.m5_write_file)(
+wbuf, len, offset, host_filename.c_str());
+len -= bytes;
+offset += bytes;
+wbuf += bytes;
+}
+if (src.eof())
+break;
}
-fprintf(stderr, "written %d bytes\n", bytes);
-
-close(src_fid);
+std::cerr << "Wrote " << offset << " bytes." << std::endl;
}
static void
do_exit(const DispatchTable &dt, Args &args)
{
-if (args.size() > 1)
-usage();
-
uint64_t ns_delay;
if (!args.pop(ns_delay, 0))
usage();
@@ -118,9 +120,6 @@
static void
do_fail(const DispatchTable &dt, Args &args)
{
-if (args.size() > 2)
-usage();
-
uint64_t ns_delay, code;
if (!args.pop(code) || !args.pop(ns_delay, 0))
usage();
@@ -131,9 +130,6 @@
static void
do_reset_stats(const DispatchTable &dt, Args &args)
{
-if (args.size() > 2)
-usage();
-
uint64_t ns_delay, ns_period;
if (!args.pop(ns_delay, 0) || !args.pop(ns_period, 0))
usage();
@@ -144,9 +140,6 @@
static void
do_dump_stats(const DispatchTable &dt, Args &args)
{
-if (args.size() > 2)
-usage();
-
uint64_t ns_delay, ns_period;
if (!args.pop(ns_delay, 0) || !ar
[gem5-dev] Change in gem5/gem5[develop]: util: Make the device file name used by map_m5_mem overridable.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27556 )
Change subject: util: Make the device file name used by map_m5_mem
overridable.
..
util: Make the device file name used by map_m5_mem overridable.
The name this function uses is now exposed as a global variable called
m5_mmap_dev which can be changed at run time.
This would be useful if using a non-standard location for /dev/mem, or
for testing where we might want to use a totally different device.
Change-Id: I5e7ac106c3e4e0555c99af2a7a0aca8171534451
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27556
Reviewed-by: Jason Lowe-Power
Reviewed-by: Pouya Fotouhi
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M util/m5/src/m5_mmap.c
M util/m5/src/m5_mmap.h
2 files changed, 8 insertions(+), 4 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Pouya Fotouhi: Looks good to me, approved
kokoro: Regressions pass
diff --git a/util/m5/src/m5_mmap.c b/util/m5/src/m5_mmap.c
index 4a5aa0f..d341303 100644
--- a/util/m5/src/m5_mmap.c
+++ b/util/m5/src/m5_mmap.c
@@ -38,9 +38,11 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include
#include
#include
#include
+#include
#include
#include
#include
@@ -54,21 +56,23 @@
#endif
uint64_t m5op_addr = M5OP_ADDR;
+const char *m5_mmap_dev = "/dev/mem";
+
void
map_m5_mem()
{
int fd;
-fd = open("/dev/mem", O_RDWR | O_SYNC);
+fd = open(m5_mmap_dev, O_RDWR | O_SYNC);
if (fd == -1) {
-perror("Can't open /dev/mem");
+fprintf(stderr, "Can't open %s: %s\n", m5_mmap_dev,
strerror(errno));
exit(1);
}
m5_mem = mmap(NULL, 0x1, PROT_READ | PROT_WRITE, MAP_SHARED, fd,
m5op_addr);
if (!m5_mem) {
-perror("Can't mmap /dev/mem");
+fprintf(stderr, "Can't map %s: %s\n", m5_mmap_dev,
strerror(errno));
exit(1);
}
}
diff --git a/util/m5/src/m5_mmap.h b/util/m5/src/m5_mmap.h
index d7fe19b..09cddb2 100644
--- a/util/m5/src/m5_mmap.h
+++ b/util/m5/src/m5_mmap.h
@@ -49,7 +49,7 @@
extern void *m5_mem;
extern uint64_t m5op_addr;
-
+extern const char *m5_mmap_dev;
void map_m5_mem();
#ifdef __cplusplus
--
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Gerrit-Change-Id: I5e7ac106c3e4e0555c99af2a7a0aca8171534451
Gerrit-Change-Number: 27556
Gerrit-PatchSet: 22
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
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[gem5-dev] Change in gem5/gem5[develop]: util: c++-ify usage printing in the m5 utility.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27555 )
Change subject: util: c++-ify usage printing in the m5 utility.
..
util: c++-ify usage printing in the m5 utility.
Change-Id: Ice8641d490fa9a510a6f1e246530ca5c82ef8170
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27555
Reviewed-by: Jason Lowe-Power
Reviewed-by: Daniel Carvalho
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M util/m5/src/usage.cc
1 file changed, 11 insertions(+), 12 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
kokoro: Regressions pass
diff --git a/util/m5/src/usage.cc b/util/m5/src/usage.cc
index 60ceedf..bbcf36a 100644
--- a/util/m5/src/usage.cc
+++ b/util/m5/src/usage.cc
@@ -38,9 +38,8 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include
-#include
#include
+#include
#include "call_type.hh"
#include "commands.hh"
@@ -51,16 +50,16 @@
void
usage()
{
-fprintf(stderr, "Usage: %s [call type] [arguments]\n",
-progname.c_str());
-fprintf(stderr, "\n");
-fprintf(stderr, "Call types:\n");
-fprintf(stderr, CallType::usageSummary().c_str());
-fprintf(stderr, "\n");
-fprintf(stderr, "Commands:\n");
-fprintf(stderr, Command::usageSummary().c_str());
-fprintf(stderr, "\n");
-fprintf(stderr, "All times in nanoseconds!\n");
+std::cerr << "Usage: " << progname <<
+"[call type] [arguments]" << std::endl <<
+std::endl <<
+"Call types:" << std::endl <<
+CallType::usageSummary() <<
+std::endl <<
+"Commands:" << std::endl <<
+Command::usageSummary() <<
+std::endl <<
+"All times in nanoseconds!" << std::endl;
exit(1);
}
--
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Gerrit-Change-Id: Ice8641d490fa9a510a6f1e246530ca5c82ef8170
Gerrit-Change-Number: 27555
Gerrit-PatchSet: 22
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
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Gerrit-Reviewer: kokoro
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[gem5-dev] Change in gem5/gem5[develop]: util: Expose the "sum" m5 op in the m5 utility.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27558 )
Change subject: util: Expose the "sum" m5 op in the m5 utility.
..
util: Expose the "sum" m5 op in the m5 utility.
This is just for testing purposes, and can be used to sanity check that
m5 ops work when running a simulation.
Change-Id: I784d033fe4704e60ace5d109beac7bafe1498de6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27558
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M util/m5/src/commands.cc
1 file changed, 15 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/util/m5/src/commands.cc b/util/m5/src/commands.cc
index c779e80..2d71f93 100644
--- a/util/m5/src/commands.cc
+++ b/util/m5/src/commands.cc
@@ -117,6 +117,19 @@
(*dt.m5_exit)(ns_delay);
}
+// For testing purposes.
+static void
+do_sum(const DispatchTable &dt, Args &args)
+{
+uint64_t a, b, c, d, e, f;
+if (!args.pop(a) || !args.pop(b) || !args.pop(c, 0) ||
+!args.pop(d, 0) || !args.pop(e, 0) || !args.pop(f, 0))
+usage();
+
+unsigned sum = (*dt.m5_sum)(a, b, c, d, e, f);
+std::cout << "Sum is " << sum << "." << std::endl;
+}
+
static void
do_fail(const DispatchTable &dt, Args &args)
{
@@ -230,6 +243,8 @@
"Exit after delay, or immediately" }},
{ "fail", { 1, 2, do_fail, " [delay]\n"
"Exit with failure code code after delay, or immediately"
}},
+{ "sum", { 2, 6, do_sum, " [c [d [e [f\n"
+"Sum a-f (defaults are 0), for testing purposes" }},
{ "initparam", { 1, 1, do_initparam, "[key]\n"
"optional key may be at most 16 characters long" }},
{ "loadsymbol", { 0, 0, do_loadsymbol, "\n"
--
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Gerrit-Change-Number: 27558
Gerrit-PatchSet: 23
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Pouya Fotouhi
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch,sim,misc: Add a new m5 op "sum" which just sums its inputs.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27557 )
Change subject: arch,sim,misc: Add a new m5 op "sum" which just sums its
inputs.
..
arch,sim,misc: Add a new m5 op "sum" which just sums its inputs.
This very simple and mostly useless operation has no side effects, and
can be used to verify that arguments are making it into gem5, being
operated on, and then that a result can be returned into the simulation.
Change-Id: I29bce824078526ff77513c80365f8fad88fef128
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27557
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M include/gem5/asm/generic/m5ops.h
M include/gem5/m5ops.h
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/m5ops.isa
M src/arch/arm/isa/insts/m5ops.isa
M src/arch/arm/isa/operands.isa
M src/arch/sparc/isa/decoder.isa
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M src/arch/x86/isa/operands.isa
M src/sim/pseudo_inst.cc
M src/sim/pseudo_inst.hh
11 files changed, 64 insertions(+), 4 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/include/gem5/asm/generic/m5ops.h
b/include/gem5/asm/generic/m5ops.h
index f175596..20f38d3 100644
--- a/include/gem5/asm/generic/m5ops.h
+++ b/include/gem5/asm/generic/m5ops.h
@@ -53,6 +53,7 @@
#define M5OP_DEPRECATED30x20 // deprecated exit function
#define M5OP_EXIT 0x21
#define M5OP_FAIL 0x22
+#define M5OP_SUM0x23 // For testing
#define M5OP_INIT_PARAM 0x30
#define M5OP_LOAD_SYMBOL0x31
#define M5OP_RESET_STATS0x40
@@ -90,6 +91,7 @@
M5OP(m5_wake_cpu, M5OP_WAKE_CPU)\
M5OP(m5_exit, M5OP_EXIT)\
M5OP(m5_fail, M5OP_FAIL)\
+M5OP(m5_sum, M5OP_SUM) \
M5OP(m5_init_param, M5OP_INIT_PARAM)\
M5OP(m5_load_symbol, M5OP_LOAD_SYMBOL) \
M5OP(m5_reset_stats, M5OP_RESET_STATS) \
diff --git a/include/gem5/m5ops.h b/include/gem5/m5ops.h
index 3edd4e6..fddbf53 100644
--- a/include/gem5/m5ops.h
+++ b/include/gem5/m5ops.h
@@ -45,6 +45,9 @@
void m5_exit(uint64_t ns_delay);
void m5_fail(uint64_t ns_delay, uint64_t code);
+// m5_sum is for sanity checking the gem5 op interface.
+unsigned m5_sum(unsigned a, unsigned b, unsigned c,
+unsigned d, unsigned e, unsigned f);
uint64_t m5_init_param(uint64_t key_str1, uint64_t key_str2);
void m5_checkpoint(uint64_t ns_delay, uint64_t ns_period);
void m5_reset_stats(uint64_t ns_delay, uint64_t ns_period);
diff --git a/src/arch/arm/isa/formats/aarch64.isa
b/src/arch/arm/isa/formats/aarch64.isa
index 4ff5456..2730e42 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -3031,6 +3031,7 @@
case M5OP_DEPRECATED3: return new Deprecated_exit (machInst);
case M5OP_EXIT: return new M5exit64(machInst);
case M5OP_FAIL: return new M5fail64(machInst);
+ case M5OP_SUM: return new M5sum64(machInst);
case M5OP_LOAD_SYMBOL: return new Loadsymbol(machInst);
case M5OP_INIT_PARAM: return new Initparam64(machInst);
case M5OP_RESET_STATS: return new Resetstats64(machInst);
diff --git a/src/arch/arm/isa/formats/m5ops.isa
b/src/arch/arm/isa/formats/m5ops.isa
index bbe6649..6120644 100644
--- a/src/arch/arm/isa/formats/m5ops.isa
+++ b/src/arch/arm/isa/formats/m5ops.isa
@@ -52,6 +52,7 @@
case M5OP_DEPRECATED3: return new Deprecated_exit (machInst);
case M5OP_EXIT: return new M5exit(machInst);
case M5OP_FAIL: return new M5fail(machInst);
+case M5OP_SUM: return new M5sum(machInst);
case M5OP_LOAD_SYMBOL: return new Loadsymbol(machInst);
case M5OP_INIT_PARAM: return new Initparam(machInst);
case M5OP_RESET_STATS: return new Resetstats(machInst);
diff --git a/src/arch/arm/isa/insts/m5ops.isa
b/src/arch/arm/isa/insts/m5ops.isa
index 4bae7a3..3dcec7e 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -279,6 +279,28 @@
PseudoInst::loadsymbol(xc->tcBase());
'''
+m5sum_code = '''
+R0 = PseudoInst::m5sum(xc->tcBase(), R0, R1, R2, R3, R4, R5);
+'''
+m5sumIop = InstObjParams("m5sum", "M5sum", "PredOp",
+ { "code": m5sum_code,
+ "predicate_test": predicateTest },
+ ["No_OpClass", "IsNonSpeculative"])
+header_output += BasicDeclare.subst(m5sumIop)
+decoder_output += BasicConstructor.subst(m5sumIop)
+exec_output += PredOpExecute.subst(m
[gem5-dev] Change in gem5/gem5[develop]: misc: Replace scalar TypedBufferArg with VPtr.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31755 )
Change subject: misc: Replace scalar TypedBufferArg with VPtr.
..
misc: Replace scalar TypedBufferArg with VPtr.
Change-Id: Ic8460ad133e3512c103b14820d90ee3df987d78d
---
M src/arch/arm/aapcs32.hh
M src/arch/arm/aapcs64.hh
M src/dev/hsa/hsa_driver.cc
M src/dev/hsa/hsa_packet_processor.cc
M src/sim/syscall_emul.cc
M src/sim/syscall_emul.hh
6 files changed, 21 insertions(+), 36 deletions(-)
diff --git a/src/arch/arm/aapcs32.hh b/src/arch/arm/aapcs32.hh
index e2e5d09..01663ff 100644
--- a/src/arch/arm/aapcs32.hh
+++ b/src/arch/arm/aapcs32.hh
@@ -38,7 +38,7 @@
#include "base/intmath.hh"
#include "cpu/thread_context.hh"
#include "sim/guest_abi.hh"
-#include "sim/syscall_emul_buf.hh"
+#include "sim/proxy_ptr.hh"
class ThreadContext;
@@ -113,8 +113,7 @@
state.nsaa = roundUp(state.nsaa, align);
// Extract the value from it.
-TypedBufferArg val(state.nsaa);
-val.copyIn(tc->getVirtProxy());
+ConstVPtr val(state.nsaa, tc);
// Move the nsaa past this argument.
state.nsaa += size;
@@ -284,9 +283,8 @@
val = gtoh(val, ArmISA::byteOrder(tc));
tc->setIntReg(ArmISA::INTREG_R0, val);
} else {
-TypedBufferArg cp(state.retAddr);
-cp = htog(composite, ArmISA::byteOrder(tc));
-cp.copyOut(tc->getVirtProxy());
+VPtr cp(state.retAddr, tc);
+*cp = htog(composite, ArmISA::byteOrder(tc));
}
}
diff --git a/src/arch/arm/aapcs64.hh b/src/arch/arm/aapcs64.hh
index 30597f5..0c11215 100644
--- a/src/arch/arm/aapcs64.hh
+++ b/src/arch/arm/aapcs64.hh
@@ -38,7 +38,7 @@
#include "base/intmath.hh"
#include "cpu/thread_context.hh"
#include "sim/guest_abi.hh"
-#include "sim/syscall_emul_buf.hh"
+#include "sim/proxy_ptr.hh"
class ThreadContext;
@@ -158,8 +158,7 @@
state.nsaa = roundUp(state.nsaa, align);
// Extract the value from it.
-TypedBufferArg val(state.nsaa);
-val.copyIn(tc->getVirtProxy());
+ConstVPtr val(state.nsaa, tc);
// Move the nsaa past this argument.
state.nsaa += size;
@@ -350,8 +349,7 @@
// kept in a buffer, and the argument is actually a pointer to
that
// buffer.
Addr addr = Argument::get(tc, state);
-TypedBufferArg composite(addr);
-composite.copyIn(tc->getVirtProxy());
+ConstVPtr composite(addr, tc);
return gtoh(*composite, ArmISA::byteOrder(tc));
}
@@ -393,7 +391,7 @@
{
if (sizeof(Composite) > 16) {
Addr addr = tc->readIntReg(ArmISA::INTREG_X8);
-TypedBufferArg composite(addr);
+VPtr composite(addr, tc);
*composite = htog(c, ArmISA::byteOrder(tc));
return;
}
diff --git a/src/dev/hsa/hsa_driver.cc b/src/dev/hsa/hsa_driver.cc
index 459043d..a1215c4 100644
--- a/src/dev/hsa/hsa_driver.cc
+++ b/src/dev/hsa/hsa_driver.cc
@@ -42,7 +42,7 @@
#include "dev/hsa/kfd_ioctl.h"
#include "params/HSADriver.hh"
#include "sim/process.hh"
-#include "sim/syscall_emul_buf.hh"
+#include "sim/proxy_ptr.hh"
HSADriver::HSADriver(HSADriverParams *p)
: EmulatedDriver(p), device(p->device), queueId(0)
diff --git a/src/dev/hsa/hsa_packet_processor.cc
b/src/dev/hsa/hsa_packet_processor.cc
index 4143019..f6da9cb 100644
--- a/src/dev/hsa/hsa_packet_processor.cc
+++ b/src/dev/hsa/hsa_packet_processor.cc
@@ -47,7 +47,7 @@
#include "mem/packet_access.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"
-#include "sim/syscall_emul_buf.hh"
+#include "sim/proxy_ptr.hh"
#include "sim/system.hh"
#define HSAPP_EVENT_DESCRIPTION_GENERATOR(XEVENT) \
@@ -408,13 +408,10 @@
* The reason for this is that the DMASequencer does
* not support atomic operations.
*/
-auto tc = sys->threads[0];
-auto &virt_proxy = tc->getVirtProxy();
-TypedBufferArg prev_signal(signal_addr);
-prev_signal.copyIn(virt_proxy);
+VPtr prev_signal(signal_addr, sys->threads[0]);
hsa_signal_value_t *new_signal = new hsa_signal_value_t;
-*new_signal = (hsa_signal_value_t) *prev_signal - 1;
+*new_signal = (hsa_signal_value_t)*prev_signal - 1;
dmaWriteVirt(signal_addr,
sizeof(hsa_signal_value_t), NULL, new_signal,
0);
diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc
index 4a41609..b271a5f 100644
--- a/src/sim/syscall_emul.cc
+++ b/src/sim/syscall_emul.cc
@@ -47,6 +47,7 @@
#include "mem/page_table.hh"
#include "sim/byteswap.hh"
#include "sim/process.hh"
+#include "sim/proxy_ptr.hh"
#include "sim/sim_exit.hh"
#include "sim/s
