[gem5-dev] Change in gem5/gem5[develop]: util: Add a "writefile" unit test to the m5 utility.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27628 )
Change subject: util: Add a "writefile" unit test to the m5 utility.
..
util: Add a "writefile" unit test to the m5 utility.
Change-Id: Ic0e8d5fbbd5b6d6b57f674cef6460f94206a5872
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27628
Reviewed-by: Jason Lowe-Power
Maintainer: Gabe Black
Tested-by: Gem5 Cloud Project GCB service account
<345032938...@cloudbuild.gserviceaccount.com>
---
M util/m5/src/command/SConscript.native
A util/m5/src/command/writefile.test.cc
2 files changed, 248 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Gabe Black: Looks good to me, approved
Gem5 Cloud Project GCB service account: Regressions pass
diff --git a/util/m5/src/command/SConscript.native
b/util/m5/src/command/SConscript.native
index 7d23b2a..fc3e975 100644
--- a/util/m5/src/command/SConscript.native
+++ b/util/m5/src/command/SConscript.native
@@ -37,6 +37,7 @@
'readfile',
'resetstats',
'sum',
+'writefile',
)
Return('command_tests')
diff --git a/util/m5/src/command/writefile.test.cc
b/util/m5/src/command/writefile.test.cc
new file mode 100644
index 000..a1adf5c
--- /dev/null
+++ b/util/m5/src/command/writefile.test.cc
@@ -0,0 +1,247 @@
+/*
+ * Copyright 2020 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+
+#include "args.hh"
+#include "command.hh"
+#include "dispatch_table.hh"
+
+uint64_t test_total_written;
+std::string test_host_file_name;
+
+std::vector test_written_data;
+uint64_t test_max_buf_size;
+
+uint64_t
+test_m5_write_file(void *buffer, uint64_t len, uint64_t offset,
+ const char *filename)
+{
+if (test_max_buf_size && len > test_max_buf_size)
+len = test_max_buf_size;
+
+test_total_written += len;
+
+if (test_host_file_name == "")
+test_host_file_name = filename;
+else
+EXPECT_EQ(test_host_file_name, filename);
+
+if (offset == 0)
+test_written_data.clear();
+
+size_t required_size = offset + len;
+if (test_written_data.size() < required_size)
+test_written_data.resize(required_size);
+
+memcpy(test_written_data.data() + offset, buffer, len);
+
+return len;
+}
+
+DispatchTable dt = { .m5_write_file = _m5_write_file };
+
+std::string cout_output;
+
+bool
+run(std::initializer_list arg_args)
+{
+test_total_written = 0;
+test_host_file_name = "";
+test_written_data.clear();
+
+Args args(arg_args);
+
+// Redirect cout into a stringstream.
+std::stringstream buffer;
+std::streambuf *orig = std::cout.rdbuf(buffer.rdbuf());
+
+bool res = Command::run(dt, args);
+
+// Capture the contents of the stringstream and restore cout.
+cout_output = buffer.str();
+std::cout.rdbuf(orig);
+
+return res;
+}
+
+class TempFile
+{
+ private:
+size_t _size;
+int fd;
+std::string _path;
+void *_buf;
+
+ public:
+TempFile(size_t _size) : _size(_size)
+{
+// Generate a temporary filename.
+char *tmp_name = strdup("/tmp/writefile.test.");
+fd = mkstemp(tmp_name);
+_path = tmp_name;
+free(tmp_name);
+
+// Make the file the appropriate length.
+assert(!ftruncate(fd, _size));
+
+//
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: resolve race between data and DMA in MOESI_AMD_Base-dir
Kyle Roarty has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31996 )
Change subject: mem-ruby: resolve race between data and DMA in
MOESI_AMD_Base-dir
..
mem-ruby: resolve race between data and DMA in MOESI_AMD_Base-dir
There seems to be race condition while running several benchmarks, where
the DMA engine and the CorePair simultaneously send requests for the
same block. This patch fixes two scenarios
(a) If the request from the DMA engine arrives before the one from the
CorePair, the directory controller records it as a pending request.
However, once the DMA request is serviced, the directory doesn't check
for pending requests. The CorePair, consequently, never sees a response
to its request and this results in a Deadlock.
Added call to wakeUpDependents in the transition from BDR_Pm to U
Added call to wakeUpDependents in the transition from BDW_P to U
(b) If the request from the CorePair is being serviced by the directory
and the DMA requests for the same block, this causes an invalid
transition because the current coherence doesn't take care of this
scenario.
Added transition state where the requests from DMA are added to the
stall buffer.
Updated B to U CoreUnblock transition to check all buffers, as the DMA
requests were being placed later in the stall buffer than was being checked
Change-Id: I5a76efef97723bc53cf239ea7e112f84fc874ef8
---
M src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
M src/mem/ruby/slicc_interface/AbstractController.cc
2 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
index c8dafd5..f1bc637 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
@@ -180,6 +180,7 @@
void set_tbe(TBE a);
void unset_tbe();
void wakeUpAllBuffers();
+ void wakeUpAllBuffers(Addr a);
void wakeUpBuffers(Addr a);
Cycles curCycle();
@@ -1069,6 +1070,10 @@
stall_and_wait(requestNetwork_in, address);
}
+ action(sd_stallAndWaitRequest, "sd", desc="Stall and wait on the
address") {
+stall_and_wait(dmaRequestQueue_in, address);
+ }
+
action(wa_wakeUpDependents, "wa", desc="Wake up any requests waiting for
this address") {
wakeUpBuffers(address);
}
@@ -1077,6 +1082,10 @@
wakeUpAllBuffers();
}
+ action(wa_wakeUpAllDependentsAddr, "waaa", desc="Wake up any requests
waiting for this address") {
+wakeUpAllBuffers(address);
+ }
+
action(z_stall, "z", desc="...") {
}
@@ -1090,6 +1099,11 @@
st_stallAndWaitRequest;
}
+ // The exit state is always going to be U, so wakeUpDependents logic
should be covered in all the
+ // transitions which are flowing into U.
+ transition({BL, BS_M, BM_M, B_M, BP, BDW_P, BS_PM, BM_PM, B_PM, BS_Pm,
BM_Pm, B_Pm, B}, {DmaRead,DmaWrite}){
+sd_stallAndWaitRequest;
+ }
// transitions from U
transition(U, DmaRead, BDR_PM) {L3TagArrayRead} {
@@ -1193,7 +1207,7 @@
}
transition({B}, CoreUnblock, U) {
-wa_wakeUpDependents;
+wa_wakeUpAllDependentsAddr;
pu_popUnblockQueue;
}
@@ -1323,12 +1337,18 @@
}
transition(BDW_P, ProbeAcksComplete, U) {
+// Check for pending requests from the core we put to sleep while
waiting
+// for a response
+wa_wakeUpAllDependentsAddr;
dt_deallocateTBE;
pt_popTriggerQueue;
}
transition(BDR_Pm, ProbeAcksComplete, U) {
dd_sendResponseDmaData;
+// Check for pending requests from the core we put to sleep while
waiting
+// for a response
+wa_wakeUpDependents;
dt_deallocateTBE;
pt_popTriggerQueue;
}
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc
b/src/mem/ruby/slicc_interface/AbstractController.cc
index 9da8727..d2b3370 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -149,8 +149,7 @@
{
if (m_waiting_buffers.count(addr) > 0) {
//
-// Wake up all possible lower rank (i.e. lower priority) buffers
that could
-// be waiting on this message.
+// Wake up all possible buffers that could be waiting on this
message.
//
for (int in_port_rank = m_in_ports - 1;
in_port_rank >= 0;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31996
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5a76efef97723bc53cf239ea7e112f84fc874ef8
Gerrit-Change-Number: 31996
Gerrit-PatchSet: 1
Gerrit-Owner: Kyle Roarty
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: configs: set hsaTopology properties from options
Kyle Roarty has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/31995 ) Change subject: configs: set hsaTopology properties from options .. configs: set hsaTopology properties from options Change-Id: I17bb812491708f4221c39b738c906f1ad944614d --- M configs/example/hsaTopology.py 1 file changed, 25 insertions(+), 24 deletions(-) diff --git a/configs/example/hsaTopology.py b/configs/example/hsaTopology.py index df24223..7cb18ad 100644 --- a/configs/example/hsaTopology.py +++ b/configs/example/hsaTopology.py @@ -36,6 +36,7 @@ from os.path import join as joinpath from os.path import isdir from shutil import rmtree, copyfile +from m5.util.convert import toFrequency def file_append(path, contents): with open(joinpath(*path), 'a') as f: @@ -77,29 +78,29 @@ # populate global node properties # NOTE: SIMD count triggers a valid GPU agent creation # TODO: Really need to parse these from options -node_prop = 'cpu_cores_count %s\n' % options.num_cpus + \ -'simd_count 32\n' + \ -'mem_banks_count 0\n' + \ -'caches_count 0\n' + \ -'io_links_count 0\n'+ \ -'cpu_core_id_base 16\n' + \ -'simd_id_base 2147483648\n' + \ -'max_waves_per_simd 40\n' + \ -'lds_size_in_kb 64\n' + \ -'gds_size_in_kb 0\n'+ \ -'wave_front_size 64\n' + \ -'array_count 1\n' + \ -'simd_arrays_per_engine 1\n'+ \ -'cu_per_simd_array 10\n'+ \ -'simd_per_cu 4\n' + \ -'max_slots_scratch_cu 32\n' + \ -'vendor_id 4098\n' + \ -'device_id 39028\n' + \ -'location_id 8\n' + \ -'max_engine_clk_fcompute 800\n' + \ -'local_mem_size 0\n'+ \ -'fw_version 699\n' + \ -'capability 4738\n' + \ -'max_engine_clk_ccompute 2100\n' +node_prop = 'cpu_cores_count %s\n' % options.num_cpus + \ +'simd_count %s\n' % (options.num_compute_units * options.simds_per_cu) + \ +'mem_banks_count 0\n' + \ +'caches_count 0\n' + \ +'io_links_count 0\n'+ \ +'cpu_core_id_base 16\n' + \ +'simd_id_base 2147483648\n' + \ +'max_waves_per_simd %s\n' % options.wfs_per_simd+ \ +'lds_size_in_kb 64\n' + \ +'gds_size_in_kb 0\n'+ \ +'wave_front_size %s\n' % options.wf_size+ \ +'array_count 1\n' + \ +'simd_arrays_per_engine %s\n' % options.sa_per_complex + \ +'cu_per_simd_array %s\n' % options.cu_per_sa+ \ +'simd_per_cu %s\n' % options.simds_per_cu + \ +'max_slots_scratch_cu 32\n' + \ +'vendor_id 4098\n' + \ +'device_id 39028\n' + \ +'location_id 8\n' + \ +'max_engine_clk_fcompute %s\n' % int(toFrequency(options.gpu_clock) / 1e6) + \ +'local_mem_size 0\n'+ \ +'fw_version 699\n' + \ +'capability 4738\n' + \ +'max_engine_clk_ccompute %s\n' % int(toFrequency(options.CPUClock) / 1e6) file_append((node_dir, 'properties'),
[gem5-dev] Change in gem5/gem5[develop]: tests: fix name collisions in verifier.py
Hoa Nguyen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31994 )
Change subject: tests: fix name collisions in verifier.py
..
tests: fix name collisions in verifier.py
In verifier.py, testlib.test_util is imported and renamed to 'test',
while several functions in the file have a subfunction named 'test()',
which causes test.fail() to fail as 'test' points to the
subfunction instead of the module.
This commit addresses the above issue by keeping the imported module
as test_util instead of renaming it to test.
Signed-off-by: Hoa Nguyen
Change-Id: I0ab7b52619f2fa9495e9a6ff8d469c022eea98bc
---
M tests/gem5/verifier.py
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tests/gem5/verifier.py b/tests/gem5/verifier.py
index 815b9bb..471d2c9 100644
--- a/tests/gem5/verifier.py
+++ b/tests/gem5/verifier.py
@@ -29,7 +29,7 @@
'''
import re
-from testlib import test_util as test
+from testlib import test_util
from testlib.configuration import constants
from testlib.helper import joinpath, diff_out_file
@@ -40,11 +40,11 @@
def _test(self, *args, **kwargs):
# Use a callback wrapper to make stack
# traces easier to understand.
-self.test(*args, **kwargs)
+self.test_util(*args, **kwargs)
def instantiate_test(self, name_pfx):
name = '-'.join([name_pfx, self.__class__.__name__])
-return test.TestFunction(self._test,
+return test_util.TestFunction(self._test,
name=name, fixtures=self.fixtures)
class MatchGoldStandard(Verifier):
@@ -80,7 +80,7 @@
ignore_regexes=self.ignore_regex,
logger=params.log)
if diff is not None:
-test.fail('Stdout did not match:\n%s\nSee %s for full results'
+test_util.fail('Stdout did not match:\n%s\nSee %s for full
results'
% (diff, tempdir))
def _generic_instance_warning(self, kwargs):
@@ -184,7 +184,7 @@
if parse_file(joinpath(tempdir,
constants.gem5_simulation_stderr)):
return # Success
-test.fail('Could not match regex.')
+test_util.fail('Could not match regex.')
_re_type = type(re.compile(''))
def _iterable_regex(regex):
--
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Gerrit-Change-Id: I0ab7b52619f2fa9495e9a6ff8d469c022eea98bc
Gerrit-Change-Number: 31994
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-gcn3: add support for flat atomic adds, subs, incs, decs
Matt Sinclair has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31974 )
Change subject: arch-gcn3: add support for flat atomic adds, subs, incs,
decs
..
arch-gcn3: add support for flat atomic adds, subs, incs, decs
Add support for all missing flat atomic adds, subtracts, increments,
and decrements, including their x2 variants.
Change-Id: I37a67fcacca91a09a82be6597facaa366105d2dc
---
M src/arch/gcn3/insts/instructions.cc
M src/arch/gcn3/insts/instructions.hh
2 files changed, 410 insertions(+), 6 deletions(-)
diff --git a/src/arch/gcn3/insts/instructions.cc
b/src/arch/gcn3/insts/instructions.cc
index 426f991..6e81e2c 100644
--- a/src/arch/gcn3/insts/instructions.cc
+++ b/src/arch/gcn3/insts/instructions.cc
@@ -40643,8 +40643,72 @@
void
Inst_FLAT__FLAT_ATOMIC_SUB::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (wf->execMask().none()) {
+wf->decVMemInstsIssued();
+wf->decLGKMInstsIssued();
+wf->wrGmReqsInPipe--;
+wf->rdGmReqsInPipe--;
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->exec_mask = wf->execMask();
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
+ConstVecOperandU32 data(gpuDynInst, extData.DATA);
+
+addr.read();
+data.read();
+
+calcAddr(gpuDynInst, addr);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+(reinterpret_cast(gpuDynInst->a_data))[lane]
+= data[lane];
+}
+}
+
+if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
+gpuDynInst->computeUnit()->globalMemoryPipe.
+issueRequest(gpuDynInst);
+wf->wrGmReqsInPipe--;
+wf->outstandingReqsWrGm++;
+wf->rdGmReqsInPipe--;
+wf->outstandingReqsRdGm++;
+} else {
+fatal("Non global flat instructions not implemented yet.\n");
+}
+
+gpuDynInst->wavefront()->outstandingReqs++;
+gpuDynInst->wavefront()->validateRequestCounters();
}
+void
+Inst_FLAT__FLAT_ATOMIC_SUB::initiateAcc(GPUDynInstPtr gpuDynInst)
+{
+initAtomicAccess(gpuDynInst);
+} // initiateAcc
+
+void
+Inst_FLAT__FLAT_ATOMIC_SUB::completeAcc(GPUDynInstPtr gpuDynInst)
+{
+if (isAtomicRet()) {
+VecOperandU32 vdst(gpuDynInst, extData.VDST);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+vdst[lane] = (reinterpret_cast(
+gpuDynInst->d_data))[lane];
+}
+}
+
+vdst.write();
+}
+} // completeAcc
Inst_FLAT__FLAT_ATOMIC_SMIN::Inst_FLAT__FLAT_ATOMIC_SMIN(InFmt_FLAT
*iFmt)
: Inst_FLAT(iFmt, "flat_atomic_smin")
@@ -40843,9 +40907,74 @@
void
Inst_FLAT__FLAT_ATOMIC_INC::execute(GPUDynInstPtr gpuDynInst)
{
-panicUnimplemented();
+Wavefront *wf = gpuDynInst->wavefront();
+
+if (wf->execMask().none()) {
+wf->decVMemInstsIssued();
+wf->decLGKMInstsIssued();
+wf->wrGmReqsInPipe--;
+wf->rdGmReqsInPipe--;
+return;
+}
+
+gpuDynInst->execUnitId = wf->execUnitId;
+gpuDynInst->exec_mask = wf->execMask();
+gpuDynInst->latency.init(gpuDynInst->computeUnit());
+gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
+
+ConstVecOperandU64 addr(gpuDynInst, extData.ADDR);
+ConstVecOperandU32 data(gpuDynInst, extData.DATA);
+
+addr.read();
+data.read();
+
+calcAddr(gpuDynInst, addr);
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (gpuDynInst->exec_mask[lane]) {
+(reinterpret_cast(gpuDynInst->a_data))[lane]
+= data[lane];
+}
+}
+
+if (gpuDynInst->executedAs() == Enums::SC_GLOBAL) {
+gpuDynInst->computeUnit()->globalMemoryPipe.
+issueRequest(gpuDynInst);
+wf->wrGmReqsInPipe--;
+wf->outstandingReqsWrGm++;
+wf->rdGmReqsInPipe--;
+wf->outstandingReqsRdGm++;
+} else {
+fatal("Non global flat instructions not implemented yet.\n");
+}
+
+gpuDynInst->wavefront()->outstandingReqs++;
+gpuDynInst->wavefront()->validateRequestCounters();
}
+void
+Inst_FLAT__FLAT_ATOMIC_INC::initiateAcc(GPUDynInstPtr gpuDynInst)
+{
+
[gem5-dev] Change in gem5/gem5[develop]: configs: Change env defaults in apu_se.py for ROCm
Matt Sinclair has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30275 )
Change subject: configs: Change env defaults in apu_se.py for ROCm
..
configs: Change env defaults in apu_se.py for ROCm
This change simplifies the setup process for running
ROCm-based programs by adding the libraries that are
needed to LD_LIBRARY_PATH by default, using
preexisting environment variables that should be set
on the host.
HOME also gets set, as MIOpen-based programs can fail
without it set.
Change-Id: Ic599674babeaebb52de8a55981d04454cdc96cd8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30275
Tested-by: kokoro
Reviewed-by: Matt Sinclair
Reviewed-by: Anthony Gutierrez
Reviewed-by: Bradford Beckmann
Maintainer: Anthony Gutierrez
Maintainer: Jason Lowe-Power
---
M configs/example/apu_se.py
1 file changed, 11 insertions(+), 4 deletions(-)
Approvals:
Bradford Beckmann: Looks good to me, approved
Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved
Matt Sinclair: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/example/apu_se.py b/configs/example/apu_se.py
index 4e9c75f..82e4022 100644
--- a/configs/example/apu_se.py
+++ b/configs/example/apu_se.py
@@ -456,11 +456,18 @@
env = [line.rstrip() for line in f]
else:
env = ['LD_LIBRARY_PATH=%s' % ':'.join([
- "/proj/radl_tools/rocm-1.6/lib",
- "/proj/radl_tools/rocm-1.6/hcc/lib64",
- "/tool/pandora64/.package/libunwind-1.1/lib",
- "/tool/pandora64/.package/gcc-6.4.0/lib64"
+ os.getenv('ROCM_PATH','/opt/rocm')+'/lib',
+ os.getenv('HCC_HOME','/opt/rocm/hcc')+'/lib',
+ os.getenv('HSA_PATH','/opt/rocm/hsa')+'/lib',
+ os.getenv('HIP_PATH','/opt/rocm/hip')+'/lib',
+ os.getenv('ROCM_PATH','/opt/rocm')+'/libhsakmt/lib',
+ os.getenv('ROCM_PATH','/opt/rocm')+'/miopen/lib',
+ os.getenv('ROCM_PATH','/opt/rocm')+'/miopengemm/lib',
+ os.getenv('ROCM_PATH','/opt/rocm')+'/hipblas/lib',
+ os.getenv('ROCM_PATH','/opt/rocm')+'/rocblas/lib',
+ "/usr/lib/x86_64-linux-gnu"
]),
+ 'HOME=%s' % os.getenv('HOME','/'),
"HSA_ENABLE_INTERRUPT=0"]
process = Process(executable = executable, cmd = [options.cmd]
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic599674babeaebb52de8a55981d04454cdc96cd8
Gerrit-Change-Number: 30275
Gerrit-PatchSet: 4
Gerrit-Owner: Kyle Roarty
Gerrit-Reviewer: Anthony Gutierrez
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] testlib question
My Jenkins setup is getting errors in testlib.
The test is failing, and trying to call test.fail
from the results.pickle file:
File "/var/lib/jenkins/workspace/stress/tests/../ext/testlib/runner.py",
line 146, in test
test_params.test.test(test_params)
File "/var/lib/jenkins/workspace/stress/tests/../ext/testlib/wrappers.py",
line 147, in test
self.obj.test(*args, **kwargs)
File "/var/lib/jenkins/workspace/stress/tests/../ext/testlib/test_util.py",
line 69, in test
self.test_function(*args, **kwargs)
File "/var/lib/jenkins/workspace/stress/tests/gem5/verifier.py",
line 43, in _test
self.test(*args, **kwargs)
File "/var/lib/jenkins/workspace/stress/tests/gem5/verifier.py",
line 83, in test
test.fail('Stdout did not match:\n%s\nSee %s for full results'
AttributeError: module 'testlib.test_util' has no attribute 'fail'
Any ideas about how to fix? I am not familiar with testlib.
I would like to see the error message it is trying to print.
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[gem5-dev] Change in gem5/gem5[develop]: python: Add DeprecatedParam type
Jason Lowe-Power has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31954 )
Change subject: python: Add DeprecatedParam type
..
python: Add DeprecatedParam type
There are times when we need to change the name of parameter, but this
breaks the external-facing python API used in configuration files. Using
this "type" for a parameter will warn users that they are using the old
name, but allow for backwards compatibility.
Declaring a SimObject parameter of type `DeprecatedParam` allows the
python configuration files to use the old name transparently. This
leverages some of the SimObject magic to remember the names of
deprecated parameters and the DeprecatedParam object stores the
"translation" from old name to new name.
This has been tested with Ports, "normal" parameters, and SimObject
parameters. It has not been tested with checkpointing as there are no
checkpointing tests in gem5 right now. The testing was manually adding
some deprecated params and checking that config scripts still run
correctly that use the old, deprecated, variables.
Change-Id: I0465a748c08a24278d6b1a9d9ee1bcd67baa5b13
Signed-off-by: Jason Lowe-Power
---
M src/python/m5/SimObject.py
M src/python/m5/params.py
2 files changed, 105 insertions(+), 1 deletion(-)
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 7f12856..159ab18 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -467,6 +467,12 @@
cls._params = multidict() # param descriptions
cls._ports = multidict() # port descriptions
+# Parameter names that are deprecated. Dict[str, DeprecatedParam]
+# The key is the "old_name" so that when the old_name is used in
+# python config files, we will use the DeprecatedParam object to
+# translate to the new type.
+cls._deprecated_params = multidict()
+
# class or instance attributes
cls._values = multidict() # param values
cls._hr_values = multidict() # human readable param values
@@ -532,6 +538,15 @@
elif isinstance(val, Port):
cls._new_port(key, val)
+# Deprecated variable names
+elif isinstance(val, DeprecatedParam):
+new_name, new_val = cls._get_param_by_value(val.newParam)
+# Note: We don't know the (string) name of this variable
until
+# here, so now we can finish setting up the dep_param.
+val.oldName = key
+val.newName = new_name
+cls._deprecated_params[key] = val
+
# init-time-only keywords
elif key in cls.init_keywords:
cls._set_keyword(key, val, cls.init_keywords[key])
@@ -604,6 +619,18 @@
cls._port_refs[attr] = ref
return ref
+def _get_param_by_value(cls, value):
+"""Given an object, value, return the name and the value from the
+internal list of parameter values. If this value can't be found,
raise
+a runtime error. This will search both the current object and its
+parents.
+"""
+for k,v in cls._value_dict.items():
+if v == value:
+return k,v
+raise RuntimeError("Cannot find parameter {} in parameter list"
+ .format(value))
+
# Set attribute (called on foo.attr = value when foo is an
# instance of class cls).
def __setattr__(cls, attr, value):
@@ -1255,6 +1282,11 @@
return ref
def __getattr__(self, attr):
+if attr in self._deprecated_params:
+dep_param = self._deprecated_params[attr]
+dep_param.printWarning(self._name, self.__class__.__name__)
+return getattr(self, self._deprecated_params[attr].newName)
+
if attr in self._ports:
return self._get_port_ref(attr)
@@ -1287,6 +1319,11 @@
object.__setattr__(self, attr, value)
return
+if attr in self._deprecated_params:
+dep_param = self._deprecated_params[attr]
+dep_param.printWarning(self._name, self.__class__.__name__)
+return setattr(self, self._deprecated_params[attr].newName,
value)
+
if attr in self._ports:
# set up port connection
self._get_port_ref(attr).connect(value)
diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 2ea614e..695604c 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -2162,6 +2162,71 @@
ptype_str = 'Port'
ptype = Port
+class DeprecatedParam(object):
+"""A special type for deprecated parameter variable names.
+
+There are times when we need to change the name of parameter, but this
+breaks the external-facing python API used in configuration files.
Using
+this "type" for a parameter will warn users that
[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Make Sp804 use the ArmInterruptPin
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31938 )
Change subject: dev-arm: Make Sp804 use the ArmInterruptPin
..
dev-arm: Make Sp804 use the ArmInterruptPin
Change-Id: I2d71c7e874ba1ec798e2314d7d282cb853b3f360
Signed-off-by: Giacomo Travaglini
---
M src/dev/arm/RealView.py
M src/dev/arm/timer_sp804.cc
M src/dev/arm/timer_sp804.hh
3 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index bb21dbc..f78b41e 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -388,10 +388,9 @@
class Sp804(AmbaPioDevice):
type = 'Sp804'
cxx_header = "dev/arm/timer_sp804.hh"
-gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
-int_num0 = Param.UInt32("Interrupt number that connects to GIC")
+int0 = Param.ArmSPI("Interrupt that connects to GIC")
clock0 = Param.Clock('1MHz', "Clock speed of the input")
-int_num1 = Param.UInt32("Interrupt number that connects to GIC")
+int1 = Param.ArmSPI("Interrupt that connects to GIC")
clock1 = Param.Clock('1MHz', "Clock speed of the input")
amba_id = 0x00141804
@@ -702,8 +701,10 @@
int_virt=ArmPPI(num=27),
int_hyp=ArmPPI(num=26))
-timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C11,
clock0='1MHz', clock1='1MHz')
-timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C12,
clock0='1MHz', clock1='1MHz')
+timer0 = Sp804(int0=ArmSPI(num=34), int1=ArmSPI(num=34),
+ pio_addr=0x1C11, clock0='1MHz', clock1='1MHz')
+timer1 = Sp804(int0=ArmSPI(num=35), int1=ArmSPI(num=35),
+ pio_addr=0x1C12, clock0='1MHz', clock1='1MHz')
clcd = Pl111(pio_addr=0x1c1f, interrupt=ArmSPI(num=46))
kmi0 = Pl050(pio_addr=0x1c06, interrupt=ArmSPI(num=44),
ps2=PS2Keyboard())
diff --git a/src/dev/arm/timer_sp804.cc b/src/dev/arm/timer_sp804.cc
index bf47e6d..dbfa7ff 100644
--- a/src/dev/arm/timer_sp804.cc
+++ b/src/dev/arm/timer_sp804.cc
@@ -46,14 +46,16 @@
#include "mem/packet_access.hh"
Sp804::Sp804(Params *p)
-: AmbaPioDevice(p, 0x1000), gic(p->gic),
- timer0(name() + ".timer0", this, p->int_num0, p->clock0),
- timer1(name() + ".timer1", this, p->int_num1, p->clock1)
+: AmbaPioDevice(p, 0x1000),
+ timer0(name() + ".timer0", this, p->int0->get(), p->clock0),
+ timer1(name() + ".timer1", this, p->int1->get(), p->clock1)
{
}
-Sp804::Timer::Timer(std::string __name, Sp804 *_parent, int int_num, Tick
_clock)
-: _name(__name), parent(_parent), intNum(int_num), clock(_clock),
control(0x20),
+Sp804::Timer::Timer(std::string __name, Sp804 *_parent,
+ArmInterruptPin *_interrupt, Tick _clock)
+: _name(__name), parent(_parent), interrupt(_interrupt),
+ clock(_clock), control(0x20),
rawInt(false), pendingInt(false), loadValue(0x),
zeroEvent([this]{ counterAtZero(); }, name())
{
@@ -158,7 +160,7 @@
if (pendingInt) {
pendingInt = false;
DPRINTF(Timer, "Clearing interrupt\n");
-parent->gic->clearInt(intNum);
+interrupt->clear();
}
break;
case BGLoad:
@@ -205,7 +207,7 @@
pendingInt = true;
if (pendingInt && !old_pending) {
DPRINTF(Timer, "-- Causing interrupt\n");
-parent->gic->sendInt(intNum);
+interrupt->raise();
}
if (control.oneShot)
diff --git a/src/dev/arm/timer_sp804.hh b/src/dev/arm/timer_sp804.hh
index ef586fc..1054b6a 100644
--- a/src/dev/arm/timer_sp804.hh
+++ b/src/dev/arm/timer_sp804.hh
@@ -80,8 +80,8 @@
/** Pointer to parent class */
Sp804 *parent;
-/** Number of interrupt to cause/clear */
-const uint32_t intNum;
+/** Pointer to the interrupt pin */
+ArmInterruptPin * const interrupt;
/** Number of ticks in a clock input */
const Tick clock;
@@ -109,7 +109,8 @@
* @param val the value to start at (pre-16 bit masking if en) */
void restartCounter(uint32_t val);
-Timer(std::string __name, Sp804 *parent, int int_num, Tick clock);
+Timer(std::string __name, Sp804 *parent, ArmInterruptPin
*_interrupt,
+ Tick clock);
std::string name() const { return _name; }
@@ -123,9 +124,6 @@
void unserialize(CheckpointIn ) override;
};
-/** Pointer to the GIC for causing an interrupt */
-BaseGic *gic;
-
/** Timers that do the actual work */
Timer timer0;
Timer timer1;
--
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Make the Sp805 use the new ArmInterruptPin::active
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31939 )
Change subject: dev-arm: Make the Sp805 use the new ArmInterruptPin::active
..
dev-arm: Make the Sp805 use the new ArmInterruptPin::active
Change-Id: I65b53b33e13345eca93a76e82efac7f8c0b97755
Signed-off-by: Giacomo Travaglini
---
M src/dev/arm/watchdog_sp805.cc
M src/dev/arm/watchdog_sp805.hh
2 files changed, 3 insertions(+), 11 deletions(-)
diff --git a/src/dev/arm/watchdog_sp805.cc b/src/dev/arm/watchdog_sp805.cc
index bed6258..3fd7006 100644
--- a/src/dev/arm/watchdog_sp805.cc
+++ b/src/dev/arm/watchdog_sp805.cc
@@ -49,7 +49,6 @@
persistedValue(timeoutInterval),
enabled(false),
resetEnabled(false),
- intRaised(false),
writeAccessEnabled(true),
integrationTestEnabled(false),
timeoutEvent([this] { timeoutExpired(); }, name())
@@ -78,10 +77,10 @@
warn("Sp805::read: WO reg (0x%x) [WDOGINTCLR]\n", addr);
break;
case WDOGRIS:
-resp = intRaised;
+resp = interrupt->active();
break;
case WDOGMIS:
-resp = intRaised & enabled;
+resp = interrupt->active() && enabled;
break;
case WDOGLOCK:
resp = writeAccessEnabled;
@@ -210,11 +209,10 @@
{
// If the previously sent interrupt has not been served,
// assert system reset if enabled
-if (intRaised & enabled) {
+if (interrupt->active() && enabled) {
if (resetEnabled)
warn("Watchdog timed out, system reset asserted\n");
} else {
-intRaised = true;
interrupt->raise();
}
}
@@ -222,7 +220,6 @@
void
Sp805::clearInt()
{
-intRaised = false;
interrupt->clear();
}
@@ -234,7 +231,6 @@
SERIALIZE_SCALAR(persistedValue);
SERIALIZE_SCALAR(enabled);
SERIALIZE_SCALAR(resetEnabled);
-SERIALIZE_SCALAR(intRaised);
SERIALIZE_SCALAR(writeAccessEnabled);
SERIALIZE_SCALAR(integrationTestEnabled);
@@ -252,7 +248,6 @@
UNSERIALIZE_SCALAR(persistedValue);
UNSERIALIZE_SCALAR(enabled);
UNSERIALIZE_SCALAR(resetEnabled);
-UNSERIALIZE_SCALAR(intRaised);
UNSERIALIZE_SCALAR(writeAccessEnabled);
UNSERIALIZE_SCALAR(integrationTestEnabled);
diff --git a/src/dev/arm/watchdog_sp805.hh b/src/dev/arm/watchdog_sp805.hh
index c2e99cd..4d9094d 100644
--- a/src/dev/arm/watchdog_sp805.hh
+++ b/src/dev/arm/watchdog_sp805.hh
@@ -93,9 +93,6 @@
/** Indicates if reset behaviour is enabled when counter reaches 0 */
bool resetEnabled;
-/** Indicates if an interrupt has been raised by the counter reaching
0 */
-bool intRaised;
-
/** Indicates if write access to registers is enabled */
bool writeAccessEnabled;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31939
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I65b53b33e13345eca93a76e82efac7f8c0b97755
Gerrit-Change-Number: 31939
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Make AmbaInt/DmaDevice use the ArmInterruptPin
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31936 )
Change subject: dev-arm: Make AmbaInt/DmaDevice use the ArmInterruptPin
..
dev-arm: Make AmbaInt/DmaDevice use the ArmInterruptPin
Change-Id: I7318b9186cd81f948211e8a955dab7eea6d2a2f5
Signed-off-by: Giacomo Travaglini
---
M src/dev/arm/RealView.py
M src/dev/arm/amba_device.cc
M src/dev/arm/amba_device.hh
M src/dev/arm/hdlcd.cc
M src/dev/arm/kmi.cc
M src/dev/arm/pl111.cc
M src/dev/arm/rtc_pl031.cc
M src/dev/arm/watchdog_sp805.cc
8 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index b0e8a8e..b3d7305 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -85,8 +85,7 @@
type = 'AmbaIntDevice'
abstract = True
cxx_header = "dev/arm/amba_device.hh"
-gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
-int_num = Param.UInt32("Interrupt number that connects to GIC")
+interrupt = Param.ArmInterruptPin("Interrupt that connects to GIC")
int_delay = Param.Latency("100ns",
"Time between action and interrupt generation by device")
@@ -96,8 +95,7 @@
cxx_header = "dev/arm/amba_device.hh"
pio_addr = Param.Addr("Address for AMBA slave interface")
pio_latency = Param.Latency("10ns", "Time between action and
write/read result by AMBA DMA Device")
-gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
-int_num = Param.UInt32("Interrupt number that connects to GIC")
+interrupt = Param.ArmInterruptPin("Interrupt that connects to GIC")
amba_id = Param.UInt32("ID of AMBA device for kernel detection")
class A9SCU(BasicPioDevice):
@@ -412,7 +410,7 @@
def generateDeviceTree(self, state):
node = self.generateBasicPioDeviceNode(state, 'watchdog',
-self.pio_addr, 0x1000, [int(self.int_num)])
+self.pio_addr, 0x1000, [int(self.interrupt.num)])
node.appendCompatible(['arm,sp805', 'arm,primecell'])
clocks = [state.phandle(self.clk_domain.unproxy(self))]
clock_names = ['wdogclk']
@@ -445,7 +443,7 @@
def generateDeviceTree(self, state):
node = self.generateBasicPioDeviceNode(state, 'rtc', self.pio_addr,
- 0x1000, [int(self.int_num)])
+0x1000, [int(self.interrupt.num)])
node.appendCompatible(["arm,pl031", "arm,primecell"])
clock = state.phandle(self.clk_domain.unproxy(self))
@@ -463,7 +461,7 @@
def generateDeviceTree(self, state):
node = self.generateBasicPioDeviceNode(state, 'kmi', self.pio_addr,
- 0x1000, [int(self.int_num)])
+0x1000, [int(self.interrupt.num)])
node.appendCompatible(["arm,pl050", "arm,primecell"])
clock = state.phandle(self.clk_domain.unproxy(self))
@@ -679,7 +677,7 @@
pio_addr=0x2C08)
hdlcd = HDLcd(pxl_clk=dcc.osc_pxl,
- pio_addr=0x2b00, int_num=117,
+ pio_addr=0x2b00, interrupt=ArmSPI(num=117),
workaround_swap_rb=True)
def _on_chip_devices(self):
@@ -712,9 +710,11 @@
timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C11,
clock0='1MHz', clock1='1MHz')
timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C12,
clock0='1MHz', clock1='1MHz')
-clcd = Pl111(pio_addr=0x1c1f, int_num=46)
-kmi0 = Pl050(pio_addr=0x1c06, int_num=44, ps2=PS2Keyboard())
-kmi1 = Pl050(pio_addr=0x1c07, int_num=45, ps2=PS2TouchKit())
+clcd = Pl111(pio_addr=0x1c1f, interrupt=ArmSPI(num=46))
+kmi0 = Pl050(pio_addr=0x1c06, interrupt=ArmSPI(num=44),
+ ps2=PS2Keyboard())
+kmi1 = Pl050(pio_addr=0x1c07, interrupt=ArmSPI(num=45),
+ ps2=PS2TouchKit())
cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
io_shift = 2, ctrl_offset = 2, Command = 0x1,
BAR0 = 0x1C1A, BAR0Size = '256B',
@@ -725,7 +725,7 @@
conf_table_reported = False)
vram = SimpleMemory(range = AddrRange(0x1800,
size='32MB'),
conf_table_reported = False)
-rtc= PL031(pio_addr=0x1C17, int_num=36)
+rtc= PL031(pio_addr=0x1C17, interrupt=ArmSPI(num=36))
l2x0_fake = IsaFake(pio_addr=0x2C10, pio_size=0xfff)
uart1_fake = AmbaFake(pio_addr=0x1C0A)
@@ -971,7 +971,7 @@
### On-chip devices ###
# Trusted Watchdog, SP805
-trusted_watchdog = Sp805(pio_addr=0x2a49, int_num=56)
+trusted_watchdog = Sp805(pio_addr=0x2a49, interrupt=ArmSPI(num=56))
sys_counter = SystemCounter()
generic_timer
[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Introduce the active boolean for ArmInterruptPin
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31934 )
Change subject: dev-arm: Introduce the active boolean for ArmInterruptPin
..
dev-arm: Introduce the active boolean for ArmInterruptPin
The active boolean will specify if the interrupt line is active
or not (high if it is active high or low if it is active low).
This is decoupled from the interrupt being in a pending state
within the GIC, and it can be used by a peripheral to query the
status of its interrupt pin
Change-Id: I18445b891a75767c8a72e9a7044d6d75fdb7e224
Signed-off-by: Giacomo Travaglini
---
M src/dev/arm/base_gic.cc
M src/dev/arm/base_gic.hh
2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/src/dev/arm/base_gic.cc b/src/dev/arm/base_gic.cc
index a2df8ab..3181dca 100644
--- a/src/dev/arm/base_gic.cc
+++ b/src/dev/arm/base_gic.cc
@@ -121,7 +121,7 @@
ArmInterruptPin::ArmInterruptPin(
Platform *_platform, ThreadContext *tc, uint32_t int_num)
: threadContext(tc), platform(dynamic_cast(_platform)),
-intNum(int_num)
+intNum(int_num), _active(false)
{
fatal_if(!platform, "Interrupt not connected to a RealView platform");
}
@@ -143,6 +143,18 @@
return threadContext->contextId();
}
+void
+ArmInterruptPin::serialize(CheckpointOut ) const
+{
+SERIALIZE_SCALAR(_active);
+}
+
+void
+ArmInterruptPin::unserialize(CheckpointIn )
+{
+UNSERIALIZE_SCALAR(_active);
+}
+
ArmSPI::ArmSPI(
Platform *_platform, uint32_t int_num)
: ArmInterruptPin(_platform, nullptr, int_num)
@@ -152,12 +164,14 @@
void
ArmSPI::raise()
{
+_active = true;
platform->gic->sendInt(intNum);
}
void
ArmSPI::clear()
{
+_active = false;
platform->gic->clearInt(intNum);
}
@@ -170,12 +184,14 @@
void
ArmPPI::raise()
{
+_active = true;
platform->gic->sendPPInt(intNum, targetContext());
}
void
ArmPPI::clear()
{
+_active = false;
platform->gic->clearPPInt(intNum, targetContext());
}
diff --git a/src/dev/arm/base_gic.hh b/src/dev/arm/base_gic.hh
index 2f4a1f6..f8fd814 100644
--- a/src/dev/arm/base_gic.hh
+++ b/src/dev/arm/base_gic.hh
@@ -173,7 +173,7 @@
/**
* Generic representation of an Arm interrupt pin.
*/
-class ArmInterruptPin
+class ArmInterruptPin : public Serializable
{
friend class ArmInterruptPinGen;
protected:
@@ -193,11 +193,18 @@
/** Get interrupt number */
uint32_t num() const { return intNum; }
+/** True if interrupt pin is active, false otherwise */
+bool active() const { return _active; }
+
/** Signal an interrupt */
virtual void raise() = 0;
/** Clear a signalled interrupt */
virtual void clear() = 0;
+ public: /* Serializable interface */
+void serialize(CheckpointOut ) const override;
+void unserialize(CheckpointIn ) override;
+
protected:
/**
* Get the target context ID of this interrupt.
@@ -218,6 +225,9 @@
/** Interrupt number to generate */
const uint32_t intNum;
+
+/** True if interrupt pin is active, false otherwise */
+bool _active;
};
class ArmSPI : public ArmInterruptPin
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I18445b891a75767c8a72e9a7044d6d75fdb7e224
Gerrit-Change-Number: 31934
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Remove the A9GlobalTimer
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31937 )
Change subject: dev-arm: Remove the A9GlobalTimer
..
dev-arm: Remove the A9GlobalTimer
This is not used anymore
Change-Id: Ia25921cfe47e7f6b895450031abb740f94dc032d
Signed-off-by: Giacomo Travaglini
---
M src/dev/arm/RealView.py
M src/dev/arm/SConscript
D src/dev/arm/timer_a9global.cc
D src/dev/arm/timer_a9global.hh
4 files changed, 0 insertions(+), 498 deletions(-)
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index b3d7305..bb21dbc 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -423,12 +423,6 @@
yield node
-class A9GlobalTimer(BasicPioDevice):
-type = 'A9GlobalTimer'
-cxx_header = "dev/arm/timer_a9global.hh"
-gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
-int_num = Param.UInt32("Interrrupt number that connects to GIC")
-
class CpuLocalTimer(BasicPioDevice):
type = 'CpuLocalTimer'
cxx_header = "dev/arm/timer_cpulocal.hh"
diff --git a/src/dev/arm/SConscript b/src/dev/arm/SConscript
index 7041bd9..37a8756 100644
--- a/src/dev/arm/SConscript
+++ b/src/dev/arm/SConscript
@@ -87,7 +87,6 @@
Source('realview.cc')
Source('rtc_pl031.cc')
Source('timer_cpulocal.cc')
-Source('timer_a9global.cc')
Source('vgic.cc')
Source('vio_mmio.cc')
Source('ufs_device.cc')
diff --git a/src/dev/arm/timer_a9global.cc b/src/dev/arm/timer_a9global.cc
deleted file mode 100644
index 9fea813..000
--- a/src/dev/arm/timer_a9global.cc
+++ /dev/null
@@ -1,316 +0,0 @@
-/*
- * Copyright (c) 2017 Gedare Bloom
- * Copyright (c) 2010 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "dev/arm/timer_a9global.hh"
-
-#include "base/intmath.hh"
-#include "base/trace.hh"
-#include "debug/Checkpoint.hh"
-#include "debug/Timer.hh"
-#include "dev/arm/base_gic.hh"
-#include "mem/packet.hh"
-#include "mem/packet_access.hh"
-
-A9GlobalTimer::A9GlobalTimer(Params *p)
-: BasicPioDevice(p, 0x1C), gic(p->gic),
- global_timer(name() + ".globaltimer", this, p->int_num)
-{
-}
-
-A9GlobalTimer::Timer::Timer(std::string __name, A9GlobalTimer *_parent,
-int int_num)
-: _name(__name), parent(_parent), intNum(int_num), control(0x0),
- rawInt(false), pendingInt(false), autoIncValue(0x0),
cmpValEvent(this)
-{
-}
-
-Tick
-A9GlobalTimer::read(PacketPtr pkt)
-{
-assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr +
pioSize);
-assert(pkt->getSize() == 4);
-Addr daddr = pkt->getAddr() - pioAddr;
-
-if (daddr < Timer::Size)
-global_timer.read(pkt, daddr);
-else
-panic("Tried to read A9GlobalTimer at offset %#x that doesn't
exist\n",
-daddr);
-pkt->makeAtomicResponse();
-return pioDelay;
-}
-
-uint64_t
[gem5-dev] Change in gem5/gem5[develop]: dev-arm: generateBasicPioDeviceNode requiring an ArmInterruptPin
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31941 )
Change subject: dev-arm: generateBasicPioDeviceNode requiring an
ArmInterruptPin
..
dev-arm: generateBasicPioDeviceNode requiring an ArmInterruptPin
Change-Id: I16ed3b689158defe2a43cccfa053d48dec4a1e41
Signed-off-by: Giacomo Travaglini
---
M src/dev/Device.py
M src/dev/arm/RealView.py
M src/dev/arm/VirtIOMMIO.py
3 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/src/dev/Device.py b/src/dev/Device.py
index d42541d..8950763 100644
--- a/src/dev/Device.py
+++ b/src/dev/Device.py
@@ -57,14 +57,14 @@
state.sizeCells(size) ))
if interrupts:
-if any([i < 32 for i in interrupts]):
+if any([i.num < 32 for i in interrupts]):
raise(("Interrupt number smaller than 32 "+
" in PioDevice %s") % name)
# subtracting 32 because Linux assumes that SPIs start at 0,
while
# gem5 uses the internal GIC numbering (SPIs start at 32)
node.append(FdtPropertyWords("interrupts", sum(
-[[0, i - 32, 4] for i in interrupts], []) ))
+[[0, i.num - 32, 4] for i in interrupts], []) ))
return node
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 54f864d..ff69ca2 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -373,7 +373,7 @@
def generateDeviceTree(self, state):
node = self.generateBasicPioDeviceNode(state, 'uart',
self.pio_addr,
-0x1000, [int(self.interrupt.num)])
+0x1000, [ self.interrupt ])
node.appendCompatible(["arm,pl011", "arm,primecell"])
# Hardcoded reference to the realview platform clocks, because the
@@ -409,7 +409,7 @@
def generateDeviceTree(self, state):
node = self.generateBasicPioDeviceNode(state, 'watchdog',
-self.pio_addr, 0x1000, [int(self.interrupt.num)])
+self.pio_addr, 0x1000, [ self.interrupt ])
node.appendCompatible(['arm,sp805', 'arm,primecell'])
clocks = [state.phandle(self.clk_domain.unproxy(self))]
clock_names = ['wdogclk']
@@ -436,7 +436,7 @@
def generateDeviceTree(self, state):
node = self.generateBasicPioDeviceNode(state, 'rtc', self.pio_addr,
-0x1000, [int(self.interrupt.num)])
+0x1000, [ self.interrupt ])
node.appendCompatible(["arm,pl031", "arm,primecell"])
clock = state.phandle(self.clk_domain.unproxy(self))
@@ -454,7 +454,7 @@
def generateDeviceTree(self, state):
node = self.generateBasicPioDeviceNode(state, 'kmi', self.pio_addr,
-0x1000, [int(self.interrupt.num)])
+0x1000, [ self.interrupt ])
node.appendCompatible(["arm,pl050", "arm,primecell"])
clock = state.phandle(self.clk_domain.unproxy(self))
@@ -517,7 +517,7 @@
port_node.append(endpoint_node)
node = self.generateBasicPioDeviceNode(state, 'hdlcd',
-self.pio_addr, 0x1000, [ self.interrupt.num ])
+self.pio_addr, 0x1000, [ self.interrupt ])
node.appendCompatible(["arm,hdlcd"])
node.append(FdtPropertyWords("clocks",
state.phandle(self.pxl_clk)))
diff --git a/src/dev/arm/VirtIOMMIO.py b/src/dev/arm/VirtIOMMIO.py
index 919755b..60aee16 100644
--- a/src/dev/arm/VirtIOMMIO.py
+++ b/src/dev/arm/VirtIOMMIO.py
@@ -54,8 +54,6 @@
def generateDeviceTree(self, state):
node = self.generateBasicPioDeviceNode(state, 'virtio',
self.pio_addr,
- int(self.pio_size), [
- int(self.interrupt.num),
- ])
+int(self.pio_size), [ self.interrupt ])
node.appendCompatible(["virtio,mmio"])
yield node
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I16ed3b689158defe2a43cccfa053d48dec4a1e41
Gerrit-Change-Number: 31941
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Fix DTB autogen for HDLcd
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31940 )
Change subject: dev-arm: Fix DTB autogen for HDLcd
..
dev-arm: Fix DTB autogen for HDLcd
The HDLcd was wrongly reporting the hardcoded IRQ=63 as the interrupt
number during DTB autogeneration. This is because the DTS is using 63.
However that corresponds to the SPI offset; the gem5 helper is
instead expecting the global IRQ number = 32 + SPI offset
Change-Id: I9e82360843eacb13cef5ddd2e28d2f3ef3147335
Signed-off-by: Giacomo Travaglini
---
M src/dev/arm/RealView.py
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index f78b41e..54f864d 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -516,9 +516,8 @@
port_node = FdtNode("port")
port_node.append(endpoint_node)
-# Interrupt number is hardcoded; it is not a property of this class
node = self.generateBasicPioDeviceNode(state, 'hdlcd',
- self.pio_addr, 0x1000, [63])
+self.pio_addr, 0x1000, [ self.interrupt.num ])
node.appendCompatible(["arm,hdlcd"])
node.append(FdtPropertyWords("clocks",
state.phandle(self.pxl_clk)))
--
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Gerrit-Change-Id: I9e82360843eacb13cef5ddd2e28d2f3ef3147335
Gerrit-Change-Number: 31940
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Make Pl011 UART use the ArmInterruptPin
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31935 )
Change subject: dev-arm: Make Pl011 UART use the ArmInterruptPin
..
dev-arm: Make Pl011 UART use the ArmInterruptPin
Change-Id: I995a424491f087b70b72d2558d96c7a472d4abaa
Signed-off-by: Giacomo Travaglini
---
M src/dev/arm/RealView.py
M src/dev/arm/pl011.cc
M src/dev/arm/pl011.hh
3 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index a22ac4a..b0e8a8e 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -369,14 +369,13 @@
class Pl011(Uart):
type = 'Pl011'
cxx_header = "dev/arm/pl011.hh"
-gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
-int_num = Param.UInt32("Interrupt number that connects to GIC")
+interrupt = Param.ArmInterruptPin("Interrupt that connects to GIC")
end_on_eot = Param.Bool(False, "End the simulation when a EOT is
received on the UART")
int_delay = Param.Latency("100ns", "Time between action and interrupt
generation by UART")
def generateDeviceTree(self, state):
node = self.generateBasicPioDeviceNode(state, 'uart',
self.pio_addr,
- 0x1000, [int(self.int_num)])
+0x1000, [int(self.interrupt.num)])
node.appendCompatible(["arm,pl011", "arm,primecell"])
# Hardcoded reference to the realview platform clocks, because the
@@ -700,7 +699,7 @@
return memories
### Off-chip devices ###
-uart = Pl011(pio_addr=0x1c09, int_num=37)
+uart = Pl011(pio_addr=0x1c09, interrupt=ArmSPI(num=37))
pci_host = GenericPciHost(
conf_base=0x3000, conf_size='256MB', conf_device_bits=16,
pci_pio_base=0)
@@ -1012,10 +1011,14 @@
clock24MHz = SrcClockDomain(clock="24MHz")
uart = [
-Pl011(pio_addr=0x1c09, int_num=37),
-Pl011(pio_addr=0x1c0a, int_num=38, device=Terminal()),
-Pl011(pio_addr=0x1c0b, int_num=39, device=Terminal()),
-Pl011(pio_addr=0x1c0c, int_num=40, device=Terminal())
+Pl011(pio_addr=0x1c09,
+interrupt=ArmSPI(num=37)),
+Pl011(pio_addr=0x1c0a,
+interrupt=ArmSPI(num=38), device=Terminal()),
+Pl011(pio_addr=0x1c0b,
+interrupt=ArmSPI(num=39), device=Terminal()),
+Pl011(pio_addr=0x1c0c,
+interrupt=ArmSPI(num=40), device=Terminal())
]
kmi0 = Pl050(pio_addr=0x1c06, int_num=44, ps2=PS2Keyboard())
diff --git a/src/dev/arm/pl011.cc b/src/dev/arm/pl011.cc
index f24cb61..11485b5 100755
--- a/src/dev/arm/pl011.cc
+++ b/src/dev/arm/pl011.cc
@@ -55,7 +55,7 @@
intEvent([this]{ generateInterrupt(); }, name()),
control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12),
imsc(0), rawInt(0),
- gic(p->gic), endOnEOT(p->end_on_eot), intNum(p->int_num),
+ endOnEOT(p->end_on_eot), interrupt(p->interrupt->get()),
intDelay(p->int_delay)
{
}
@@ -272,7 +272,7 @@
imsc, rawInt, maskInt());
if (maskInt()) {
-gic->sendInt(intNum);
+interrupt->raise();
DPRINTF(Uart, " -- Generated\n");
}
}
@@ -289,7 +289,7 @@
if (!intEvent.scheduled())
schedule(intEvent, curTick() + intDelay);
} else if (old_ints && !maskInt()) {
-gic->clearInt(intNum);
+interrupt->clear();
}
}
diff --git a/src/dev/arm/pl011.hh b/src/dev/arm/pl011.hh
index 81181b7..0ecbe13 100755
--- a/src/dev/arm/pl011.hh
+++ b/src/dev/arm/pl011.hh
@@ -171,14 +171,10 @@
uint16_t rawInt;
protected: // Configuration
-/** Gic to use for interrupting */
-BaseGic * const gic;
-
/** Should the simulation end on an EOT */
const bool endOnEOT;
-/** Interrupt number to generate */
-const int intNum;
+ArmInterruptPin* const interrupt;
/** Delay before interrupting */
const Tick intDelay;
--
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Gerrit-Change-Number: 31935
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Gerrit-Owner: Giacomo Travaglini
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Remove scs_prefix_appli_output binding.
Chris January has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31077 )
Change subject: fastmodel: Remove scs_prefix_appli_output binding.
..
fastmodel: Remove scs_prefix_appli_output binding.
The scx_prefix_appli_output function is removed in recent Fast Models
releases.
Change-Id: I324b911ec7ed68b7d0c324ac20a9795515e4de57
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31077
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/arm/fastmodel/fastmodel.cc
1 file changed, 12 insertions(+), 2 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/fastmodel.cc
b/src/arch/arm/fastmodel/fastmodel.cc
index 27a39fc..48a92b2 100644
--- a/src/arch/arm/fastmodel/fastmodel.cc
+++ b/src/arch/arm/fastmodel/fastmodel.cc
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright 2019 Google, Inc.
*
* Redistribution and use in source and binary forms, with or without
@@ -85,8 +97,6 @@
pybind11::arg("debug") = false)
.def("scx_enable_cadi_log", ::scx_enable_cadi_log,
pybind11::arg("log") = true)
-.def("scx_prefix_appli_output", ::scx_prefix_appli_output,
- pybind11::arg("prefix") = true)
.def("scx_print_port_number", ::scx_print_port_number,
pybind11::arg("print") = true)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31077
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Gerrit-Branch: develop
Gerrit-Change-Id: I324b911ec7ed68b7d0c324ac20a9795515e4de57
Gerrit-Change-Number: 31077
Gerrit-PatchSet: 5
Gerrit-Owner: Chris January
Gerrit-Reviewer: Chris January
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Fix hierachical Iris component names.
Chris January has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31076 )
Change subject: fastmodel: Fix hierachical Iris component names.
..
fastmodel: Fix hierachical Iris component names.
Recent releases of Fast Models structure Iris resources in a hierarchy.
Use the parent resource ID if set to construct the hierachical name of
components when constructing the resource map.
Change-Id: Iafafa26d5aff560c3b2e93894f81f770c0e98079
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31076
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/arm/fastmodel/iris/thread_context.cc
1 file changed, 27 insertions(+), 2 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc
b/src/arch/arm/fastmodel/iris/thread_context.cc
index a2cf2bf..070a386 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright 2019 Google, Inc.
*
* Redistribution and use in source and binary forms, with or without
@@ -204,9 +216,22 @@
std::vector resources;
call().resource_getList(_instId, resources);
+std::map
+idToResource;
+for (const auto : resources) {
+idToResource[resource.rscId] =
+}
ResourceMap resourceMap;
-for (auto : resources)
-resourceMap[resource.name] = resource;
+for (const auto : resources) {
+std::string name = resource.name;
+iris::ResourceId parentId = resource.parentRscId;
+while (parentId != iris::IRIS_UINT64_MAX) {
+const auto *parent = idToResource[parentId];
+name = parent->name + "." + name;
+parentId = parent->parentRscId;
+}
+resourceMap[name] = resource;
+}
initFromIrisInstance(resourceMap);
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Iafafa26d5aff560c3b2e93894f81f770c0e98079
Gerrit-Change-Number: 31076
Gerrit-PatchSet: 5
Gerrit-Owner: Chris January
Gerrit-Reviewer: Chris January
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Implement GIC DTB auto-generation.
Chris January has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31078 )
Change subject: fastmodel: Implement GIC DTB auto-generation.
..
fastmodel: Implement GIC DTB auto-generation.
Implement generateDeviceTree for FastModelGIC so the interrupt
controller is automatically added to the DTB. This is sufficient to
allow a VExpressFastmodel system model to boot Linux without an
explicit DTB.
Change-Id: I69d86fd8bba1b86768c8a118d2de079a56179854
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31078
Reviewed-by: Giacomo Travaglini
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/arm/fastmodel/GIC/FastModelGIC.py
1 file changed, 75 insertions(+), 0 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/GIC/FastModelGIC.py
b/src/arch/arm/fastmodel/GIC/FastModelGIC.py
index d682e85..0980cc4 100644
--- a/src/arch/arm/fastmodel/GIC/FastModelGIC.py
+++ b/src/arch/arm/fastmodel/GIC/FastModelGIC.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright 2019 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
@@ -24,6 +36,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.params import *
+from m5.util.fdthelper import *
from m5.SimObject import SimObject
from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
@@ -463,6 +476,9 @@
redistributor = VectorGicv3CommsInitiatorSocket(
'GIC communication initiator')
+# Used for DTB autogeneration
+_state = FdtState(addr_cells=2, size_cells=2, interrupt_cells=3)
+
def get_redist_bases(self):
"""
The format of reg_base_per_redistributor is
@@ -497,3 +513,62 @@
]
return ranges
+
+def interruptCells(self, int_type, int_num, int_flag):
+"""
+Interupt cells generation helper:
+Following specifications described in
+
+
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
+"""
+prop = self._state.interruptCells(0)
+assert len(prop) >= 3
+prop[0] = int_type
+prop[1] = int_num
+prop[2] = int_flag
+return prop
+
+def generateDeviceTree(self, state):
+sc_gic = self.sc_gic
+
+node = FdtNode("interrupt-controller")
+node.appendCompatible(["arm,gic-v3"])
+node.append(self._state.interruptCellsProperty())
+node.append(self._state.addrCellsProperty())
+node.append(self._state.sizeCellsProperty())
+node.append(FdtProperty("ranges"))
+node.append(FdtProperty("interrupt-controller"))
+
+redist_stride = 0x4 if sc_gic.has_gicv4_1 else 0x2
+node.append(FdtPropertyWords("redistributor-stride",
+state.sizeCells(redist_stride)))
+
+regs = (
+state.addrCells(sc_gic.reg_base) +
+state.sizeCells(0x1) +
+state.addrCells(self.get_redist_bases()[0]) +
+state.sizeCells(0x200) )
+
+node.append(FdtPropertyWords("reg", regs))
+# Maintenance interrupt (PPI 25).
+node.append(FdtPropertyWords("interrupts",
+self.interruptCells(1, 9, 0xf04)))
+
+node.appendPhandle(self)
+
+# Generate the ITS device tree
+its_frame_size = 0x1
+its_bases = [
+sc_gic.its0_base, sc_gic.its1_base, sc_gic.its2_base,
+sc_gic.its3_base
+]
+for its_base in its_bases:
+its_node = self.generateBasicPioDeviceNode(state, "gic-its",
+ its_base,
+ 2 * its_frame_size)
+its_node.appendCompatible(["arm,gic-v3-its"])
+its_node.append(FdtProperty("msi-controller"))
+its_node.append(FdtPropertyWords("#msi-cells", [1]))
+node.append(its_node)
+
+yield node
--
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: Add missing dependencies.
Chris January has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31075 )
Change subject: fastmodel: Add missing dependencies.
..
fastmodel: Add missing dependencies.
Add -latomic library required by recent Fast Models releases.
Add SystemCExport directory for tlm_has_get_protocol_types.h include.
Change-Id: Ia0c275d55f5077499588228737ed1ff5975cd5db
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31075
Tested-by: kokoro
Reviewed-by: Gabe Black
Maintainer: Gabe Black
---
M src/arch/arm/fastmodel/SConscript
1 file changed, 18 insertions(+), 7 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/SConscript
b/src/arch/arm/fastmodel/SConscript
index 2fd4ba0..c9b08b1 100644
--- a/src/arch/arm/fastmodel/SConscript
+++ b/src/arch/arm/fastmodel/SConscript
@@ -1,3 +1,15 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright 2019 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
@@ -114,6 +126,7 @@
'armctmodel',
'fmruntime',
'IrisSupport',
+'atomic',
'dl',
'rt',
)
@@ -374,10 +387,8 @@
Command(gic_protocol_dest.File(header), gic_protocol_src.File(header),
Copy('${TARGET}', '${SOURCE}'))
-lisa_protocol_types_header_path = 'include/lisa_protocol_types.h'
-lisa_protocol_types_header_target = \
-gic_protocol_dest.File(lisa_protocol_types_header_path)
-lisa_protocol_types_header_src = \
-examples_common_dir.File(lisa_protocol_types_header_path)
-Command(lisa_protocol_types_header_target, lisa_protocol_types_header_src,
-Copy('${TARGET}', '${SOURCE}'))
+common_headers = ('lisa_protocol_types.h', 'tlm_has_get_protocol_types.h')
+for header in common_headers:
+header_target = gic_protocol_dest.Dir('include').File(header)
+header_src = examples_common_dir.Dir('include').File(header)
+Command(header_target, header_src, Copy('${TARGET}', '${SOURCE}'))
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia0c275d55f5077499588228737ed1ff5975cd5db
Gerrit-Change-Number: 31075
Gerrit-PatchSet: 4
Gerrit-Owner: Chris January
Gerrit-Reviewer: Chris January
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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