[gem5-dev] Change in gem5/gem5[release-staging-v20.1.0.0]: tests,misc: Updated TestLib and boot-tests for gzipped imgs

2020-09-29 Thread Bobby R. Bruce (Gerrit) via gem5-dev 
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35257 )


Change subject: tests,misc: Updated TestLib and boot-tests for gzipped imgs
..

tests,misc: Updated TestLib and boot-tests for gzipped imgs

In efforts to reduce storage costs and download times, the images hosted
by us have been gzipped. The TestLib framework has therefore been
extended to decompress gzipped files after download.

The x86-boot-tests are, at present, the only tests which use the gem5
images. These tests have been updated to download the gzipped image.

Change-Id: I6b2dbe9472a604148834820db8ea70e91e94376f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35257
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M tests/gem5/fixture.py
M tests/gem5/x86-boot-tests/test_linux_boot.py
2 files changed, 20 insertions(+), 5 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/gem5/fixture.py b/tests/gem5/fixture.py
index bb911dd..e21cb88 100644
--- a/tests/gem5/fixture.py
+++ b/tests/gem5/fixture.py
@@ -42,6 +42,7 @@
 import sys
 import socket
 import threading
+import gzip

 from six.moves import urllib

@@ -260,11 +261,11 @@
 and downloads an updated version if it is needed.
 """

-def __new__(cls, url, path, filename):
+def __new__(cls, url, path, filename, gzip_decompress=False):
 target = joinpath(path, filename)
 return super(DownloadedProgram, cls).__new__(cls, target)

-def _init(self, url, path, filename, **kwargs):
+def _init(self, url, path, filename, gzip_decompress=False, **kwargs):
 """
 url: string
 The url of the archive
@@ -272,12 +273,16 @@
 The absolute path of the directory containing the archive
 filename: string
 The name of the archive
+gzip_decompress: boolean
+True if this target resource have been compressed using gzip  
and

+is to be decompressed prior to usage.
 """

 self.url = url
 self.path = path
 self.filename = joinpath(path, filename)
 self.name = "Downloaded:" + self.filename
+self.gzip_decompress = gzip_decompress

 def _download(self):
 import errno
@@ -288,7 +293,17 @@
 except OSError as e:
 if e.errno != errno.EEXIST:
 raise
-urllib.request.urlretrieve(self.url, self.filename)
+if self.gzip_decompress:
+gzipped_filename = self.filename + ".gz"
+urllib.request.urlretrieve(self.url, gzipped_filename)
+
+with open(self.filename, 'w') as outfile:
+with gzip.open(gzipped_filename, 'r') as infile:
+shutil.copyfileobj(infile, outfile)
+
+os.remove(gzipped_filename)
+else:
+urllib.request.urlretrieve(self.url, self.filename)

 def _getremotetime(self):
 import datetime, time
diff --git a/tests/gem5/x86-boot-tests/test_linux_boot.py  
b/tests/gem5/x86-boot-tests/test_linux_boot.py

index 0e66659..d73f3a1 100644
--- a/tests/gem5/x86-boot-tests/test_linux_boot.py
+++ b/tests/gem5/x86-boot-tests/test_linux_boot.py
@@ -34,13 +34,13 @@
 base_path = joinpath(absdirpath(__file__), '..', 'resources',
 'ubuntu-boot')

-image_url = config.resource_url + '/images/x86/ubuntu-18-04/base.img'
+image_url = config.resource_url + '/images/x86/ubuntu-18-04/base.img.gz'
 kernel_url = config.resource_url + '/kernels/x86/static/vmlinux-4.19.83'

 image_name = 'ubuntu-18-04-base.img'
 kernel_name = 'vmlinux-4.19.83' # 4.19 is LTS (Projected EOL: Dec, 2020)

-image = DownloadedProgram(image_url, base_path, image_name)
+image = DownloadedProgram(image_url, base_path, image_name, True)
 kernel = DownloadedProgram(kernel_url, base_path, kernel_name)



--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35257
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.1.0.0
Gerrit-Change-Id: I6b2dbe9472a604148834820db8ea70e91e94376f
Gerrit-Change-Number: 35257
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] gem5-20.1 release imminent

2020-09-29 Thread Jason Lowe-Power via gem5-dev 
Hi all,

We're planning on making the gem5-20.1 release official tomorrow. Please
let us know if there's any last minute blocking issues. There are a couple
of small things we're still waiting on, but we're confident they'll be
resolved by tomorrow morning (US west coast time).

In the meantime, let me know if you have any comments on the release notes
here: https://gem5-review.googlesource.com/c/public/gem5/+/35375

Thanks to everyone for making this another successful release!

Cheers,
Jason
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[release-staging-v20.1.0.0]: misc: Add release notes for 20.1

2020-09-29 Thread Jason Lowe-Power (Gerrit) via gem5-dev 
Jason Lowe-Power has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35375 )



Change subject: misc: Add release notes for 20.1
..

misc: Add release notes for 20.1

Change-Id: I011ff987e222326dd7f0787c41043578b52b236a
Signed-off-by: Jason Lowe-Power 
---
M RELEASE-NOTES.md
1 file changed, 115 insertions(+), 1 deletion(-)



diff --git a/RELEASE-NOTES.md b/RELEASE-NOTES.md
index 1a97b4c..5525972 100644
--- a/RELEASE-NOTES.md
+++ b/RELEASE-NOTES.md
@@ -1,6 +1,120 @@
 # Version 20.1.0.0

-* m5.stats.dump() root argument renamed to roots to reflect the fact that  
it now takes a list of SimObjects

+Thank you to everyone that made this release possible!
+This has been a very productive release with [150  
issues](https://gem5.atlassian.net/), over 650  commits (a 25% increase  
from the 20.0 release), and 58 unique contributors (a 100% increase!).

+
+## Process changes
+
+We are no longer using the "master" branch.
+Instead, we will have two branches:
+
+* "stable": This will point to the latest stable release (gem5-20.1 as of  
today)
+* "develop": This is the latest development code that will be merged in to  
the "stable" branch at each release.

+
+We suggest all *users* use the stable (default) branch.
+However, to contribute your fixes and new changes to gem5, it should be  
contributed to the develop branch.

+See CONTRIBUTING.md for more details.
+
+## New features in 20.1
+
+### New DRAM interface: Contributed by *Wendy Elsasser*
+
+You can find details about this on the [gem5  
blog](http://www.gem5.org/2020/05/27/memory-controller.html) or Wendy's  
talks on YouTube: [Talk on new interface and  
NVM](https://www.youtube.com/watch?v=t2PRoZPwwpk) and the [talk on  
LPDDR5](https://www.youtube.com/watch?v=ttJ9_I_Avyc)

+
+* **[PYTHON API CHANGE]**: The DRAM models are now *DRAM interfaces* which  
is a child of the *memory controller*. Example change shown [in the blog  
post](http://www.gem5.org/project/2020/07/18/gem5-20-1.html).

+  * The DRAM is split into a memory controller and a DRAM interface
+  * `SimpleMemory` is no longer a drop-in replacement for a DRAM-based  
memory controller.

+* LPDDR5 model added
+* NVM model added
+* New memory controller model that can use both NVM and DRAM
+
+### Improved on-chip interconnect model, HeteroGarnet: Contributed by  
*Srikant Bharadwaj*

+
+You can find details about this on the [gem5  
blog](http://www.gem5.org/2020/05/27/heterogarnet.html) and [Srikant's talk  
on YouTube](https://www.youtube.com/watch?v=AH9r44r2lHA).

+
+* **[USER-FACING CHANGE]**: The network type options are now "simple"  
and "garnet" instead of "garnet2.0". (If "garnet2.0" is used, you will get  
a warning until gem5-20.2)
+* Added models for clock domain crossings and  
serialization/deserialization (SERDES)

+
+### Transactional memory support: Contributed by *Timothy Hayes*
+
+You can find details on the [Jira  
issue](https://gem5.atlassian.net/browse/GEM5-587)

+
+* gem5 now supports Arm TME (transactional memory extensions)
+* Transactional memory is only implemented in the `MESI_Three_Level_HTM`  
Ruby protocol, and it is only implemented in Ruby.
+* This implements a checkpointing mechanism for the architectural state  
and buffering of speculative memory updates.

+* IBM POWER and x86 HTM extensions have *not* been implemented.
+
+### Other new features
+
+* External simulator integrations
+  * Added support for DRAMSim3
+  * Added back support for DRAMSim2
+* Armv8-A Self Hosted Debug extension added
+* KVM support for Armv8 hosts without GICv2 hardware
+* Implemented Secure EL2 for ARMv8
+
+## Removed features
+
+* Dropped support for mercurial version control
+
+## New supported platforms
+
+* GCC up to 10.2 is now supported. Minimum GCC is now 5.0.
+* Clang up to version 9. Minimum Clang is now 3.9.
+
+## Platforms no longer support
+
+* **[USER-FACING CHANGE]**: Python 2 is officially deprecated. We will  
drop support for Python 2 in the next release. In this release you will get  
a warning if you're using Python 2.

+* **[USER-FACING CHANGE]**: We have dropped support for GCC 4.X
+* **[USER-FACING CHANGE]**: We have dropped support for Scons 2.x (Note:  
this is the default in Ubuntu 16.04. Use pip to install a newer scons.)

+
+See  for gem5's  
current dependencies.

+
+## Other changes
+
+### Deprecating "master" and "slave"
+
+* **[API CHANGE]**: The names "master" and "slave" have been deprecated
+  * Special thanks to Lakin Smith, Shivani Parekh, Eden Avivi, and Emily  
Brickey.

+  * Below is a guide to most of the name changes.
+  * The goal was to replace problematic language with more descriptive and  
precise terms.
+* There may be some bugs introduced with this change as there were many  
places in the Python configurations which relied on "duck typing".
+* This change is mostly back

[gem5-dev] Change in gem5/gem5[develop]: arch: Wrap a docstring in isa_parser.py.

2020-09-29 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35276 )


Change subject: arch: Wrap a docstring in isa_parser.py.
..

arch: Wrap a docstring in isa_parser.py.

This brings the ISA parser in line with the style guide. Note that the
docstring needs to be a single string literal for python to consider it
a docstring, and the parser itself needs each line of the docstring to
be a rule in its CFG. We can accomplish both by taking advantage of the
fact that two directly adjacent quoted strings are treated as a single
string literal by python, and by escaping the newline so that they're
actually considered adjacent.

Change-Id: I7f4d252998877808425aafb0159600ba4c3bf9ad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35276
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/isa_parser.py
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index d69bea2..4f69a3f 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -2082,7 +2082,8 @@
 # 'def [signed] bitfield  [:]'
 # This generates a preprocessor macro in the output file.
 def p_def_bitfield_0(self, t):
-'def_bitfield : DEF opt_signed BITFIELD ID LESS INTLIT COLON  
INTLIT GREATER SEMI'

+'def_bitfield : DEF opt_signed ' \
+'BITFIELD ID LESS INTLIT COLON INTLIT GREATER SEMI'
 expr = 'bits(machInst, %2d, %2d)' % (t[6], t[8])
 if (t[2] == 'signed'):
 expr = 'sext<%d>(%s)' % (t[6] - t[8] + 1, expr)

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35276
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7f4d252998877808425aafb0159600ba4c3bf9ad
Gerrit-Change-Number: 35276
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Steve Reinhardt 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: base: Expose the ObjectFile class to python.

2020-09-29 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/33899 )


Change subject: base: Expose the ObjectFile class to python.
..

base: Expose the ObjectFile class to python.

This will make it possible to inspect a binary and determine, for
example, what architecture or operating system it was compiled for.

Change-Id: Ib40f1e1c02448dc5bf084bb0dd98d3767f463fef
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33899
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/base/loader/object_file.cc
M src/base/loader/object_file.hh
M src/python/SConscript
A src/python/pybind11/object_file.cc
4 files changed, 116 insertions(+), 0 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/loader/object_file.cc b/src/base/loader/object_file.cc
index 12e5606..6fdf228 100644
--- a/src/base/loader/object_file.cc
+++ b/src/base/loader/object_file.cc
@@ -38,6 +38,60 @@

 ObjectFile::ObjectFile(ImageFileDataPtr ifd) : ImageFile(ifd) {}

+const char *
+archToString(Arch arch)
+{
+switch (arch) {
+  case UnknownArch:
+return "unknown";
+  case SPARC64:
+return "sparc64";
+  case SPARC32:
+return "sparc32";
+  case Mips:
+return "mips";
+  case X86_64:
+return "x86_64";
+  case I386:
+return "i386";
+  case Arm64:
+return "arm64";
+  case Arm:
+return "arm";
+  case Thumb:
+return "thumb";
+  case Power:
+return "power";
+  case Riscv64:
+return "riscv64";
+  case Riscv32:
+return "riscv32";
+  default:
+panic("Unrecognized arch %d.", arch);
+}
+}
+
+const char *
+opSysToString(OpSys op_sys)
+{
+switch (op_sys) {
+  case UnknownOpSys:
+return "unknown";
+  case Tru64:
+return "tru64";
+  case Linux:
+return "linux";
+  case Solaris:
+return "solaris";
+  case LinuxArmOABI:
+return "linux_arm_OABI";
+  case FreeBSD:
+return "freebsd";
+  default:
+panic("Unrecognized operating system %d.", op_sys);
+}
+}
+
 namespace
 {

diff --git a/src/base/loader/object_file.hh b/src/base/loader/object_file.hh
index 9ff9997..0bfd918 100644
--- a/src/base/loader/object_file.hh
+++ b/src/base/loader/object_file.hh
@@ -56,6 +56,8 @@
 Riscv32
 };

+const char *archToString(Arch arch);
+
 enum OpSys {
 UnknownOpSys,
 Tru64,
@@ -65,6 +67,8 @@
 FreeBSD
 };

+const char *opSysToString(OpSys op_sys);
+
 class SymbolTable;

 class ObjectFile : public ImageFile
diff --git a/src/python/SConscript b/src/python/SConscript
index cf52ee1..50f467e 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -69,4 +69,5 @@
 Source('pybind11/core.cc', add_tags='python')
 Source('pybind11/debug.cc', add_tags='python')
 Source('pybind11/event.cc', add_tags='python')
+Source('pybind11/object_file.cc', add_tags='python')
 Source('pybind11/stats.cc', add_tags='python')
diff --git a/src/python/pybind11/object_file.cc  
b/src/python/pybind11/object_file.cc

new file mode 100644
index 000..2ad5598
--- /dev/null
+++ b/src/python/pybind11/object_file.cc
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2020 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "base/loader/object_file.hh"
+#include "py

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: SMMUv3, default CMDQ entries to 128

2020-09-29 Thread Adrian Herrera (Gerrit) via gem5-dev 
Adrian Herrera has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35297 )


Change subject: dev-arm: SMMUv3, default CMDQ entries to 128
..

dev-arm: SMMUv3, default CMDQ entries to 128

From Linux 587e6c10a7ce89a5924fdbeff2ec524fbd6a124b, SMMUv3
implementations in 64-bit platforms must report a minimum of 128 CMDQ
entries via SMMU_IDR1. Otherwise, the SMMUv3 Linux driver returns -ENXIO.

Change-Id: I304aac1b734515b3077003e8d67cc19730afc67f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35297
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/dev/arm/SMMUv3.py
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py
index 29c1568..f53b8ec 100644
--- a/src/dev/arm/SMMUv3.py
+++ b/src/dev/arm/SMMUv3.py
@@ -162,9 +162,9 @@
 # [0] S2P = 0b1, Stage 2 translation supported.
 smmu_idr0 = Param.UInt32(0x094C100F, "SMMU_IDR0 register");

-# [25:21] CMDQS = 0b00101, Maximum number of Command queue entries
-# as log 2 (entries) (0b00101 = 32 entries).
-smmu_idr1 = Param.UInt32(0x00A0, "SMMU_IDR1 register");
+# [25:21] CMDQS = 0b00111, Maximum number of Command queue entries
+# as log 2 (entries) (0b00111 = 128 entries).
+smmu_idr1 = Param.UInt32(0x00E0, "SMMU_IDR1 register");

 smmu_idr2 = Param.UInt32(0, "SMMU_IDR2 register");
 smmu_idr3 = Param.UInt32(0, "SMMU_IDR3 register");

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35297
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I304aac1b734515b3077003e8d67cc19730afc67f
Gerrit-Change-Number: 35297
Gerrit-PatchSet: 2
Gerrit-Owner: Adrian Herrera 
Gerrit-Reviewer: Adrian Herrera 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[release-staging-v20.1.0.0]: scons,python: Add python2-config to PYTHON_CONFIG

2020-09-29 Thread Bobby R. Bruce (Gerrit) via gem5-dev 
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35255 )


Change subject: scons,python: Add python2-config to PYTHON_CONFIG
..

scons,python: Add python2-config to PYTHON_CONFIG

PYTHON_CONFIG can be python2-config as well as python2.7-config.

Change-Id: I482cb922fcf26b37f67f2aca392e04968ca144bd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35255
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M SConstruct
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index 316c10b..667a0e6 100755
--- a/SConstruct
+++ b/SConstruct
@@ -238,7 +238,8 @@
 ('MARSHAL_CCFLAGS_EXTRA', 'Extra C and C++ marshal compiler  
flags', ''),

 ('MARSHAL_LDFLAGS_EXTRA', 'Extra marshal linker flags', ''),
 ('PYTHON_CONFIG', 'Python config binary to use',
- [ 'python3-config', 'python-config', 'python2.7-config' ]),
+  
[ 'python3-config', 'python-config', 'python2.7-config', 'python2-config']

+),
 ('PROTOC', 'protoc tool', environ.get('PROTOC', 'protoc')),
 ('BATCH', 'Use batch pool for build and tests', False),
 ('BATCH_CMD', 'Batch pool submission command name', 'qdo'),

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35255
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.1.0.0
Gerrit-Change-Id: I482cb922fcf26b37f67f2aca392e04968ca144bd
Gerrit-Change-Number: 35255
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[release-staging-v20.1.0.0]: python: Flush the simulation stdout/stderr buffers

2020-09-29 Thread Bobby R. Bruce (Gerrit) via gem5-dev 
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34995 )


Change subject: python: Flush the simulation stdout/stderr buffers
..

python: Flush the simulation stdout/stderr buffers

Occasionally gem5's stdout/stderr, when run within the TestLib
framework, will be shuffled. This is resolved by flushing the
stdout/stderr buffer before and after simulation.

In addition to this, the verifier.py has been improved to remove
boilerplate gem5 code from the stdout comparison.

Change-Id: I04c8f9cee4475b8eab2f1ba9bb76bfa3cfcca6ec
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34995
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Jason Lowe-Power 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/python/m5/simulate.py
M tests/gem5/cpu_tests/ref/Bubblesort
M tests/gem5/cpu_tests/ref/FloatMM
M tests/gem5/dram-lowp/ref/simout
M tests/gem5/hello_se/ref/simout
M tests/gem5/insttest_se/ref/sparc/linux/insttest/simout
M tests/gem5/learning_gem5/ref/hello
M tests/gem5/learning_gem5/ref/hello_goodbye
M tests/gem5/learning_gem5/ref/simple
M tests/gem5/learning_gem5/ref/test
M tests/gem5/learning_gem5/ref/threads
M tests/gem5/m5threads_test_atomic/ref/sparc64/simout
M tests/gem5/verifier.py
13 files changed, 12 insertions(+), 45 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/python/m5/simulate.py b/src/python/m5/simulate.py
index 698dfbc..080d725 100644
--- a/src/python/m5/simulate.py
+++ b/src/python/m5/simulate.py
@@ -175,7 +175,15 @@
 if _drain_manager.isDrained():
 _drain_manager.resume()

-return _m5.event.simulate(*args, **kwargs)
+# We flush stdout and stderr before and after the simulation to ensure  
the

+# output arrive in order.
+sys.stdout.flush()
+sys.stderr.flush()
+sim_out = _m5.event.simulate(*args, **kwargs)
+sys.stdout.flush()
+sys.stderr.flush()
+
+return sim_out

 def drain():
 """Drain the simulator in preparation of a checkpoint or memory mode
diff --git a/tests/gem5/cpu_tests/ref/Bubblesort  
b/tests/gem5/cpu_tests/ref/Bubblesort

index 79d2ae3..76f4de0 100644
--- a/tests/gem5/cpu_tests/ref/Bubblesort
+++ b/tests/gem5/cpu_tests/ref/Bubblesort
@@ -1,6 +1,2 @@
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-
 Global frequency set at 1 ticks per second
 -5
diff --git a/tests/gem5/cpu_tests/ref/FloatMM  
b/tests/gem5/cpu_tests/ref/FloatMM

index 6539627..0f1d582 100644
--- a/tests/gem5/cpu_tests/ref/FloatMM
+++ b/tests/gem5/cpu_tests/ref/FloatMM
@@ -1,6 +1,2 @@
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-
 Global frequency set at 1 ticks per second
 -776.61
diff --git a/tests/gem5/dram-lowp/ref/simout  
b/tests/gem5/dram-lowp/ref/simout

index 5128ab4..6fdcf85 100644
--- a/tests/gem5/dram-lowp/ref/simout
+++ b/tests/gem5/dram-lowp/ref/simout
@@ -1,7 +1,3 @@
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-
 Global frequency set at 1 ticks per second
 --- Done DRAM low power sweep ---
 Fixed params -
diff --git a/tests/gem5/hello_se/ref/simout b/tests/gem5/hello_se/ref/simout
index a38e288..9e8cf27 100644
--- a/tests/gem5/hello_se/ref/simout
+++ b/tests/gem5/hello_se/ref/simout
@@ -1,7 +1,3 @@
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-
 Global frequency set at 1 ticks per second
  REAL SIMULATION 
 Hello world!
diff --git a/tests/gem5/insttest_se/ref/sparc/linux/insttest/simout  
b/tests/gem5/insttest_se/ref/sparc/linux/insttest/simout

index 4665746..81a0b92 100644
--- a/tests/gem5/insttest_se/ref/sparc/linux/insttest/simout
+++ b/tests/gem5/insttest_se/ref/sparc/linux/insttest/simout
@@ -1,7 +1,3 @@
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-
 Global frequency set at 1 ticks per second
  REAL SIMULATION 
 Begining test of difficult SPARC instructions...
diff --git a/tests/gem5/learning_gem5/ref/hello  
b/tests/gem5/learning_gem5/ref/hello

index 0f0a7d6..bcdd7b9 100644
--- a/tests/gem5/learning_gem5/ref/hello
+++ b/tests/gem5/learning_gem5/ref/hello
@@ -1,7 +1,3 @@
-gem5 Simulator System.  http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-
 Global frequency set at 1 ticks per second
 Beginning simulation!
 Hello world!
diff --git a/tests/gem5/learning_gem5/ref/hello_goodbye  
b/tests/gem5/learning_gem5/ref/hello_goodbye

index 8e80377..cda

[gem5-dev] Change in gem5/gem5[release-staging-v20.1.0.0]: scons,python: Prioritize Python3 for PYTHON_CONFIG

2020-09-29 Thread Bobby R. Bruce (Gerrit) via gem5-dev 
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34899 )


Change subject: scons,python: Prioritize Python3 for PYTHON_CONFIG
..

scons,python: Prioritize Python3 for PYTHON_CONFIG

Change-Id: I0ac4d90b93f2e0a9384216f759937f7b0aa23d41
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34899
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M SConstruct
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index ca3f1a1..316c10b 100755
--- a/SConstruct
+++ b/SConstruct
@@ -238,7 +238,7 @@
 ('MARSHAL_CCFLAGS_EXTRA', 'Extra C and C++ marshal compiler  
flags', ''),

 ('MARSHAL_LDFLAGS_EXTRA', 'Extra marshal linker flags', ''),
 ('PYTHON_CONFIG', 'Python config binary to use',
- [ 'python2.7-config', 'python-config', 'python3-config' ]),
+ [ 'python3-config', 'python-config', 'python2.7-config' ]),
 ('PROTOC', 'protoc tool', environ.get('PROTOC', 'protoc')),
 ('BATCH', 'Use batch pool for build and tests', False),
 ('BATCH_CMD', 'Batch pool submission command name', 'qdo'),

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34899
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.1.0.0
Gerrit-Change-Id: I0ac4d90b93f2e0a9384216f759937f7b0aa23d41
Gerrit-Change-Number: 34899
Gerrit-PatchSet: 4
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[release-staging-v20.1.0.0]: scons,python: Add warning for when python3-config is not used

2020-09-29 Thread Bobby R. Bruce (Gerrit) via gem5-dev 
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35256 )


Change subject: scons,python: Add warning for when python3-config is not  
used

..

scons,python: Add warning for when python3-config is not used

We cannot say for certain whether 'python-config' is python2 or python3,
but this patch will produce a warning if 'python3-config' is not used,
stating that support for python2 will be dropped in future releases of
gem5.

Change-Id: I114da359c8768071bf7dd7f2701aae85e3459678
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35256
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Jason Lowe-Power 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M SConstruct
1 file changed, 4 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/SConstruct b/SConstruct
index 667a0e6..621f923 100755
--- a/SConstruct
+++ b/SConstruct
@@ -637,6 +637,10 @@
   main['PYTHON_CONFIG'])

 print("Info: Using Python config: %s" % (python_config, ))
+if python_config != 'python3-config':
+warning('python3-config could not be found.\n'
+'Future releases of gem5 will drop support for python2.')
+
 py_includes = readCommand([python_config, '--includes'],
   exception='').split()
 py_includes = list(filter(

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35256
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.1.0.0
Gerrit-Change-Id: I114da359c8768071bf7dd7f2701aae85e3459678
Gerrit-Change-Number: 35256
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[release-staging-v20.1.0.0]: tests: Removing gem5/hello_se/ref/simerr

2020-09-29 Thread Bobby R. Bruce (Gerrit) via gem5-dev 
Bobby R. Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/34996 )


Change subject: tests: Removing gem5/hello_se/ref/simerr
..

tests: Removing gem5/hello_se/ref/simerr

This is not needed in any comparison we make. It was probably added in
error.

Change-Id: Ie771654f73d101d0ef90ca6e2864a7cb684b3919
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34996
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
D tests/gem5/hello_se/ref/simerr
1 file changed, 0 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/tests/gem5/hello_se/ref/simerr b/tests/gem5/hello_se/ref/simerr
deleted file mode 100644
index e69de29..000
--- a/tests/gem5/hello_se/ref/simerr
+++ /dev/null

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/34996
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.1.0.0
Gerrit-Change-Id: Ie771654f73d101d0ef90ca6e2864a7cb684b3919
Gerrit-Change-Number: 34996
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby R. Bruce 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Re: MMU object vs. DTB and ITB

2020-09-29 Thread Jason Lowe-Power via gem5-dev 
Hey Giacomo,

Thanks for the patches! I think this is moving in the right direction. It
looks like the C++ interface is getting much better, though there are still
a few places to improve :).

However, I think we need to reconsider the python interface at this time
too. Right now, we have the following "dependencies".

To hook up the memory system, you have to know details about the internal
CPU implementation. This in turn depends on the MMU implementation. This in
turn depends on the TLB implementation. This in turn depends on the walker
implementation (which also depends on the ISA!).

To create a CPU correctly, the CPU also depends on the memory system (i.e.,
classic caches use "cpu_side" whereas Ruby (now) uses "in_port"). This also
means that the transitive dependency described above also depends on the
memory system implementation. (There's also the dependence on "cached" vs
"uncached" ports in the CPU too... But I think this is a different issue.)

These circular dependencies are not great.

I think we should talk about which way we want the dependencies to flow,
and then hide the implementation behind functions. By defining some
functions in the Python SimObject description files, we can hide the
implementation details (e.g., that an MMU has two child SimObjects called
itb and dtb). In doing this, we can have *well defined* interfaces/APIs for
the Python SimObjects instead of the mess of "duck typing" that we have
right now.

Given all of the changes in
https://gem5-review.googlesource.com/c/public/gem5/+/34976 to the config
files, I would prefer to hash this out before these changes go in, but I
would also be open to waiting and going through some pain on the develop
branch. However, if we're going to do this TLB refactor now, I think it's a
requirement to also refactor the python interface before the 20.2 release.

Cheers,
Jason

On Tue, Sep 22, 2020 at 8:48 AM Giacomo Travaglini <
giacomo.travagl...@arm.com> wrote:

> Hey Jason,
>
>
>
> I have just posted the patchset:
>
>
>
> https://gem5-review.googlesource.com/c/public/gem5/+/34975/1
>
>
>
> Supporting a multi-level TLB design was actually the reason why I started
> implementing this.
>
> I am not at that point yet, but I believe we are getting closer now,
> having a MMU hiding the TLB hierarchy to the rest of the cpu code.
>
> The remaining thing after this patches would be to move most TLB methods
> to the MMU class and to make the TLB a simple passive translation cache.
> That will allow us to stack them in any way we want
>
>
>
> Giacomo
>
>
>
> *From:* Jason Lowe-Power via gem5-dev 
> *Sent:* 21 September 2020 16:02
> *To:* gem5 Developer List 
> *Cc:* Jason Lowe-Power 
> *Subject:* [gem5-dev] Re: MMU object vs. DTB and ITB
>
>
>
> We (well, mostly Ayaz) have also been looking at this interface. We've
> been thinking more about x86 and RISC-V, but would also like to be kept up
> to date!
>
>
>
> We were also thinking that many of the TLB/MMU concepts are shared between
> ISAs (or are microarchitecture details). So, it would be nice to be able to
> use the same multi-level TLB design for any ISA similar to how we can use
> caches for any ISA. I'm not sure if this is something that's enabled by
> your changes, Giacomo, or if it's something others think is important.
>
>
>
> Cheers,
>
> Jason
>
>
>
> On Mon, Sep 21, 2020 at 4:06 AM Gabe Black via gem5-dev 
> wrote:
>
> Oh, nice. I got sidetracked with some other things I wanted to rearrange
> first, so I haven't actually started on the MMU part :-). Please add me as
> a reviewer!
>
>
>
> Gabe
>
>
>
> On Mon, Sep 21, 2020 at 1:17 AM Giacomo Travaglini <
> giacomo.travagl...@arm.com> wrote:
>
> Hi  Gabe, I am actually about to post the same patchset (which is:
> removing the TLB from the CPU interface and make it interface with an MMU
> instead)
>
>
>
> Giacomo
>
>
>
> *From:* Gabe Black via gem5-dev 
> *Sent:* 20 September 2020 04:44
> *To:* gem5 Developer List 
> *Cc:* Gabe Black 
> *Subject:* [gem5-dev] Re: MMU object vs. DTB and ITB
>
>
>
> Oh, this will also absorb multilevel TLBs too, like how ARM has second
> level translation in some cases. This isn't really implemented in x86, but
> could also be used for it's multilevel translation in SVM and VT's nested
> page table schemes.
>
>
>
> Gabe
>
>
>
> On Sat, Sep 19, 2020 at 8:25 PM Gabe Black  wrote:
>
> Hi folks. I've been thinking about how to rework the
> scanning-through-page-translation thing we currently do when translating a
> region of addresses through both the ITB and DTB. We currently do that one
> page at a time by trying one, and then the other. That requires knowing
> what "the" page size is, which introduces a dependence on the ISA and also
> constraints things to a single page size.
>
>
>
> One improvement that I think makes sense is to instead use an approach
> where you'd ask for a translation for a region and let whatever is
> translating for you decide how to break things up. Then it can use a single
> page size, th

[gem5-dev] Change in gem5/gem5[develop]: sim: factor fs_workload address relocation

2020-09-29 Thread Ciro Santilli (Gerrit) via gem5-dev 
Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35335 )



Change subject: sim: factor fs_workload address relocation
..

sim: factor fs_workload address relocation

The same operation was being done from three different places, this commit
factors them out with KernelWorkload::relocateAddr.

Also always call the function instead of using the member in case the
getter starts doing some extra logic later on.

Change-Id: Idc06ac9fd361c62dec3ef3d7db4d912068a28a88
---
M src/arch/arm/freebsd/fs_workload.cc
M src/arch/arm/fs_workload.cc
M src/arch/arm/linux/fs_workload.cc
M src/sim/kernel_workload.cc
M src/sim/kernel_workload.hh
5 files changed, 29 insertions(+), 23 deletions(-)



diff --git a/src/arch/arm/freebsd/fs_workload.cc  
b/src/arch/arm/freebsd/fs_workload.cc

index 080dc35..79bc5e6 100644
--- a/src/arch/arm/freebsd/fs_workload.cc
+++ b/src/arch/arm/freebsd/fs_workload.cc
@@ -81,7 +81,8 @@
 // to do this permanently, for but early bootup work
 // it is helpful.
 if (params()->early_kernel_symbols) {
-auto phys_globals =  
kernelObj->symtab().globals()->mask(_loadAddrMask);

+auto phys_globals = kernelObj->symtab().globals()->mask(
+loadAddrMask());
 kernelSymtab.insert(*phys_globals);
 Loader::debugSymbolTable.insert(*phys_globals);
 }
@@ -95,7 +96,7 @@
 // Kernel supports flattened device tree and dtb file specified.
 // Using Device Tree Blob to describe system configuration.
 inform("Loading DTB file: %s at address %#x\n", params()->dtb_filename,
-params()->atags_addr + _loadAddrOffset);
+params()->atags_addr + loadAddrOffset());

 auto *dtb_file = new ::Loader::DtbFile(params()->dtb_filename);

@@ -108,7 +109,7 @@
 bootReleaseAddr = ra & ~ULL(0x7F);

 dtb_file->buildImage().
-offset(params()->atags_addr + _loadAddrOffset).
+offset(params()->atags_addr + loadAddrOffset()).
 write(system->physProxy);
 delete dtb_file;

@@ -116,7 +117,7 @@
 for (auto *tc: system->threads) {
 tc->setIntReg(0, 0);
 tc->setIntReg(1, params()->machine_type);
-tc->setIntReg(2, params()->atags_addr + _loadAddrOffset);
+tc->setIntReg(2, params()->atags_addr + loadAddrOffset());
 }
 }

diff --git a/src/arch/arm/fs_workload.cc b/src/arch/arm/fs_workload.cc
index 0cafb1b..1fae3ab 100644
--- a/src/arch/arm/fs_workload.cc
+++ b/src/arch/arm/fs_workload.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2015,2017-2019 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2015,2017-2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -72,8 +72,7 @@
 FsWorkload::FsWorkload(Params *p) : KernelWorkload(*p)
 {
 if (kernelObj) {
-kernelEntry = (kernelObj->entryPoint() & loadAddrMask()) +
-loadAddrOffset();
+kernelEntry = relocateAddr(kernelObj->entryPoint());
 }

 bootLoaders.reserve(p->boot_loader.size());
diff --git a/src/arch/arm/linux/fs_workload.cc  
b/src/arch/arm/linux/fs_workload.cc

index 8aba285..dc36195 100644
--- a/src/arch/arm/linux/fs_workload.cc
+++ b/src/arch/arm/linux/fs_workload.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, 2016 ARM Limited
+ * Copyright (c) 2010-2013, 2016, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -76,7 +76,8 @@
 // to do this permanently, for but early bootup work
 // it is helpful.
 if (params()->early_kernel_symbols) {
-auto phys_globals =  
kernelObj->symtab().globals()->mask(_loadAddrMask);

+auto phys_globals = kernelObj->symtab().globals()->mask(
+loadAddrMask());
 kernelSymtab.insert(*phys_globals);
 Loader::debugSymbolTable.insert(*phys_globals);
 }
@@ -92,7 +93,7 @@
 // Kernel supports flattened device tree and dtb file specified.
 // Using Device Tree Blob to describe system configuration.
 inform("Loading DTB file: %s at address %#x\n",  
params()->dtb_filename,

-params()->atags_addr + _loadAddrOffset);
+params()->atags_addr + loadAddrOffset());

 auto *dtb_file = new ::Loader::DtbFile(params()->dtb_filename);

@@ -103,7 +104,7 @@
 }

 dtb_file->buildImage().
-offset(params()->atags_addr + _loadAddrOffset).
+offset(params()->atags_addr + loadAddrOffset()).
 write(system->physProxy);
 delete dtb_file;
 } else {
@@ -152,7 +153,7 @@
 DPRINTF(Loader, "Boot atags was %d bytes in total\n", size << 2);
 DDUMP(Loader, boot_data, size << 2);

-system->physProxy.writeBlob(params()->atags_addr + _loadAddrOffset,
+system->physProxy.writeBlob(params()->atags_addr +  
loadAddrOffset()

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: SMMUv3, default CMDQ entries to 128

2020-09-29 Thread Adrian Herrera (Gerrit) via gem5-dev 
Adrian Herrera has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35297 )



Change subject: dev-arm: SMMUv3, default CMDQ entries to 128
..

dev-arm: SMMUv3, default CMDQ entries to 128

From Linux 587e6c10a7ce89a5924fdbeff2ec524fbd6a124b, SMMUv3
implementations in 64-bit platforms must report a minimum of 128 CMDQ
entries via SMMU_IDR1. Otherwise, the SMMUv3 Linux driver returns -ENXIO.

Change-Id: I304aac1b734515b3077003e8d67cc19730afc67f
---
M src/dev/arm/SMMUv3.py
1 file changed, 3 insertions(+), 3 deletions(-)



diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py
index 29c1568..f53b8ec 100644
--- a/src/dev/arm/SMMUv3.py
+++ b/src/dev/arm/SMMUv3.py
@@ -162,9 +162,9 @@
 # [0] S2P = 0b1, Stage 2 translation supported.
 smmu_idr0 = Param.UInt32(0x094C100F, "SMMU_IDR0 register");

-# [25:21] CMDQS = 0b00101, Maximum number of Command queue entries
-# as log 2 (entries) (0b00101 = 32 entries).
-smmu_idr1 = Param.UInt32(0x00A0, "SMMU_IDR1 register");
+# [25:21] CMDQS = 0b00111, Maximum number of Command queue entries
+# as log 2 (entries) (0b00111 = 128 entries).
+smmu_idr1 = Param.UInt32(0x00E0, "SMMU_IDR1 register");

 smmu_idr2 = Param.UInt32(0, "SMMU_IDR2 register");
 smmu_idr3 = Param.UInt32(0, "SMMU_IDR3 register");

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35297
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I304aac1b734515b3077003e8d67cc19730afc67f
Gerrit-Change-Number: 35297
Gerrit-PatchSet: 1
Gerrit-Owner: Adrian Herrera 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: x86: Use the common pseudoInst dispatch function.

2020-09-29 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/27789 )


Change subject: x86: Use the common pseudoInst dispatch function.
..

x86: Use the common pseudoInst dispatch function.

Instead of hand invoking each individual pseudo inst. New instructions
added in the future will automatically become available without a lot of
extra hand implementation. It also simplifies the x86 ISA description.

Change-Id: Ibb671dc2656e61679b7ed016c51a6c879e12910a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27789
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M src/arch/x86/isa/includes.isa
2 files changed, 8 insertions(+), 92 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa  
b/src/arch/x86/isa/decoder/two_byte_opcodes.isa

index e8b1e3d..2236c4f 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -144,98 +144,13 @@
 // to play with so there can be quite a few pseudo
 // instructions.
 //0x04: loadall_or_reset_or_hang();
-0x4: decode IMMEDIATE {
-format BasicOperate {
-0x00: m5arm({{
-PseudoInst::arm(xc->tcBase());
-}}, IsNonSpeculative);
-0x01: m5quiesce({{
-PseudoInst::quiesce(xc->tcBase());
-}}, IsNonSpeculative, IsQuiesce);
-0x02: m5quiesceNs({{
-PseudoInst::quiesceNs(xc->tcBase(), Rdi);
-}}, IsNonSpeculative, IsQuiesce);
-0x03: m5quiesceCycle({{
-PseudoInst::quiesceCycles(xc->tcBase(), Rdi);
-}}, IsNonSpeculative, IsQuiesce);
-0x04: m5quiesceTime({{
-Rax = PseudoInst::quiesceTime(xc->tcBase());
-}}, IsNonSpeculative);
-0x07: m5rpns({{
-Rax = PseudoInst::rpns(xc->tcBase());
-}}, IsNonSpeculative);
-0x21: m5exit({{
-PseudoInst::m5exit(xc->tcBase(), Rdi);
-}}, IsNonSpeculative);
-0x22: m5fail({{
-PseudoInst::m5fail(xc->tcBase(), Rdi, Rsi);
-}}, IsNonSpeculative);
-0x23: m5sum({{
-Rax = PseudoInst::m5sum(xc->tcBase(),
-Rdi, Rsi, Rdx, Rcx, R8, R9);
-}}, IsNonSpeculative);
-0x30: m5initparam({{
-Rax = PseudoInst::initParam(xc->tcBase(), Rdi,  
Rsi);

-}}, IsNonSpeculative);
-0x31: m5loadsymbol({{
-PseudoInst::loadsymbol(xc->tcBase());
-}}, IsNonSpeculative);
-0x40: m5resetstats({{
-PseudoInst::resetstats(xc->tcBase(), Rdi, Rsi);
-}}, IsNonSpeculative);
-0x41: m5dumpstats({{
-PseudoInst::dumpstats(xc->tcBase(), Rdi, Rsi);
-}}, IsNonSpeculative);
-0x42: m5dumpresetstats({{
-PseudoInst::dumpresetstats(xc->tcBase(), Rdi, Rsi);
-}}, IsNonSpeculative);
-0x43: m5checkpoint({{
-PseudoInst::m5checkpoint(xc->tcBase(), Rdi, Rsi);
-}}, IsNonSpeculative);
-0x50: m5readfile({{
-Rax = PseudoInst::readfile(
-xc->tcBase(), Rdi, Rsi, Rdx);
-}}, IsNonSpeculative);
-0x51: m5debugbreak({{
-PseudoInst::debugbreak(xc->tcBase());
-}}, IsNonSpeculative);
-0x52: m5switchcpu({{
-PseudoInst::switchcpu(xc->tcBase());
-}}, IsNonSpeculative);
-0x53: m5addsymbol({{
-PseudoInst::addsymbol(xc->tcBase(), Rdi, Rsi);
-}}, IsNonSpeculative);
-0x54: m5panic({{
-panic("M5 panic instruction called at pc = %#x.\n",
-  RIP);
-}}, IsNonSpeculative);
-0x55: m5reserved1({{
-warn("M5 reserved opcode 1 ignored.\n");
-}}, IsNonSpeculative);
-0x56: m5reserved2({{
-warn("M5 reserved opcode 2 ignored.\n");
-}}, IsNonSpeculative);
-

[gem5-dev] Change in gem5/gem5[develop]: ext: Disable range-loop-analysis warnings for pybind11

2020-09-29 Thread Nikos Nikoleris (Gerrit) via gem5-dev 
Nikos Nikoleris has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35296 )



Change subject: ext: Disable range-loop-analysis warnings for pybind11
..

ext: Disable range-loop-analysis warnings for pybind11

Change-Id: I9d9e118c1c70c2f6b11260fff31ecd763e491115
Signed-off-by: Nikos Nikoleris 
---
M ext/pybind11/include/pybind11/pybind11.h
1 file changed, 1 insertion(+), 0 deletions(-)



diff --git a/ext/pybind11/include/pybind11/pybind11.h  
b/ext/pybind11/include/pybind11/pybind11.h

index a9ee31a..04ef30f 100644
--- a/ext/pybind11/include/pybind11/pybind11.h
+++ b/ext/pybind11/include/pybind11/pybind11.h
@@ -12,6 +12,7 @@
 #ifdef __clang__
 #pragma clang diagnostic push
 #pragma clang diagnostic ignored "-Wunused-value"
+#pragma clang diagnostic warning "-Wrange-loop-analysis"
 #endif

 #if defined(__INTEL_COMPILER)

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35296
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9d9e118c1c70c2f6b11260fff31ecd763e491115
Gerrit-Change-Number: 35296
Gerrit-PatchSet: 1
Gerrit-Owner: Nikos Nikoleris 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[release-staging-v20.1.0.0]: arch-arm: Instantiate a single HTM checkpoint at ISA::startup

2020-09-29 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35016 )


Change subject: arch-arm: Instantiate a single HTM checkpoint at  
ISA::startup

..

arch-arm: Instantiate a single HTM checkpoint at ISA::startup

Change-Id: I48cc71dce607233f025387379507bcd485943dde
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35016
Reviewed-by: Jason Lowe-Power 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/insts/tme64ruby.cc
M src/arch/arm/isa.cc
2 files changed, 15 insertions(+), 7 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/insts/tme64ruby.cc  
b/src/arch/arm/insts/tme64ruby.cc

index 99481ba..f8d9481 100644
--- a/src/arch/arm/insts/tme64ruby.cc
+++ b/src/arch/arm/insts/tme64ruby.cc
@@ -109,15 +109,16 @@

 // checkpointing occurs in the outer transaction only
 if (htm_depth == 1) {
-auto new_cpt = new HTMCheckpoint();
+BaseHTMCheckpointPtr& cpt =  
xc->tcBase()->getHtmCheckpointPtr();


-new_cpt->save(tc);
-new_cpt->destinationRegister(dest);
+HTMCheckpoint *armcpt =
+dynamic_cast(cpt.get());
+assert(armcpt != nullptr);
+
+armcpt->save(tc);
+armcpt->destinationRegister(dest);

 ArmISA::globalClearExclusive(tc);
-
-xc->tcBase()->setHtmCheckpointPtr(
-std::unique_ptr(new_cpt));
 }

 xc->setIntRegOperand(this, 0, (Dest64) & mask(intWidth));
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 9ace236..4ad1125 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -38,6 +38,7 @@
 #include "arch/arm/isa.hh"

 #include "arch/arm/faults.hh"
+#include "arch/arm/htm.hh"
 #include "arch/arm/interrupts.hh"
 #include "arch/arm/pmu.hh"
 #include "arch/arm/self_debug.hh"
@@ -439,9 +440,15 @@
 {
 BaseISA::startup();

-if (tc)
+if (tc) {
 setupThreadContext();

+if (haveTME) {
+std::unique_ptr cpt(new HTMCheckpoint());
+tc->setHtmCheckpointPtr(std::move(cpt));
+}
+}
+
 afterStartup = true;
 }


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35016
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.1.0.0
Gerrit-Change-Id: I48cc71dce607233f025387379507bcd485943dde
Gerrit-Change-Number: 35016
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Timothy Hayes 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[release-staging-v20.1.0.0]: cpu: Allow storing an invalid HTM checkpoint

2020-09-29 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35015 )


Change subject: cpu: Allow storing an invalid HTM checkpoint
..

cpu: Allow storing an invalid HTM checkpoint

Commits 02745afd and f9b4e32 introduced a mechanism for creating checkpoint
objects for hardware transactional memory (HTM) and Arm TME. Because the
checkpoint object also contains the local UID of a transaction, it is
needed before any architectural checkpointing takes places. This caused
segfaults when running HTM codes.

This commit allows ISAs to allocate a checkpoint once at the beginning
of simulation.  In order to do that we need to remove the validity check
assertion; the cpt will become valid only after a first successfull
transaction start

Change-Id: I233d01805f8ab655131ed8cd6404950a2bf6fbc7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35015
Reviewed-by: Jason Lowe-Power 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/cpu/o3/thread_context_impl.hh
M src/cpu/simple_thread.cc
2 files changed, 0 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/cpu/o3/thread_context_impl.hh  
b/src/cpu/o3/thread_context_impl.hh

index 005aa57..bea4dc7 100644
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -347,7 +347,6 @@
 void
 O3ThreadContext::setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt)
 {
-assert(!thread->htmCheckpoint->valid());
 thread->htmCheckpoint = std::move(new_cpt);
 }

diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 28a1c80..b9b69d8 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -196,6 +196,5 @@
 void
 SimpleThread::setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt)
 {
-assert(!_htmCheckpoint->valid());
 _htmCheckpoint = std::move(new_cpt);
 }

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35015
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v20.1.0.0
Gerrit-Change-Id: I233d01805f8ab655131ed8cd6404950a2bf6fbc7
Gerrit-Change-Number: 35015
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Timothy Hayes 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: ext: Add timing indications to every TestCase

2020-09-29 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/32653 )


Change subject: ext: Add timing indications to every TestCase
..

ext: Add timing indications to every TestCase

The log_call helper is now accepting a time parameter (dictionary). If
the param is not None, the function will fill the timing indications
(user and system time) for the TestCase.

There are some TestCases whose user time is not of our interest; for
example we don't really care about the cpu time of a stdout diff
(MatchStdout tests). In those cases the resulting cpu time in the
generated JUnit file (results.xml) will be 0.

JIRA: https://gem5.atlassian.net/browse/GEM5-548

Change-Id: I53c1b59f8ad93900aeac06197e39189c00a9053c
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32653
Tested-by: kokoro 
---
M ext/testlib/helper.py
M ext/testlib/result.py
M ext/testlib/runner.py
M ext/testlib/wrappers.py
M tests/gem5/fixture.py
M tests/gem5/suite.py
6 files changed, 43 insertions(+), 6 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/ext/testlib/helper.py b/ext/testlib/helper.py
index 01ca539..1cb13f0 100644
--- a/ext/testlib/helper.py
+++ b/ext/testlib/helper.py
@@ -132,7 +132,7 @@
 TimedWaitPID.install()

 #TODO Tear out duplicate logic from the sandbox IOManager
-def log_call(logger, command, *popenargs, **kwargs):
+def log_call(logger, command, time, *popenargs, **kwargs):
 '''
 Calls the given process and automatically logs the command and output.

@@ -186,6 +186,12 @@
 retval = p.wait()
 stdout_thread.join()
 stderr_thread.join()
+
+if time is not None and TimedWaitPID.has_time_for_pid(p.pid):
+resource_usage = TimedWaitPID.get_time_for_pid(p.pid)
+time['user_time'] = resource_usage.user_time
+time['system_time'] = resource_usage.system_time
+
 # Return the return exit code of the process.
 if retval != 0:
 raise subprocess.CalledProcessError(retval, cmdstr)
@@ -482,7 +488,8 @@
 (_, tfname) = tempfile.mkstemp(dir=os.path.dirname(out_file),  
text=True)

 with open(tfname, 'r+') as tempfile_:
 try:
-log_call(logger, ['diff', out_file, ref_file],  
stdout=tempfile_)

+log_call(logger, ['diff', out_file, ref_file],
+time=None, stdout=tempfile_)
 except OSError:
 # Likely signals that diff does not exist on this system.  
fallback

 # to difflib
diff --git a/ext/testlib/result.py b/ext/testlib/result.py
index 2d2c506..5c60342 100644
--- a/ext/testlib/result.py
+++ b/ext/testlib/result.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2020 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2017 Mark D. Hill and David A. Wood
 # All rights reserved.
 #
@@ -60,6 +72,10 @@
 def unsuccessful(self):
 return self._metadata.result.value != state.Result.Passed

+@property
+def time(self):
+return self._metadata.time
+

 class InternalTestResult(_CommonMetadataMixin):
 def __init__(self, obj, suite, directory):
@@ -258,6 +274,7 @@
  # TODO JUnit expects class of test.. add as test metadata.
 XMLAttribute('classname', str(test_result.uid)),
 XMLAttribute('status', str(test_result.result)),
+XMLAttribute('time', str(test_result.time["user_time"])),
 ]

 # TODO JUnit expects a message for the reason a test was
diff --git a/ext/testlib/runner.py b/ext/testlib/runner.py
index ee658c9..16ff952 100644
--- a/ext/testlib/runner.py
+++ b/ext/testlib/runner.py
@@ -79,6 +79,8 @@
 self.suite = suite
 self.log = log.test_log
 self.log.test = test
+self.time = {
+"user_time" : 0, "system_time" : 0}

 @helper.cacheresult
 def _fixtures(self):
@@ -152,6 +154,8 @@
 else:
 self.testable.result = Result(Result.Passed)

+self.testable.time = test_params.time
+

 class SuiteRunner(RunnerPattern):
 def test(self):
diff --git a/ext/testlib/wrappers.py b/ext/testlib/wrappers.py
index e919702..b2b887b 100644
--- a/ext/testlib/wrappers.py
+++ b/ext/testlib/wrappers.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2019 ARM Limited
+# Copyright (c) 2019-2020 AR

[gem5-dev] Change in gem5/gem5[develop]: arch: Wrap a docstring in isa_parser.py.

2020-09-29 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35276 )



Change subject: arch: Wrap a docstring in isa_parser.py.
..

arch: Wrap a docstring in isa_parser.py.

This brings the ISA parser in line with the style guide. Note that the
docstring needs to be a single string literal for python to consider it
a docstring, and the parser itself needs each line of the docstring to
be a rule in its CFG. We can accomplish both by taking advantage of the
fact that two directly adjacent quoted strings are treated as a single
string literal by python, and by escaping the newline so that they're
actually considered adjacent.

Change-Id: I7f4d252998877808425aafb0159600ba4c3bf9ad
---
M src/arch/isa_parser.py
1 file changed, 2 insertions(+), 1 deletion(-)



diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 858fe85..43c5c4b 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -2099,7 +2099,8 @@
 # 'def [signed] bitfield  [:]'
 # This generates a preprocessor macro in the output file.
 def p_def_bitfield_0(self, t):
-'def_bitfield : DEF opt_signed BITFIELD ID LESS INTLIT COLON  
INTLIT GREATER SEMI'

+'def_bitfield : DEF opt_signed ' \
+'BITFIELD ID LESS INTLIT COLON INTLIT GREATER SEMI'
 expr = 'bits(machInst, %2d, %2d)' % (t[6], t[8])
 if (t[2] == 'signed'):
 expr = 'sext<%d>(%s)' % (t[6] - t[8] + 1, expr)

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35276
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7f4d252998877808425aafb0159600ba4c3bf9ad
Gerrit-Change-Number: 35276
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch: Split utility methods/variables out of the ISA parser.

2020-09-29 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35279 )



Change subject: arch: Split utility methods/variables out of the ISA parser.
..

arch: Split utility methods/variables out of the ISA parser.

Change-Id: Ifbff4bc6633cd11f98b02ba1291a91c3ad189285
---
M src/arch/isa_parser/isa_parser.py
A src/arch/isa_parser/util.py
2 files changed, 140 insertions(+), 99 deletions(-)



diff --git a/src/arch/isa_parser/isa_parser.py  
b/src/arch/isa_parser/isa_parser.py

index c147caf..2461e29 100755
--- a/src/arch/isa_parser/isa_parser.py
+++ b/src/arch/isa_parser/isa_parser.py
@@ -47,60 +47,10 @@

 from m5.util.grammar import Grammar
 from .operand_types import *
+from .util import *

 debug=False

-###
-# Utility functions
-
-#
-# Indent every line in string 's' by two spaces
-# (except preprocessor directives).
-# Used to make nested code blocks look pretty.
-#
-def indent(s):
-return re.sub(r'(?m)^(?!#)', '  ', s)
-
-#
-# Munge a somewhat arbitrarily formatted piece of Python code
-# (e.g. from a format 'let' block) into something whose indentation
-# will get by the Python parser.
-#
-# The two keys here are that Python will give a syntax error if
-# there's any whitespace at the beginning of the first line, and that
-# all lines at the same lexical nesting level must have identical
-# indentation.  Unfortunately the way code literals work, an entire
-# let block tends to have some initial indentation.  Rather than
-# trying to figure out what that is and strip it off, we prepend 'if
-# 1:' to make the let code the nested block inside the if (and have
-# the parser automatically deal with the indentation for us).
-#
-# We don't want to do this if (1) the code block is empty or (2) the
-# first line of the block doesn't have any whitespace at the front.
-
-def fixPythonIndentation(s):
-# get rid of blank lines first
-s = re.sub(r'(?m)^\s*\n', '', s);
-if (s != '' and re.match(r'[ \t]', s[0])):
-s = 'if 1:\n' + s
-return s
-
-class ISAParserError(Exception):
-"""Exception class for parser errors"""
-def __init__(self, first, second=None):
-if second is None:
-self.lineno = 0
-self.string = first
-else:
-self.lineno = first
-self.string = second
-
-def __str__(self):
-return self.string
-
-def error(*args):
-raise ISAParserError(*args)
-
 
 # Template objects.
 #
@@ -763,54 +713,6 @@
 else:
 self.fp_enable_check = ''

-##
-# Stack: a simple stack object.  Used for both formats (formatStack)
-# and default cases (defaultStack).  Simply wraps a list to give more
-# stack-like syntax and enable initialization with an argument list
-# (as opposed to an argument that's a list).
-
-class Stack(list):
-def __init__(self, *items):
-list.__init__(self, items)
-
-def push(self, item):
-self.append(item);
-
-def top(self):
-return self[-1]
-
-# Format a file include stack backtrace as a string
-def backtrace(filename_stack):
-fmt = "In file included from %s:"
-return "\n".join([fmt % f for f in filename_stack])
-
-
-###
-#
-# LineTracker: track filenames along with line numbers in PLY lineno fields
-# PLY explicitly doesn't do anything with 'lineno' except propagate
-# it.  This class lets us tie filenames with the line numbers with a
-# minimum of disruption to existing increment code.
-#
-
-class LineTracker(object):
-def __init__(self, filename, lineno=1):
-self.filename = filename
-self.lineno = lineno
-
-# Overload '+=' for increments.  We need to create a new object on
-# each update else every token ends up referencing the same
-# constantly incrementing instance.
-def __iadd__(self, incr):
-return LineTracker(self.filename, self.lineno + incr)
-
-def __str__(self):
-return "%s:%d" % (self.filename, self.lineno)
-
-# In case there are places where someone really expects a number
-def __int__(self):
-return self.lineno
-

 ###
 #
diff --git a/src/arch/isa_parser/util.py b/src/arch/isa_parser/util.py
new file mode 100755
index 000..378cb30
--- /dev/null
+++ b/src/arch/isa_parser/util.py
@@ -0,0 +1,139 @@
+# Copyright (c) 2014, 2016, 2018-2019 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributi

[gem5-dev] Change in gem5/gem5[develop]: arch: Move the ISA parser into a package.

2020-09-29 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35277 )



Change subject: arch: Move the ISA parser into a package.
..

arch: Move the ISA parser into a package.

This will make splitting the parser into components easier, since it
will keep help keep everything together and organized.

Change-Id: I737641e124b6da8b1b18a49de9110c8424d8cc4f
---
M src/arch/SConscript
A src/arch/isa_parser/__init__.py
R src/arch/isa_parser/isa_parser.py
3 files changed, 31 insertions(+), 3 deletions(-)



diff --git a/src/arch/SConscript b/src/arch/SConscript
index 12e605f..5fb543e 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -105,15 +105,17 @@
 # output from the ISA description (*.isa) files.
 #

-parser_py = File('isa_parser.py')
+parser_files = Glob('isa_parser/*.py')
 micro_asm_py = File('micro_asm.py')

 # import ply here because SCons screws with sys.path when performing  
actions.

 import ply

+arch_dir = Dir('.')
+
 def run_parser(target, source, env):
 # Add the current directory to the system path so we can import files.
-sys.path[0:0] = [ parser_py.dir.abspath ]
+sys.path[0:0] = [ arch_dir.abspath ]
 import isa_parser

 parser = isa_parser.ISAParser(target[0].dir.abspath)
@@ -207,7 +209,7 @@
 source_gen('generic_cpu_exec_%d.cc' % i)

 # Actually create the builder.
-sources = [desc, parser_py, micro_asm_py]
+sources = [desc, micro_asm_py] + parser_files
 IsaDescBuilder(target=gen, source=sources, env=env)
 return gen

diff --git a/src/arch/isa_parser/__init__.py  
b/src/arch/isa_parser/__init__.py

new file mode 100644
index 000..02f4999
--- /dev/null
+++ b/src/arch/isa_parser/__init__.py
@@ -0,0 +1,26 @@
+# Copyright 2020 Google, Inc.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from .isa_parser import ISAParser
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser/isa_parser.py
similarity index 100%
rename from src/arch/isa_parser.py
rename to src/arch/isa_parser/isa_parser.py

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35277
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I737641e124b6da8b1b18a49de9110c8424d8cc4f
Gerrit-Change-Number: 35277
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch: Minor cleanup of imports in isa_parser.py.

2020-09-29 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35280 )



Change subject: arch: Minor cleanup of imports in isa_parser.py.
..

arch: Minor cleanup of imports in isa_parser.py.

The with statement and print function are no longer in the future, and
the "inspect" module is not used. Also alphabetize the imports.

Change-Id: I35f2b7b0f7495cb9ca79d2cbe05f020560ec3593
---
M src/arch/isa_parser/isa_parser.py
1 file changed, 2 insertions(+), 3 deletions(-)



diff --git a/src/arch/isa_parser/isa_parser.py  
b/src/arch/isa_parser/isa_parser.py

index 2461e29..99bf5aa 100755
--- a/src/arch/isa_parser/isa_parser.py
+++ b/src/arch/isa_parser/isa_parser.py
@@ -37,11 +37,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

-from __future__ import with_statement, print_function
 import os
-import sys
 import re
-import inspect, traceback
+import sys
+import traceback
 # get type names
 from types import *


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35280
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I35f2b7b0f7495cb9ca79d2cbe05f020560ec3593
Gerrit-Change-Number: 35280
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: Add Data Abort handler for Atomic Instructions

2020-09-29 Thread Victor Soria (Gerrit) via gem5-dev 
Victor Soria has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/35295 )



Change subject: cpu-o3: Add Data Abort handler for Atomic Instructions
..

cpu-o3: Add Data Abort handler for Atomic Instructions

Change-Id: I79e7113efd8157fba61b6d4a0b0c09bc6f85ec29
---
M src/cpu/o3/lsq_unit_impl.hh
1 file changed, 12 insertions(+), 0 deletions(-)



diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 808a671..6fd33a4 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -708,6 +708,18 @@
 DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n",
 store_inst->pcState(), store_inst->seqNum);

+// If the instruction is atomic and had a fault then it may not  
have a mem req

+if (store_inst->isAtomic()) {
+// If the instruction faulted, then we need to send it along
+// to commit without the instruction completing.
+if (!(store_inst->hasRequest() &&  
store_inst->strictlyOrdered()) ||

+store_inst->isAtCommit()) {
+store_inst->setExecuted();
+}
+iewStage->instToCommit(store_inst);
+iewStage->activityThisCycle();
+}
+
 return store_fault;
 }


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35295
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I79e7113efd8157fba61b6d4a0b0c09bc6f85ec29
Gerrit-Change-Number: 35295
Gerrit-PatchSet: 1
Gerrit-Owner: Victor Soria 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s