[gem5-dev] PCI memory BARs broken on ARM
Hi folks. We locally just rebased and picked up a change where the ARM PCI controller's configuration was fixed so that it had the appropriate starting address for memory mappings. Now that that's correct, it means that instead of setting memory BARs to 0x4000 (for example) to get them in the correct place, they need to be set to 0, and the "hardware" will take care of adding in a 0x4000 offset. That's more correct, but it means that now the BAR needs to be set to 0, and the gem5 PCI BAR handling code is a little bit simplistic and wrong in that it treats 0 and 0x as magical values and has special behavior when the BARs are set to them. Specifically, it treats a 0 as off, and doesn't update the ranges the device responds to on its parent bus. This isn't a problem on x86 where the memory addresses are usually not 0 since there's actual RAM there, and there's generally no offset applied either. To fix this, I have a big rework in progress which will change how BARs are set up for PCI devices across the board. Note that this will not affect any of the work Andreas did a while ago setting up a host device, the DeviceInterface type, etc., which is all fine. There are two major parts to the change I'm making, in python and C++. First, rather than having several arrays of scalar parameters which together control the BARs, a raw BAR value as it would be in the config, a flag setting it s a "legacyIO", and a size, (and a legacy IO offset!) each BAR is represented by a python object whose type reflects it's job. There is one for IO, one for memory, one for the upper 32 bits of a 64 bit BAR, and one for legacy IO. They each have appropriate properties like a fixed address or a size as appropriate, and are assigned to a device as a VectorParam. Then on the C++ side, rather than try to track things from the raw BAR values, config writes are filtered through the BAR objects which know what bits to mask, what the corresponding address range should be based on their type, etc. I also took this opportunity to clear away a number of clumsy bookkeeping mechanisms and bugs/misunderstandings of how BARs work, many of them my own from a long time ago. Also, the handling of disabling memory or IO BARs through the config "command" byte is now handled centrally, rather than being implemented one off in the IDE controller. Both of these things seem to now be working, so that's great. The reason I'm writing an email rather than sending a code review (yet) is that I'm also running into a problem with the python config. The gist of it is that the PCI device creates the VectorParam of BARs. The IDE controller then sets the BARs using a python list of BAR objects as a default, and that works. Then in the X86 SouthBridge object (x86 is a little easier for me to test atm), I've tried to overwrite some of those BARs individually to give them new defaults which make sense on x86. That fails because the new values are not parented correctly. If I try setting the whole VectorParam with a new list, then it works fine. I think the problem is that foo.bar[0] = doesn't actually set foo.bar, it extracts bar from foo and then sets element 0 in the bar it extracted. The bookkeeping for this is wrong somehow. Anyway, I wanted to send out an email to let people know there's a bug here on both counts, in case they ran into any problems. The default ARM setup should be mostly ok since the only PCI device seems to be the IDE controller, and that uses legacy style fixed IO BARs which seem to work fine. I also wanted to let people know I'm fighting with the bug in the config system. I'm going to try to figure that one out, but it's pretty twisty in there and I'm struggling to understand how all that plumbing works. If anybody has any great insights, I'd be happy to hear them! Gabe ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Re: Segmentation fault in gem5
Hey, I haven't tried to replicate this segfault myself, but it may be related to this segfault we've encountered before: https://gem5.atlassian.net/browse/GEM5-782. We haven't really found the root cause of this problem yet. If this is the same issue, it can be overcome by compiling gem5 to it's "debug" build variant. I.e., recompile with `scons build/ARM_MESI_Three_Level/gem5.debug`, then use the `build/ARM_MESI_Three_Level/gem5.debug` instead of the `gem5.opt` one. Please let me know if this does or does not work. As a minimum I'd like to know if this is the same error as GEM5-782. Kind regards, Bobby -- Dr. Bobby R. Bruce Room 2235, Kemper Hall, UC Davis Davis, CA, 95616 web: https://www.bobbybruce.net On Thu, Oct 1, 2020 at 12:42 AM 1154063264--- via gem5-dev < gem5-dev@gem5.org> wrote: > I am trying to run parsec in MESI_Three_Level-gem5.opt for ARM > architecture in FS mode, > but I am getting a segmentation fault. > > info: Entering event queue @ 25592214185500. Starting simulation... > info: Entering event queue @ 2559222830. Starting simulation... > gem5 has encountered a segmentation fault! > > --- BEGIN LIBC BACKTRACE --- > > ./build/ARM_MESI_Three_Level/gem5.opt(_Z15print_backtracev+0x30)[0x559591d5f160] > ./build/ARM_MESI_Three_Level/gem5.opt(+0x1ed2b15)[0x559591d72b15] > /lib/x86_64-linux-gnu/libpthread.so.0(+0x153c0)[0x7f047e58d3c0] > > ./build/ARM_MESI_Three_Level/gem5.opt(_ZN9DataBlockaSERKS_+0x12)[0x559591e06e12] > > ./build/ARM_MESI_Three_Level/gem5.opt(_ZN18L1Cache_Controller25u_writeDataFromL2ResponseERP11L1Cache_TBERP13L1Cache_Entrym+0xf2)[0x5595925d51c2] > > ./build/ARM_MESI_Three_Level/gem5.opt(_ZN18L1Cache_Controller18doTransitionWorkerE13L1Cache_Event13L1Cache_StateRS1_RP11L1Cache_TBERP13L1Cache_Entrym+0xe93)[0x5595925e1713] > > ./build/ARM_MESI_Three_Level/gem5.opt(_ZN18L1Cache_Controller12doTransitionE13L1Cache_EventP13L1Cache_EntryP11L1Cache_TBEm+0x591)[0x5595925e1ef1] > > ./build/ARM_MESI_Three_Level/gem5.opt(_ZN18L1Cache_Controller6wakeupEv+0x9c3)[0x5595925e48e3] > > ./build/ARM_MESI_Three_Level/gem5.opt(_ZN10EventQueue10serviceOneEv+0xb9)[0x559591d67159] > > ./build/ARM_MESI_Three_Level/gem5.opt(_Z9doSimLoopP10EventQueue+0xf8)[0x559591d87dc8] > ./build/ARM_MESI_Three_Level/gem5.opt(_Z8simulatem+0xaed)[0x559591d88bbd] > > ./build/ARM_MESI_Three_Level/gem5.opt(_ZN10RubySystem12memWritebackEv+0xa29)[0x559590b79629] > ./build/ARM_MESI_Three_Level/gem5.opt(+0x25b8df2)[0x559592458df2] > ./build/ARM_MESI_Three_Level/gem5.opt(+0x1f3d899)[0x559591ddd899] > > /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x9701)[0x7f047e6b3381] > > /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7f8)[0x7f047e6a9628] > > /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6f81)[0x7f047e6b0c01] > > /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7f8)[0x7f047e6a9628] > > /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6f81)[0x7f047e6b0c01] > > /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7f8)[0x7f047e6a9628] > > /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6f81)[0x7f047e6b0c01] > > /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7f8)[0x7f047e6a9628] > > /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6f81)[0x7f047e6b0c01] > > /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7f8)[0x7f047e6a9628] > > /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCode+0x19)[0x7f047e6a9b39] > > /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6e76)[0x7f047e6b0af6] > > /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7f8)[0x7f047e6a9628] > > /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6f81)[0x7f047e6b0c01] > > /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7f8)[0x7f047e6a9628] > > /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCode+0x19)[0x7f047e6a9b39] > > /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyRun_StringFlags+0x76)[0x7f047e682846] > ./build/ARM_MESI_Three_Level/gem5.opt(_Z6m5MainiPPc+0x8b)[0x559591d70a8b] > --- END LIBC BACKTRACE --- > Segmentation fault > > What can be done here to resolve this? > ___ > gem5-dev mailing list -- gem5-dev@gem5.org > To unsubscribe send an email to gem5-dev-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: misc: Changed gem5 version info for gem5 20.2 dev
Bobby R. Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/35439 ) Change subject: misc: Changed gem5 version info for gem5 20.2 dev .. misc: Changed gem5 version info for gem5 20.2 dev Change-Id: I34505c054f1ec83f5da169bfde90702f3da3917e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35439 Tested-by: kokoro Reviewed-by: Bobby R. Bruce Maintainer: Bobby R. Bruce --- M ext/testlib/configuration.py M src/Doxyfile M src/base/version.cc 3 files changed, 3 insertions(+), 3 deletions(-) Approvals: Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/ext/testlib/configuration.py b/ext/testlib/configuration.py index 3203479..1267c25 100644 --- a/ext/testlib/configuration.py +++ b/ext/testlib/configuration.py @@ -214,7 +214,7 @@ os.pardir, os.pardir)) defaults.result_path = os.path.join(os.getcwd(), 'testing-results') -defaults.resource_url = 'http://dist.gem5.org/dist/v20-1' +defaults.resource_url = 'http://dist.gem5.org/dist/develop' defaults.resource_path = os.path.abspath(os.path.join(defaults.base_dir, 'tests', 'gem5', diff --git a/src/Doxyfile b/src/Doxyfile index d029a66..d453314 100644 --- a/src/Doxyfile +++ b/src/Doxyfile @@ -31,7 +31,7 @@ # This could be handy for archiving the generated documentation or # if some version control system is used. -PROJECT_NUMBER = v20.1.0.0 +PROJECT_NUMBER = DEVELOP-FOR-V20.2 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) # base path where the generated documentation will be put. diff --git a/src/base/version.cc b/src/base/version.cc index 8edb8c6..cfa98f9 100644 --- a/src/base/version.cc +++ b/src/base/version.cc @@ -29,4 +29,4 @@ /** * @ingroup api_base_utils */ -const char *gem5Version = "20.1.0.0"; +const char *gem5Version = "[DEVELOP-FOR-V20.2]"; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35439 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I34505c054f1ec83f5da169bfde90702f3da3917e Gerrit-Change-Number: 35439 Gerrit-PatchSet: 3 Gerrit-Owner: Bobby R. Bruce Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: base: Add some error handling to compiler.hh.
Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/35275 ) Change subject: base: Add some error handling to compiler.hh. .. base: Add some error handling to compiler.hh. Rather than just leaving some macros undefined if none of the scenarios we checked for match, we should report an error so it's clear what happened. Otherwise the places the macros are used will just not compile properly, or worse will silently not work correctly. Change-Id: Ie010d6b6d1b6a1496a45d9ebc0d75d1c804df12f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35275 Reviewed-by: Daniel Carvalho Reviewed-by: Nikos Nikoleris Maintainer: Gabe Black Tested-by: kokoro --- M src/base/compiler.hh 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: Nikos Nikoleris: Looks good to me, approved Daniel Carvalho: Looks good to me, but someone else must approve Gabe Black: Looks good to me, approved kokoro: Regressions pass diff --git a/src/base/compiler.hh b/src/base/compiler.hh index ee9a224..ead1507 100644 --- a/src/base/compiler.hh +++ b/src/base/compiler.hh @@ -76,6 +76,8 @@ // gcc and clang support a custom attribute which is essentially the same // thing. # define M5_VAR_USED [[gnu::unused]] +#else +# error "Don't know what to do for your compiler." #endif @@ -106,6 +108,8 @@ // we can't do that with direct substitution. # define M5_LIKELY(cond) __builtin_expect(!!(cond), 1) # define M5_UNLIKELY(cond) __builtin_expect(!!(cond), 0) +#else +# error "Don't know what to do for your compiler." #endif // When a member variable may be unused, mark it with M5_CLASS_VAR_USED. This -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35275 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ie010d6b6d1b6a1496a45d9ebc0d75d1c804df12f Gerrit-Change-Number: 35275 Gerrit-PatchSet: 2 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Nikos Nikoleris Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implement ArmPMU DTB generation
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/35476 )
Change subject: arch-arm: Implement ArmPMU DTB generation
..
arch-arm: Implement ArmPMU DTB generation
This has been implemented by following Linux documentation:
Documentation/devicetree/bindings/arm/pmu.txt
Change-Id: I22583eed3792d5828f9c260e952ec5e8cf9e118b
Signed-off-by: Giacomo Travaglini
---
M src/arch/arm/ArmPMU.py
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/ArmPMU.py b/src/arch/arm/ArmPMU.py
index 047e908..1416e72 100644
--- a/src/arch/arm/ArmPMU.py
+++ b/src/arch/arm/ArmPMU.py
@@ -39,7 +39,8 @@
from m5.params import *
from m5.params import isNullPointer
from m5.proxy import *
-from m5.objects.Gic import ArmInterruptPin
+from m5.objects.Gic import ArmInterruptPin, ArmPPI
+from m5.util.fdthelper import *
class ProbeEvent(object):
def __init__(self, pmu, _eventId, obj, *listOfNames):
@@ -168,6 +169,20 @@
# 0x2F: L2D_TLB
# 0x30: L2I_TLB
+def generateDeviceTree(self, state):
+# For simplicity we just support PPIs for DTB autogen otherwise
+# it would be difficult to construct a ordered list of SPIs
+assert isinstance(self.interrupt, ArmPPI)
+
+node = FdtNode("pmu")
+node.appendCompatible("arm,armv8-pmuv3")
+
+node.append(
+FdtPropertyWords("interrupts",
+self.interrupt.generateFdtProperty()))
+
+yield node
+
cycleEventId = Param.Int(ARCH_EVENT_CORE_CYCLES, "Cycle event id")
platform = Param.Platform(Parent.any, "Platform this device is part
of.")
eventCounters = Param.Int(31, "Number of supported PMU counters")
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/35476
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I22583eed3792d5828f9c260e952ec5e8cf9e118b
Gerrit-Change-Number: 35476
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: misc: Re-add -Werror for the gem5 20.2 development
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/35495 )
Change subject: misc: Re-add -Werror for the gem5 20.2 development
..
misc: Re-add -Werror for the gem5 20.2 development
This reverts commit 2a4357bfd0c688a19cfd6b1c600bb2d2d6fa6151,
https://gem5-review.googlesource.com/c/public/gem5/+/35455
Change-Id: I10de506658bcad542abbb6d2b4f0c416d55bc121
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35495
Reviewed-by: Bobby R. Bruce
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M SConstruct
1 file changed, 6 insertions(+), 0 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index ce9e9b6..8e7ec34 100755
--- a/SConstruct
+++ b/SConstruct
@@ -337,6 +337,12 @@
main.Append(PSHLINKFLAGS=shared_partial_flags)
main.Append(PLINKFLAGS=shared_partial_flags)
+# Treat warnings as errors but white list some warnings that we
+# want to allow (e.g., deprecation warnings).
+main.Append(CCFLAGS=['-Werror',
+ '-Wno-error=deprecated-declarations',
+ '-Wno-error=deprecated',
+])
else:
error('\n'.join((
"Don't know what compiler options to use for your compiler.",
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I10de506658bcad542abbb6d2b4f0c416d55bc121
Gerrit-Change-Number: 35495
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby R. Bruce
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Segmentation fault in gem5
I am trying to run parsec in MESI_Three_Level-gem5.opt for ARM architecture in FS mode, but I am getting a segmentation fault. info: Entering event queue @ 25592214185500. Starting simulation... info: Entering event queue @ 2559222830. Starting simulation... gem5 has encountered a segmentation fault! --- BEGIN LIBC BACKTRACE --- ./build/ARM_MESI_Three_Level/gem5.opt(_Z15print_backtracev+0x30)[0x559591d5f160] ./build/ARM_MESI_Three_Level/gem5.opt(+0x1ed2b15)[0x559591d72b15] /lib/x86_64-linux-gnu/libpthread.so.0(+0x153c0)[0x7f047e58d3c0] ./build/ARM_MESI_Three_Level/gem5.opt(_ZN9DataBlockaSERKS_+0x12)[0x559591e06e12] ./build/ARM_MESI_Three_Level/gem5.opt(_ZN18L1Cache_Controller25u_writeDataFromL2ResponseERP11L1Cache_TBERP13L1Cache_Entrym+0xf2)[0x5595925d51c2] ./build/ARM_MESI_Three_Level/gem5.opt(_ZN18L1Cache_Controller18doTransitionWorkerE13L1Cache_Event13L1Cache_StateRS1_RP11L1Cache_TBERP13L1Cache_Entrym+0xe93)[0x5595925e1713] ./build/ARM_MESI_Three_Level/gem5.opt(_ZN18L1Cache_Controller12doTransitionE13L1Cache_EventP13L1Cache_EntryP11L1Cache_TBEm+0x591)[0x5595925e1ef1] ./build/ARM_MESI_Three_Level/gem5.opt(_ZN18L1Cache_Controller6wakeupEv+0x9c3)[0x5595925e48e3] ./build/ARM_MESI_Three_Level/gem5.opt(_ZN10EventQueue10serviceOneEv+0xb9)[0x559591d67159] ./build/ARM_MESI_Three_Level/gem5.opt(_Z9doSimLoopP10EventQueue+0xf8)[0x559591d87dc8] ./build/ARM_MESI_Three_Level/gem5.opt(_Z8simulatem+0xaed)[0x559591d88bbd] ./build/ARM_MESI_Three_Level/gem5.opt(_ZN10RubySystem12memWritebackEv+0xa29)[0x559590b79629] ./build/ARM_MESI_Three_Level/gem5.opt(+0x25b8df2)[0x559592458df2] ./build/ARM_MESI_Three_Level/gem5.opt(+0x1f3d899)[0x559591ddd899] /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x9701)[0x7f047e6b3381] /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7f8)[0x7f047e6a9628] /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6f81)[0x7f047e6b0c01] /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7f8)[0x7f047e6a9628] /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6f81)[0x7f047e6b0c01] /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7f8)[0x7f047e6a9628] /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6f81)[0x7f047e6b0c01] /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7f8)[0x7f047e6a9628] /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6f81)[0x7f047e6b0c01] /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7f8)[0x7f047e6a9628] /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCode+0x19)[0x7f047e6a9b39] /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6e76)[0x7f047e6b0af6] /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7f8)[0x7f047e6a9628] /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6f81)[0x7f047e6b0c01] /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x7f8)[0x7f047e6a9628] /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCode+0x19)[0x7f047e6a9b39] /lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyRun_StringFlags+0x76)[0x7f047e682846] ./build/ARM_MESI_Three_Level/gem5.opt(_Z6m5MainiPPc+0x8b)[0x559591d70a8b] --- END LIBC BACKTRACE --- Segmentation fault What can be done here to resolve this? ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
