[gem5-dev] Design doc for partial rework of instruction execution mechanism
Hey folks.I have a design doc for a moderate in scope but significant in impact rework of how instruction execution and tracing work in gem5. This is something I've been thinking about for a while, but threw together just now to get it out there: https://docs.google.com/document/d/1IqxBYr_arZq5G51oqmXoL5I9HiiwWMQ_t-rvHA78YPE/edit?usp=sharing This is strongly informed by an earlier design doc I wrote about how registers are handled here: https://docs.google.com/document/d/1O_u_Xq14TgreYThuZcbM3kuXFCrKvaFHA2O9poCeHSk/edit#heading=h.r067bn3rmydo It is a lot more narrowly scoped though, focusing only on operands and instruction execution at the StaticInst level, but also extends beyond what was described in that original doc. I'm biased of course, but I think there's a lot of value in reworking things as described in the doc. Please take a look at let me know what you think. Gabe ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: scons: Check for "make" when using LTO with gcc.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41773 )
Change subject: scons: Check for "make" when using LTO with gcc.
..
scons: Check for "make" when using LTO with gcc.
gcc uses "make" to parallelize LTO. If we're using gcc and make isn't
found, we have to use single threaded LTO instead. A warning will let
the user know what's happening and that they might want to correct the
situation.
Technically gcc can use the MAKE environment variable to override the
program it uses, although I assume it still has to be "make" compatible.
Given the fairly low likelihood that someone will need that override and
the fact that scons won't pipe that variable through unless we plumb it
up, we'll just ignore that for now.
Change-Id: I891b213ece2a75bd8a915ee91f4130458dab397b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41773
Reviewed-by: Earl Ou
Maintainer: Gabe Black
Tested-by: kokoro
---
M SConstruct
1 file changed, 12 insertions(+), 2 deletions(-)
Approvals:
Earl Ou: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index cc3af90..19a5da9 100755
--- a/SConstruct
+++ b/SConstruct
@@ -360,14 +360,24 @@
# Add the appropriate Link-Time Optimization (LTO) flags
# unless LTO is explicitly turned off.
if not GetOption('no_lto'):
+# g++ uses "make" to parallelize LTO. The program can be overriden
with
+# the environment variable "MAKE", but we currently make no
attempt to
+# plumb that variable through.
+parallelism = ''
+if main.Detect('make'):
+parallelism = '=%d' % GetOption('num_jobs')
+else:
+warning('"make" not found, link time optimization will be '
+'single threaded.')
+
# Pass the LTO flag when compiling to produce GIMPLE
# output, we merely create the flags here and only append
# them later
-main['LTO_CCFLAGS'] = ['-flto=%d' % GetOption('num_jobs')]
+main['LTO_CCFLAGS'] = ['-flto%s' % parallelism]
# Use the same amount of jobs for LTO as we are running
# scons with
-main['LTO_LDFLAGS'] = ['-flto=%d' % GetOption('num_jobs')]
+main['LTO_LDFLAGS'] = ['-flto%s' % parallelism]
main.Append(TCMALLOC_CCFLAGS=['-fno-builtin-malloc', '-fno-builtin-calloc',
'-fno-builtin-realloc', '-fno-builtin-free'])
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41773
To unsubscribe, or for help writing mail filters, visit
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I891b213ece2a75bd8a915ee91f4130458dab397b
Gerrit-Change-Number: 41773
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-CC: Jui-min Lee
Gerrit-CC: Yu-hsin Wang
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Implementation of CLINT
Peter Yuen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40597 )
Change subject: arch-riscv: Implementation of CLINT
..
arch-riscv: Implementation of CLINT
This patch implements the CLINT device model based
on the SiFive U54MC datasheet. CLINT is modelled to
receive its clock signal via an interrupt pin. A
generic RTC (non-MMIO) is also implemented to provide
this signal at arbitrary frequencies.
isa.cc is also modified to provide a correct implementation
of the rdtime instruction. It will read from the miscreg
file (which is updated by CLINT every time mtime is
incremented).
Change-Id: I6f5393f3a8fdbd059f25df51d3d74bcb28da09f1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40597
Tested-by: kokoro
Reviewed-by: Ayaz Akram
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M src/arch/riscv/isa.cc
A src/dev/riscv/Clint.py
A src/dev/riscv/RTC.py
A src/dev/riscv/SConscript
A src/dev/riscv/clint.cc
A src/dev/riscv/clint.hh
A src/dev/riscv/rtc.cc
A src/dev/riscv/rtc.hh
8 files changed, 696 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Ayaz Akram: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 98798e7..8d200d4 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -255,7 +255,7 @@
if (hpmCounterEnabled(MISCREG_TIME)) {
DPRINTF(RiscvMisc, "Wall-clock counter at: %llu.\n",
std::time(nullptr));
-return std::time(nullptr);
+return readMiscRegNoEffect(MISCREG_TIME);
} else {
warn("Wall clock disabled.\n");
return 0;
diff --git a/src/dev/riscv/Clint.py b/src/dev/riscv/Clint.py
new file mode 100644
index 000..25b595b
--- /dev/null
+++ b/src/dev/riscv/Clint.py
@@ -0,0 +1,53 @@
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.objects.Device import BasicPioDevice
+from m5.objects.IntPin import IntSinkPin
+from m5.params import *
+from m5.proxy import *
+
+class Clint(BasicPioDevice):
+"""
+This implementation of CLINT is based on
+the SiFive U54MC datasheet:
+https://sifive.cdn.prismic.io/sifive/fab000f6-
+0e07-48d0-9602-e437d5367806_sifive_U54MC_rtl_
+full_20G1.03.00_manual.pdf
+"""
+type = 'Clint'
+cxx_header = 'dev/riscv/clint.hh'
+intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
+int_pin = IntSinkPin('Pin to receive RTC signal')
+pio_size = Param.Addr(0xC000, "PIO Size")
diff --git a/src/dev/riscv/RTC.py b/src/dev/riscv/RTC.py
new file mode 100644
index 000..2de7d32
--- /dev/null
+++ b/src/dev/riscv/RTC.py
@@ -0,0 +1,51 @@
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# T
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: RISC-V HiFive Platform implementation
Peter Yuen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/40599 ) Change subject: arch-riscv: RISC-V HiFive Platform implementation .. arch-riscv: RISC-V HiFive Platform implementation This patch implements the RISC-V HiFive Platform (based on the SiFive HiFive series). The HiFive platform requires a PLIC and CLINT device (based on current HiFive boards). The optional uart_int_id field redirects Console interrupts to the PLIC interrupt controller. PlicDevice is a wrapper around BasicPioDevice that requires an interrupt ID. Interrupts are expected to be raised via platform->postPciInterrupt(id). VirtIOMMIO is a slight modification from the ARM implementation such that interrupts are posted through PLIC PlicDevice is a wrapper around BasicPioDevice that requires an interrupt ID. Interrupts are expected to be raised via platform->postPciInterrupt(id). VirtIOMMIO is a slight modification from the ARM implementation such that interrupts are posted through PLIC. Uart8250 was modified slightly for easier Python setup. Change-Id: I4bbdb5f903b52a41d1b7e0ccc44877c46cd30d56 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40599 Reviewed-by: Ayaz Akram Reviewed-by: Jason Lowe-Power Tested-by: kokoro Maintainer: Jason Lowe-Power --- A src/dev/riscv/HiFive.py A src/dev/riscv/PlicDevice.py M src/dev/riscv/SConscript A src/dev/riscv/VirtIOMMIO.py A src/dev/riscv/hifive.cc A src/dev/riscv/hifive.hh A src/dev/riscv/plic_device.cc A src/dev/riscv/plic_device.hh A src/dev/riscv/vio_mmio.cc A src/dev/riscv/vio_mmio.hh M src/dev/serial/Uart.py M src/dev/serial/uart8250.cc 12 files changed, 944 insertions(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, but someone else must approve; Looks good to me, approved Ayaz Akram: Looks good to me, approved kokoro: Regressions pass diff --git a/src/dev/riscv/HiFive.py b/src/dev/riscv/HiFive.py new file mode 100755 index 000..17d54e3 --- /dev/null +++ b/src/dev/riscv/HiFive.py @@ -0,0 +1,169 @@ +# Copyright (c) 2021 Huawei International +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.Platform import Platform +from m5.objects.PMAChecker import PMAChecker +from m5.objects.Clint import Clint +from m5.objects.Plic import Plic +from m5.objects.RTC import RiscvRTC +from m5.objects.Uart import Uart8250 +from m5.objects.Terminal import Terminal +from m5.params import * +from m5.proxy import * + +class HiFive(Platform): +"""HiFive Platform + +Implementation: +This is the base class for SiFive's HiFive +board series. It contains the CLINT and PLIC +interrupt controllers, Uart and Disk. + +Implementation details are based on SiFive +FU540-C000. https://sifive.cdn.prismic.io/ +sifive/b5e7a29c-d3c2-44ea-85fb-acc1df282e2 +1_FU540-C000-v1p3.pdf + +Setup: +The fo
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: PLIC Implementation
Peter Yuen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40598 )
Change subject: arch-riscv: PLIC Implementation
..
arch-riscv: PLIC Implementation
This patch contains the implementation for the RISC-V PLIC.
The PLIC Memory Map is based on the SiFive U54MC datasheet.
The PLIC models a 3-cycle latency as stated in the RISC-V
specs.
Change-Id: I571c7bd3bd2918c92e4f207a1b57cf9d06e9c72f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40598
Reviewed-by: Ayaz Akram
Reviewed-by: Jason Lowe-Power
Tested-by: kokoro
Maintainer: Jason Lowe-Power
---
A src/dev/riscv/Plic.py
M src/dev/riscv/SConscript
A src/dev/riscv/plic.cc
A src/dev/riscv/plic.hh
4 files changed, 882 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Ayaz Akram: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/riscv/Plic.py b/src/dev/riscv/Plic.py
new file mode 100644
index 000..0e2f386
--- /dev/null
+++ b/src/dev/riscv/Plic.py
@@ -0,0 +1,52 @@
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.objects.Device import BasicPioDevice
+from m5.params import *
+from m5.proxy import *
+
+class Plic(BasicPioDevice):
+"""
+This implementation of PLIC is based on
+the SiFive U54MC datasheet:
+https://sifive.cdn.prismic.io/sifive/fab000f6-
+0e07-48d0-9602-e437d5367806_sifive_U54MC_rtl_
+full_20G1.03.00_manual.pdf
+"""
+type = 'Plic'
+cxx_header = 'dev/riscv/plic.hh'
+intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
+pio_size = Param.Addr(0x400, "PIO Size")
+n_src = Param.Int("Number of interrupt sources")
diff --git a/src/dev/riscv/SConscript b/src/dev/riscv/SConscript
index 43946c2..08d462b 100755
--- a/src/dev/riscv/SConscript
+++ b/src/dev/riscv/SConscript
@@ -31,9 +31,12 @@
if env['TARGET_ISA'] == 'riscv':
SimObject('Clint.py')
+SimObject('Plic.py')
SimObject('RTC.py')
DebugFlag('Clint')
+DebugFlag('Plic')
Source('clint.cc')
+Source('plic.cc')
Source('rtc.cc')
diff --git a/src/dev/riscv/plic.cc b/src/dev/riscv/plic.cc
new file mode 100644
index 000..60ac192
--- /dev/null
+++ b/src/dev/riscv/plic.cc
@@ -0,0 +1,544 @@
+/*
+ * Copyright (c) 2021 Huawei International
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distri
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Added PMA support for RiscvTLB
Peter Yuen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/40596 ) Change subject: arch-riscv: Added PMA support for RiscvTLB .. arch-riscv: Added PMA support for RiscvTLB Since the RISC-V privileged specs V1.11 did not specify an implementation of physical memory attributes (PMA), e.g. cacheability, an abstract PMAChecker class is created. This class acts as a generic PMAChecker hardware without any latency modelling. The TLB finds the PMAChecker defined at the MMU level by Parent.any. Change-Id: I4400133895be44da67536d80b82422ec3a49d786 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40596 Reviewed-by: Ayaz Akram Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- A src/arch/riscv/PMAChecker.py M src/arch/riscv/RiscvMMU.py M src/arch/riscv/RiscvTLB.py M src/arch/riscv/SConscript M src/arch/riscv/pagetable_walker.cc M src/arch/riscv/pagetable_walker.hh A src/arch/riscv/pma_checker.cc A src/arch/riscv/pma_checker.hh M src/arch/riscv/tlb.cc M src/arch/riscv/tlb.hh 10 files changed, 234 insertions(+), 2 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved Ayaz Akram: Looks good to me, but someone else must approve kokoro: Regressions pass diff --git a/src/arch/riscv/PMAChecker.py b/src/arch/riscv/PMAChecker.py new file mode 100644 index 000..12b1ca3 --- /dev/null +++ b/src/arch/riscv/PMAChecker.py @@ -0,0 +1,45 @@ +# -*- mode:python -*- + +# Copyright (c) 2021 Huawei International +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.SimObject import SimObject +from m5.params import * +from m5.proxy import * + +class PMAChecker(SimObject): +type = 'PMAChecker' +cxx_header = 'arch/riscv/pma_checker.hh' +uncacheable = VectorParam.AddrRange([], "Uncacheable address ranges") diff --git a/src/arch/riscv/RiscvMMU.py b/src/arch/riscv/RiscvMMU.py index 238e11e..4ff477e 100644 --- a/src/arch/riscv/RiscvMMU.py +++ b/src/arch/riscv/RiscvMMU.py @@ -37,6 +37,7 @@ from m5.objects.BaseMMU import BaseMMU from m5.objects.RiscvTLB import RiscvTLB +from m5.objects.PMAChecker import PMAChecker class RiscvMMU(BaseMMU): type = 'RiscvMMU' @@ -44,6 +45,7 @@ cxx_header = 'arch/riscv/mmu.hh' itb = RiscvTLB() dtb = RiscvTLB() +pma_checker = PMAChecker() @classmethod def walkerPorts(cls): diff --git a/src/arch/riscv/RiscvTLB.py b/src/arch/riscv/RiscvTLB.py index 4844feb..b419262 100644 --- a/src/arch/riscv/RiscvTLB.py +++ b/src/arch/riscv/RiscvTLB.py @@ -2,6 +2,7 @@ # Copyright (c) 2007 MIPS Technologies, Inc. # Copyright (c) 2020 Barkhausen Institut +# Copyright (c) 2021 Huawei International # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -41,6 +42,8 @@ system = Param.System(Parent.any, "system object") num_squash_per_
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: FS Linux config file for RISC-V
Peter Yuen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41033 )
Change subject: arch-riscv: FS Linux config file for RISC-V
..
arch-riscv: FS Linux config file for RISC-V
This file is added to provide a clean starter for RISC-V FS Linux
configuration.
Change-Id: Ifd401761be86758340f26edd00a5ab1ca51e6938
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41033
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Reviewed-by: Ayaz Akram
Maintainer: Jason Lowe-Power
---
A configs/example/riscv/fs_linux.py
1 file changed, 221 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Ayaz Akram: Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/example/riscv/fs_linux.py
b/configs/example/riscv/fs_linux.py
new file mode 100644
index 000..3d40061
--- /dev/null
+++ b/configs/example/riscv/fs_linux.py
@@ -0,0 +1,221 @@
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
+# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import optparse
+import sys
+
+import m5
+from m5.defines import buildEnv
+from m5.objects import *
+from m5.util import addToPath, fatal, warn
+from m5.util.fdthelper import *
+
+addToPath('../../')
+
+from ruby import Ruby
+
+from common.FSConfig import *
+from common.SysPaths import *
+from common.Benchmarks import *
+from common import Simulation
+from common import CacheConfig
+from common import CpuConfig
+from common import MemConfig
+from common import ObjectList
+from common.Caches import *
+from common import Options
+
+# - Add Options #
+parser = optparse.OptionParser()
+Options.addCommonOptions(parser)
+Options.addFSOptions(parser)
+
+# NOTE: Ruby in FS Linux has not been tested yet
+if '--ruby' in sys.argv:
+Ruby.define_options(parser)
+
+# Parse Options --- #
+(options, args) = parser.parse_args()
+
+if args:
+print("Error: script doesn't take any positional arguments")
+sys.exit(1)
+
+# CPU and Memory
+(CPUClass, mem_mode, FutureClass) = Simulation.setCPUClass(options)
+MemClass = Simulation.setMemClass(options)
+
+np = options.num_cpus
+
+# Setup System #
+# Edit this section to customize peripherals and system settings
+system = System()
+mdesc = SysConfig(disks=options.disk_image, rootdev=options.root_device,
+mem=options.mem_size, os_type=options.os_type)
+system.mem_mode = mem_mode
+system.mem_ranges = [AddrRange(start=0x8000, size=mdesc.mem())]
+
+system.workload = RiscvBareMeta
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Fixing interrupt handling order and effect of mideleg
Peter Yuen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40076 )
Change subject: arch-riscv: Fixing interrupt handling order and effect of
mideleg
..
arch-riscv: Fixing interrupt handling order and effect of mideleg
This patch fixes the issues listed in:
https://gem5.atlassian.net/browse/GEM5-887
https://gem5.atlassian.net/browse/GEM5-889
The code change has been verified by booting FS linux.
Software, timer and external interrupts work as expected.
Change-Id: I6ce4fc843d2e0338355152c3fc33c966d6b4a481
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40076
Reviewed-by: Ayaz Akram
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/riscv/interrupts.hh
1 file changed, 19 insertions(+), 6 deletions(-)
Approvals:
Ayaz Akram: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh
index f07e7d7..142911e 100644
--- a/src/arch/riscv/interrupts.hh
+++ b/src/arch/riscv/interrupts.hh
@@ -66,16 +66,24 @@
{
INTERRUPT mask = 0;
STATUS status = tc->readMiscReg(MISCREG_STATUS);
+INTERRUPT mideleg = tc->readMiscReg(MISCREG_MIDELEG);
+INTERRUPT sideleg = tc->readMiscReg(MISCREG_SIDELEG);
PrivilegeMode prv = (PrivilegeMode)tc->readMiscReg(MISCREG_PRV);
switch (prv) {
case PRV_U:
-mask.mei = mask.mti = mask.msi = 1;
-mask.sei = mask.sti = mask.ssi = 1;
+mask.mei = (!sideleg.mei) | (sideleg.mei & status.uie);
+mask.mti = (!sideleg.mti) | (sideleg.mti & status.uie);
+mask.msi = (!sideleg.msi) | (sideleg.msi & status.uie);
+mask.sei = (!sideleg.sei) | (sideleg.sei & status.uie);
+mask.sti = (!sideleg.sti) | (sideleg.sti & status.uie);
+mask.ssi = (!sideleg.ssi) | (sideleg.ssi & status.uie);
if (status.uie)
mask.uei = mask.uti = mask.usi = 1;
break;
case PRV_S:
-mask.mei = mask.mti = mask.msi = 1;
+mask.mei = (!mideleg.mei) | (mideleg.mei & status.sie);
+mask.mti = (!mideleg.mti) | (mideleg.mti & status.sie);
+mask.msi = (!mideleg.msi) | (mideleg.msi & status.sie);
if (status.sie)
mask.sei = mask.sti = mask.ssi = 1;
mask.uei = mask.uti = mask.usi = 0;
@@ -105,9 +113,14 @@
{
assert(checkInterrupts());
std::bitset mask = globalMask();
-for (int c = 0; c < NumInterruptTypes; c++)
-if (checkInterrupt(c) && mask[c])
-return std::make_shared(c);
+const std::vector interrupt_order {
+INT_EXT_MACHINE, INT_TIMER_MACHINE, INT_SOFTWARE_MACHINE,
+INT_EXT_SUPER, INT_TIMER_SUPER, INT_SOFTWARE_SUPER,
+INT_EXT_USER, INT_TIMER_USER, INT_SOFTWARE_USER
+};
+for (const int &id : interrupt_order)
+if (checkInterrupt(id) && mask[id])
+return std::make_shared(id);
return NoFault;
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40076
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6ce4fc843d2e0338355152c3fc33c966d6b4a481
Gerrit-Change-Number: 40076
Gerrit-PatchSet: 3
Gerrit-Owner: Peter Yuen
Gerrit-Reviewer: Ayaz Akram
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Peter Yuen
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: Check for "make" when using LTO with gcc.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41773 )
Change subject: scons: Check for "make" when using LTO with gcc.
..
scons: Check for "make" when using LTO with gcc.
gcc uses "make" to parallelize LTO. If we're using gcc and make isn't
found, we have to use single threaded LTO instead. A warning will let
the user know what's happening and that they might want to correct the
situation.
Technically gcc can use the MAKE environment variable to override the
program it uses, although I assume it still has to be "make" compatible.
Given the fairly low likelihood that someone will need that override and
the fact that scons won't pipe that variable through unless we plumb it
up, we'll just ignore that for now.
Change-Id: I891b213ece2a75bd8a915ee91f4130458dab397b
---
M SConstruct
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/SConstruct b/SConstruct
index cc3af90..19a5da9 100755
--- a/SConstruct
+++ b/SConstruct
@@ -360,14 +360,24 @@
# Add the appropriate Link-Time Optimization (LTO) flags
# unless LTO is explicitly turned off.
if not GetOption('no_lto'):
+# g++ uses "make" to parallelize LTO. The program can be overriden
with
+# the environment variable "MAKE", but we currently make no
attempt to
+# plumb that variable through.
+parallelism = ''
+if main.Detect('make'):
+parallelism = '=%d' % GetOption('num_jobs')
+else:
+warning('"make" not found, link time optimization will be '
+'single threaded.')
+
# Pass the LTO flag when compiling to produce GIMPLE
# output, we merely create the flags here and only append
# them later
-main['LTO_CCFLAGS'] = ['-flto=%d' % GetOption('num_jobs')]
+main['LTO_CCFLAGS'] = ['-flto%s' % parallelism]
# Use the same amount of jobs for LTO as we are running
# scons with
-main['LTO_LDFLAGS'] = ['-flto=%d' % GetOption('num_jobs')]
+main['LTO_LDFLAGS'] = ['-flto%s' % parallelism]
main.Append(TCMALLOC_CCFLAGS=['-fno-builtin-malloc', '-fno-builtin-calloc',
'-fno-builtin-realloc', '-fno-builtin-free'])
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I891b213ece2a75bd8a915ee91f4130458dab397b
Gerrit-Change-Number: 41773
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] gem5 v20.1.0.4 Hotfix Release
Dear all, A bug was identified in gem5 v20.1 that resulted in gem5 failing to compile with scons 4.0.1 and 4.1.0: https://gem5.atlassian.net/browse/GEM5-916 As such a hotfix (v20.1.0.4) has been released. This fix can be obtained by pulling the latest version of gem5 via the git stable branch. The fix will ensure gem5 functions correctly on the latest scons release. Special thanks to Hoa Nguyen for finding and fixing this bug! Dr. Bobby R. Bruce Room 2235, Kemper Hall, UC Davis Davis, CA, 95616 web: https://www.bobbybruce.net ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[hotfix-scons-4]: misc: Updated the RELEASE-NOTES and version number
Bobby R. Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/41713 ) Change subject: misc: Updated the RELEASE-NOTES and version number .. misc: Updated the RELEASE-NOTES and version number Updated the RELEASE-NOTES.md and version number for the v20.1.0.3 hotfix release. Change-Id: Iaefed86cb176c3adcd66d101ac3155d30528b025 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41713 Maintainer: Bobby R. Bruce Reviewed-by: Jason Lowe-Power Reviewed-by: Hoa Nguyen Tested-by: kokoro --- M RELEASE-NOTES.md M src/Doxyfile M src/base/version.cc 3 files changed, 7 insertions(+), 2 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved Hoa Nguyen: Looks good to me, approved Bobby R. Bruce: Looks good to me, approved kokoro: Regressions pass diff --git a/RELEASE-NOTES.md b/RELEASE-NOTES.md index c84d9b4..3f17091 100644 --- a/RELEASE-NOTES.md +++ b/RELEASE-NOTES.md @@ -1,3 +1,8 @@ +# Version 20.1.0.4 + +**[HOTFIX]** [gem5 was failing to build with SCons 4.0.1 and 4.1.0](https://gem5.atlassian.net/browse/GEM5-916). +This hotfix makes the necessary changes to `site_scons/site_tools/default.py` for gem5 to compile successfully on these versions of SCons. + # Version 20.1.0.3 **[HOTFIX]** A patch was apply to fix an [error where booting Linux stalled when using the ARM ISA](https://gem5.atlassian.net/browse/GEM5-901). diff --git a/src/Doxyfile b/src/Doxyfile index ddc3933..4ad0ea5 100644 --- a/src/Doxyfile +++ b/src/Doxyfile @@ -31,7 +31,7 @@ # This could be handy for archiving the generated documentation or # if some version control system is used. -PROJECT_NUMBER = v20.1.0.3 +PROJECT_NUMBER = v20.1.0.4 # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) # base path where the generated documentation will be put. diff --git a/src/base/version.cc b/src/base/version.cc index d30ddd1..0a34488 100644 --- a/src/base/version.cc +++ b/src/base/version.cc @@ -29,4 +29,4 @@ /** * @ingroup api_base_utils */ -const char *gem5Version = "20.1.0.3"; +const char *gem5Version = "20.1.0.4"; -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41713 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: hotfix-scons-4 Gerrit-Change-Id: Iaefed86cb176c3adcd66d101ac3155d30528b025 Gerrit-Change-Number: 41713 Gerrit-PatchSet: 2 Gerrit-Owner: Bobby R. Bruce Gerrit-Reviewer: Bobby R. Bruce Gerrit-Reviewer: Hoa Nguyen Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[hotfix-scons-4]: scons: Fixing build errors with scons 4.0.1 and 4.1.0
Bobby R. Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41594 )
Change subject: scons: Fixing build errors with scons 4.0.1 and 4.1.0
..
scons: Fixing build errors with scons 4.0.1 and 4.1.0
SCons failed to find m5 module while loading m5.util.terminal
from site_scons/gem5_scons/util.py.
This results in the current version of gem5 stable failed to
build with scons 4.0.1 and 4.1.0.
The nature of the bug and the explaination for the fix can be
found here,
https://gem5-review.googlesource.com/c/public/gem5/+/38616
Jira: https://gem5.atlassian.net/browse/GEM5-916
Change-Id: I3817f39ebc3021fb6fc89bcd09a96999f8ca2841
Signed-off-by: Hoa Nguyen
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41594
Reviewed-by: Bobby R. Bruce
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M SConstruct
M site_scons/site_tools/default.py
2 files changed, 1 insertion(+), 7 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index 0d8159b..bb038b8 100755
--- a/SConstruct
+++ b/SConstruct
@@ -139,7 +139,7 @@
#
-main = Environment()
+main = Environment(tools=['default', 'git'])
from gem5_scons.util import get_termcap
termcap = get_termcap()
diff --git a/site_scons/site_tools/default.py
b/site_scons/site_tools/default.py
index 1965a20..88a6932 100644
--- a/site_scons/site_tools/default.py
+++ b/site_scons/site_tools/default.py
@@ -78,15 +78,9 @@
# as well
env.AppendENVPath('PYTHONPATH', extra_python_paths)
-gem5_tool_list = [
-'git',
-]
-
def generate(env):
common_config(env)
SCons.Tool.default.generate(env)
-for tool in gem5_tool_list:
-SCons.Tool.Tool(tool)(env)
def exists(env):
return 1
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41594
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Gerrit-Project: public/gem5
Gerrit-Branch: hotfix-scons-4
Gerrit-Change-Id: I3817f39ebc3021fb6fc89bcd09a96999f8ca2841
Gerrit-Change-Number: 41594
Gerrit-PatchSet: 4
Gerrit-Owner: Hoa Nguyen
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-CC: Jason Lowe-Power
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: base-stats,python: Add Units to the Python Stats
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/41754 ) Change subject: base-stats,python: Add Units to the Python Stats .. base-stats,python: Add Units to the Python Stats Change-Id: Ic8d3c9a5c2bb7fbe51b8672b74b0e5fb17906a5e --- M src/python/m5/pystats/loader.py 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/python/m5/pystats/loader.py b/src/python/m5/pystats/loader.py index aae223d..84bc884 100644 --- a/src/python/m5/pystats/loader.py +++ b/src/python/m5/pystats/loader.py @@ -104,7 +104,7 @@ def __get_scaler(statistic: _m5.stats.ScalarInfo) -> Scalar: value = statistic.value -unit = None # TODO https://gem5.atlassian.net/browse/GEM5-850. +unit = statistic.unit description = statistic.desc # ScalarInfo uses the C++ `double`. datatype = StorageType["f64"] @@ -117,7 +117,7 @@ ) def __get_distribution(statistic: _m5.stats.DistInfo) -> Distribution: -unit = None # TODO https://gem5.atlassian.net/browse/GEM5-850. +unit = statistic.unit description = statistic.desc value = statistic.values bin_size = statistic.bucket_size @@ -154,7 +154,7 @@ for index in range(statistic.size): # All the values in a Vector are Scalar values value = statistic.value[index] -unit = None # TODO https://gem5.atlassian.net/browse/GEM5-850. +unit = statistic.unit description = statistic.subdescs[index] # ScalarInfo uses the C++ `double`. datatype = StorageType["f64"] -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/41754 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ic8d3c9a5c2bb7fbe51b8672b74b0e5fb17906a5e Gerrit-Change-Number: 41754 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: base-stats,python: Expose a stat's unit via PyBind11
Bobby R. Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41753 )
Change subject: base-stats,python: Expose a stat's unit via PyBind11
..
base-stats,python: Expose a stat's unit via PyBind11
Change-Id: I77df868a6bc92e5bb0a39592b5aca8e0d259bb05
---
M src/python/pybind11/stats.cc
1 file changed, 3 insertions(+), 0 deletions(-)
diff --git a/src/python/pybind11/stats.cc b/src/python/pybind11/stats.cc
index 1e6773f..f1b1e9c 100644
--- a/src/python/pybind11/stats.cc
+++ b/src/python/pybind11/stats.cc
@@ -132,6 +132,9 @@
py::class_>(
m, "Info")
.def_readwrite("name", &Stats::Info::name)
+.def_property_readonly("unit", [](const Stats::Info &info) {
+return info.unit->getUnitString();
+})
.def_readonly("desc", &Stats::Info::desc)
.def_readonly("id", &Stats::Info::id)
.def_property_readonly("flags", [](const Stats::Info &info) {
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I77df868a6bc92e5bb0a39592b5aca8e0d259bb05
Gerrit-Change-Number: 41753
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby R. Bruce
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch,cpu: Create register class descriptors.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41733 )
Change subject: arch,cpu: Create register class descriptors.
..
arch,cpu: Create register class descriptors.
These currently only hold the number of registers in a particular class,
but can be extended in the future to hold other information about each
class. The ISA class holds a vector of descriptors which other parts of
gem5 can retrieve to set up storage for each class, etc.
Currently, the RegClass enum is used to explicitly index into the vector
of descriptors to get information about a particular class. Once enough
information is stored in the descriptors, the other parts of gem5 should
be able to set up for each register class generically, and the ISAs will
be able to leave out or create new register classes without having to
set up global plumbing for it.
The more immediate benefit is that this should (mostly) parameterize
away the ISA register constants to break another TheISA style
dependency. Currently a global set of descriptors are set up in the
BaseISA class using the old TheISA constants, but it should be easy to
break those out and make the ISAs set up their own descriptors. That
will bring arch/registers.hh significantly closer to being eliminated.
Change-Id: I6d6d1256288f880391246b71045482a4a03c4198
---
M src/arch/generic/isa.hh
M src/cpu/minor/execute.cc
M src/cpu/minor/scoreboard.cc
M src/cpu/minor/scoreboard.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/free_list.cc
M src/cpu/o3/regfile.cc
M src/cpu/o3/regfile.hh
M src/cpu/o3/rename_impl.hh
M src/cpu/o3/rename_map.cc
M src/cpu/o3/rename_map.hh
M src/cpu/reg_class.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
M src/cpu/thread_context.cc
15 files changed, 249 insertions(+), 167 deletions(-)
diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index 4c717c7..8b8b2db 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -40,23 +40,44 @@
#ifndef __ARCH_GENERIC_ISA_HH__
#define __ARCH_GENERIC_ISA_HH__
+#include
+
+#include "arch/registers.hh"
+#include "cpu/reg_class.hh"
#include "sim/sim_object.hh"
class ThreadContext;
class BaseISA : public SimObject
{
+ public:
+typedef std::vector RegClasses;
+
protected:
using SimObject::SimObject;
ThreadContext *tc = nullptr;
+RegClasses _regClasses = {
+#if THE_ISA != NULL_ISA
+{ TheISA::NumIntRegs },
+{ TheISA::NumFloatRegs },
+{ TheISA::NumVecRegs },
+{ TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg },
+{ TheISA::NumVecPredRegs },
+{ TheISA::NumCCRegs },
+{ TheISA::NumMiscRegs }
+#endif // THE_ISA != NULL_ISA
+};
+
public:
virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext
*old_tc) {}
virtual void setThreadContext(ThreadContext *_tc) { tc = _tc; }
virtual uint64_t getExecutingAsid() const { return 0; }
virtual bool inUserMode() const = 0;
+
+const RegClasses ®Classes() const { return _regClasses; }
};
#endif // __ARCH_GENERIC_ISA_HH__
diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc
index 3eb7811..7575cf9 100644
--- a/src/cpu/minor/execute.cc
+++ b/src/cpu/minor/execute.cc
@@ -175,8 +175,10 @@
name_ + ".inputBuffer" + tid_str, "insts",
params.executeInputBufferSize));
+const auto ®Classes =
cpu.threads[tid]->getIsaPtr()->regClasses();
+
/* Scoreboards */
-scoreboard.push_back(Scoreboard(name_ + ".scoreboard" + tid_str));
+scoreboard.emplace_back(name_ + ".scoreboard" + tid_str,
regClasses);
/* In-flight instruction records */
executeInfo[tid].inFlightInsts = new Queue writingInst;
public:
-Scoreboard(const std::string &name) :
+Scoreboard(const std::string &name,
+const BaseISA::RegClasses& reg_classes) :
Named(name),
-numRegs(TheISA::NumIntRegs + TheISA::NumCCRegs +
-TheISA::NumFloatRegs +
-(TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg) +
-TheISA::NumVecPredRegs),
+regClasses(reg_classes),
+intRegOffset(0),
+floatRegOffset(intRegOffset + reg_classes.at(IntRegClass).size()),
+ccRegOffset(floatRegOffset + reg_classes.at(FloatRegClass).size()),
+vecRegOffset(ccRegOffset + reg_classes.at(CCRegClass).size()),
+vecPredRegOffset(vecRegOffset +
reg_classes.at(VecElemClass).size()),
+numRegs(vecPredRegOffset + reg_classes.at(VecPredRegClass).size()),
numResults(numRegs, 0),
numUnpredictableResults(numRegs, 0),
fuIndices(numRegs, 0),
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 3b9f991..3cebbf1 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -95,6 +95,7 @@
params.numPhysVecRegs,
params.numPhysVecPredRegs,
params.numP
[gem5-dev] Change in gem5/gem5[develop]: arch: Move setting up RegClassInfos into the arches.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41734 )
Change subject: arch: Move setting up RegClassInfos into the arches.
..
arch: Move setting up RegClassInfos into the arches.
Also remove no longer global constants from arch/registers.hh if they
are no longer used locally.
Change-Id: I1d1589db3dd4c51a5ec11e32348d394261e36d17
---
M src/arch/arm/freebsd/se_workload.hh
M src/arch/arm/htm.cc
M src/arch/arm/htm.hh
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/isa_device.cc
M src/arch/arm/nativetrace.cc
M src/arch/arm/process.cc
M src/arch/arm/registers.hh
M src/arch/arm/tracers/tarmac_base.cc
M src/arch/arm/tracers/tarmac_record.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
M src/arch/generic/isa.hh
M src/arch/mips/isa.cc
M src/arch/mips/isa.hh
M src/arch/mips/registers.hh
M src/arch/mips/utility.cc
M src/arch/power/isa.cc
M src/arch/power/isa.hh
M src/arch/power/isa/includes.isa
M src/arch/power/registers.hh
M src/arch/power/se_workload.hh
M src/arch/power/utility.cc
M src/arch/riscv/isa.cc
M src/arch/riscv/registers.hh
M src/arch/sparc/insts/static_inst.cc
M src/arch/sparc/interrupts.hh
M src/arch/sparc/isa.cc
M src/arch/sparc/isa.hh
M src/arch/sparc/isa/includes.isa
M src/arch/sparc/process.cc
M src/arch/sparc/registers.hh
M src/arch/sparc/remote_gdb.cc
M src/arch/sparc/tlb.cc
M src/arch/sparc/utility.cc
M src/arch/sparc/utility.hh
M src/arch/x86/isa.cc
M src/arch/x86/registers.hh
39 files changed, 126 insertions(+), 106 deletions(-)
diff --git a/src/arch/arm/freebsd/se_workload.hh
b/src/arch/arm/freebsd/se_workload.hh
index a228ee0..6f13201 100644
--- a/src/arch/arm/freebsd/se_workload.hh
+++ b/src/arch/arm/freebsd/se_workload.hh
@@ -34,8 +34,8 @@
#ifndef __ARCH_ARM_FREEBSD_SE_WORKLOAD_HH__
#define __ARCH_ARM_FREEBSD_SE_WORKLOAD_HH__
+#include "arch/arm/ccregs.hh"
#include "arch/arm/freebsd/freebsd.hh"
-#include "arch/arm/registers.hh"
#include "arch/arm/se_workload.hh"
#include "params/ArmEmuFreebsd.hh"
#include "sim/syscall_desc.hh"
diff --git a/src/arch/arm/htm.cc b/src/arch/arm/htm.cc
index 276406a..3129b3f 100644
--- a/src/arch/arm/htm.cc
+++ b/src/arch/arm/htm.cc
@@ -36,6 +36,9 @@
*/
#include "arch/arm/htm.hh"
+
+#include "arch/arm/intregs.hh"
+#include "arch/arm/miscregs.hh"
#include "cpu/thread_context.hh"
void
@@ -70,7 +73,7 @@
//tme_checkpoint->iccPmrEl1 = tc->readMiscReg(MISCREG_ICC_PMR_EL1);
nzcv = tc->readMiscReg(MISCREG_NZCV);
daif = tc->readMiscReg(MISCREG_DAIF);
-for (auto n = 0; n < NumIntArchRegs; n++) {
+for (auto n = 0; n < NUM_ARCH_INTREGS; n++) {
x[n] = tc->readIntReg(n);
}
// TODO first detect if FP is enabled at this EL
@@ -97,7 +100,7 @@
//tc->setMiscReg(MISCREG_ICC_PMR_EL1, tme_checkpoint->iccPmrEl1);
tc->setMiscReg(MISCREG_NZCV, nzcv);
tc->setMiscReg(MISCREG_DAIF, daif);
-for (auto n = 0; n < NumIntArchRegs; n++) {
+for (auto n = 0; n < NUM_ARCH_INTREGS; n++) {
tc->setIntReg(n, x[n]);
}
// TODO first detect if FP is enabled at this EL
diff --git a/src/arch/arm/htm.hh b/src/arch/arm/htm.hh
index 3fa7c1d..d32c58e 100644
--- a/src/arch/arm/htm.hh
+++ b/src/arch/arm/htm.hh
@@ -44,6 +44,7 @@
* ISA-specific types for hardware transactional memory.
*/
+#include "arch/arm/intregs.hh"
#include "arch/arm/registers.hh"
#include "arch/generic/htm.hh"
#include "base/types.hh"
@@ -70,7 +71,7 @@
private:
uint8_t rt; // TSTART destination register
Addr nPc; // Fallback instruction address
-std::array x; // General purpose registers
+std::array x; // General purpose registers
std::array z; // Vector registers
std::array p; // Predicate registers
Addr sp; // Stack Pointer at current EL
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index c7f82e0..039224f 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -47,6 +47,7 @@
#include "arch/arm/tlbi_op.hh"
#include "cpu/base.hh"
#include "cpu/checker/cpu.hh"
+#include "cpu/reg_class.hh"
#include "debug/Arm.hh"
#include "debug/MiscRegs.hh"
#include "dev/arm/generic_timer.hh"
@@ -65,6 +66,16 @@
pmu(p.pmu), impdefAsNop(p.impdef_nop),
afterStartup(false)
{
+_regClasses.insert(_regClasses.end(), {
+{ NUM_INTREGS },
+{ 0 },
+{ NumVecRegs },
+{ NumVecRegs * TheISA::NumVecElemPerVecReg },
+{ NumVecPredRegs },
+{ NUM_CCREGS },
+{ NUM_MISCREGS }
+});
+
miscRegs[MISCREG_SCTLR_RST] = 0;
// Hook up a dummy device if we haven't been configured with a
@@ -484,7 +495,7 @@
RegVal
ISA::readMiscRegNoEffect(int misc_reg) const
{
-assert(misc_reg < NumMiscRegs);
+assert(misc_reg < NUM_MISCREGS);
const auto ® = lookUpMiscReg[misc_reg]; // bit masks
const auto &map = getMiscIndices(misc_reg);
@@ -810,7 +821,7 @@
void
[gem5-dev] Change in gem5/gem5[develop]: arch-sparc: Move non-public values out of registers.hh.
Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/41741 ) Change subject: arch-sparc: Move non-public values out of registers.hh. .. arch-sparc: Move non-public values out of registers.hh. Change-Id: If5f1c09b3988bc009821330ca128ff22a54c0e88 --- M src/arch/sparc/decoder.hh M src/arch/sparc/faults.cc M src/arch/sparc/insts/static_inst.cc M src/arch/sparc/interrupts.hh M src/arch/sparc/isa.cc M src/arch/sparc/isa.hh M src/arch/sparc/isa/includes.isa M src/arch/sparc/linux/linux.hh M src/arch/sparc/nativetrace.cc M src/arch/sparc/process.cc M src/arch/sparc/registers.hh A src/arch/sparc/regs/float.hh A src/arch/sparc/regs/int.hh R src/arch/sparc/regs/misc.hh M src/arch/sparc/remote_gdb.cc M src/arch/sparc/se_workload.cc M src/arch/sparc/se_workload.hh M src/arch/sparc/tlb.cc M src/arch/sparc/ua2005.cc M src/arch/sparc/utility.cc M src/arch/sparc/utility.hh 21 files changed, 153 insertions(+), 67 deletions(-) diff --git a/src/arch/sparc/decoder.hh b/src/arch/sparc/decoder.hh index ece3b9c..6e2e203 100644 --- a/src/arch/sparc/decoder.hh +++ b/src/arch/sparc/decoder.hh @@ -31,7 +31,6 @@ #include "arch/generic/decode_cache.hh" #include "arch/generic/decoder.hh" -#include "arch/sparc/registers.hh" #include "arch/sparc/types.hh" #include "cpu/static_inst.hh" #include "debug/Decode.hh" diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index a80e649..408c5c4 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -33,6 +33,7 @@ #include "arch/sparc/mmu.hh" #include "arch/sparc/process.hh" #include "arch/sparc/se_workload.hh" +#include "arch/sparc/sparc_traits.hh" #include "arch/sparc/types.hh" #include "base/bitfield.hh" #include "base/trace.hh" diff --git a/src/arch/sparc/insts/static_inst.cc b/src/arch/sparc/insts/static_inst.cc index 65a38ff..72e4c6b 100644 --- a/src/arch/sparc/insts/static_inst.cc +++ b/src/arch/sparc/insts/static_inst.cc @@ -29,8 +29,8 @@ #include "arch/sparc/insts/static_inst.hh" -#include "arch/sparc/miscregs.hh" -#include "arch/sparc/registers.hh" +#include "arch/sparc/regs/int.hh" +#include "arch/sparc/regs/misc.hh" #include "base/bitunion.hh" namespace SparcISA diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh index 18646fa..cd1e5dc 100644 --- a/src/arch/sparc/interrupts.hh +++ b/src/arch/sparc/interrupts.hh @@ -32,8 +32,7 @@ #include "arch/generic/interrupts.hh" #include "arch/sparc/faults.hh" #include "arch/sparc/isa_traits.hh" -#include "arch/sparc/miscregs.hh" -#include "arch/sparc/registers.hh" +#include "arch/sparc/regs/misc.hh" #include "cpu/thread_context.hh" #include "debug/Interrupt.hh" #include "params/SparcInterrupts.hh" diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc index 12e2908..6fe79be 100644 --- a/src/arch/sparc/isa.cc +++ b/src/arch/sparc/isa.cc @@ -31,7 +31,10 @@ #include "arch/sparc/asi.hh" #include "arch/sparc/decoder.hh" #include "arch/sparc/interrupts.hh" -#include "arch/sparc/miscregs.hh" +#include "arch/sparc/regs/float.hh" +#include "arch/sparc/regs/int.hh" +#include "arch/sparc/regs/misc.hh" +#include "arch/sparc/sparc_traits.hh" #include "base/bitfield.hh" #include "base/trace.hh" #include "cpu/base.hh" diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh index 2d75b0a..54cd763 100644 --- a/src/arch/sparc/isa.hh +++ b/src/arch/sparc/isa.hh @@ -33,7 +33,9 @@ #include #include "arch/generic/isa.hh" -#include "arch/sparc/miscregs.hh" +#include "arch/sparc/regs/int.hh" +#include "arch/sparc/regs/misc.hh" +#include "arch/sparc/sparc_traits.hh" #include "arch/sparc/types.hh" #include "cpu/reg_class.hh" #include "sim/sim_object.hh" diff --git a/src/arch/sparc/isa/includes.isa b/src/arch/sparc/isa/includes.isa index c2c44a7..679ddf3 100644 --- a/src/arch/sparc/isa/includes.isa +++ b/src/arch/sparc/isa/includes.isa @@ -47,8 +47,8 @@ #include "arch/sparc/insts/unimp.hh" #include "arch/sparc/insts/unknown.hh" #include "arch/sparc/isa_traits.hh" -#include "arch/sparc/miscregs.hh" -#include "arch/sparc/registers.hh" +#include "arch/sparc/regs/int.hh" +#include "arch/sparc/regs/misc.hh" #include "base/condcodes.hh" #include "base/logging.hh" #include "cpu/static_inst.hh" diff --git a/src/arch/sparc/linux/linux.hh b/src/arch/sparc/linux/linux.hh index 431ec06..8d43c91 100644 --- a/src/arch/sparc/linux/linux.hh +++ b/src/arch/sparc/linux/linux.hh @@ -29,6 +29,7 @@ #ifndef __ARCH_SPARC_LINUX_LINUX_HH__ #define __ARCH_SPARC_LINUX_LINUX_HH__ +#include "arch/sparc/regs/int.hh" #include "arch/sparc/utility.hh" #include "kern/linux/linux.hh" diff --git a/src/arch/sparc/nativetrace.cc b/src/arch/sparc/nativetrace.cc index 32ce10e..f4de60a 100644 --- a/src/arch/sparc/nativetrace.cc +++ b/src/arch/sparc/nativetrace.cc @@ -29,7 +29,7 @@ #include "arch/sparc/nativetrace.hh" #include "arch/sparc/isa_traits.hh" -#include "arch/sparc/re
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Pull everything not purely public out of registers.hh.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41738 )
Change subject: arch-arm: Pull everything not purely public out of
registers.hh.
..
arch-arm: Pull everything not purely public out of registers.hh.
There are currently only two types of values exported from registers.hh,
vector register definitions, and the zero reg index. The ZeroReg
constant is still defined in registers.hh. The vector register
information has been moved into a new file called arch/arm/regs/vec.hh
since it's used internally by the ISA itself, and then included in
registers.hh so it can be consumed externally too.
Change-Id: I31d8dd5bcb21818efa32ccc42f26b0e598a2c88e
---
M src/arch/arm/registers.hh
M src/arch/arm/regs/int.hh
A src/arch/arm/regs/vec.hh
3 files changed, 112 insertions(+), 61 deletions(-)
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 15a84a5..8d5cfdf 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -42,73 +42,13 @@
#define __ARCH_ARM_REGISTERS_HH__
#include "arch/arm/regs/int.hh"
-#include "arch/generic/vec_pred_reg.hh"
-#include "arch/generic/vec_reg.hh"
+#include "arch/arm/regs/vec.hh"
namespace ArmISA
{
-// Number of VecElem per Vector Register considering only pre-SVE
-// Advanced SIMD registers.
-constexpr unsigned NumVecElemPerNeonVecReg = 4;
-// Number of VecElem per Vector Register, computed based on the vector
length
-constexpr unsigned NumVecElemPerVecReg = MaxSveVecLenInWords;
-
-using VecElem = uint32_t;
-using VecReg = ::VecRegT;
-using ConstVecReg = ::VecRegT;
-using VecRegContainer = VecReg::Container;
-
-using VecPredReg = ::VecPredRegT;
-using ConstVecPredReg = ::VecPredRegT;
-using VecPredRegContainer = VecPredReg::Container;
-
-// Vec, PredVec
-// NumFloatV7ArchRegs: This in theory should be 32.
-// However in A32 gem5 is splitting double register accesses in two
-// subsequent single register ones. This means we would use a index
-// bigger than 31 when accessing D16-D31.
-const int NumFloatV7ArchRegs = 64; // S0-S31, D0-D31
-const int NumVecV7ArchRegs = 16; // Q0-Q15
-const int NumVecV8ArchRegs = 32; // V0-V31
-const int NumVecSpecialRegs = 8;
-const int NumVecIntrlvRegs = 4;
-const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs +
NumVecIntrlvRegs;
-const int NumVecPredRegs = 18; // P0-P15, FFR, UREG0
-
-// Semantically meaningful register indices
-const int ReturnValueReg = 0;
-const int ReturnValueReg1 = 1;
-const int ReturnValueReg2 = 2;
-const int NumArgumentRegs = 4;
-const int NumArgumentRegs64 = 8;
-const int ArgumentReg0 = 0;
-const int ArgumentReg1 = 1;
-const int ArgumentReg2 = 2;
-const int ArgumentReg3 = 3;
-const int FramePointerReg = 11;
-const int StackPointerReg = INTREG_SP;
-const int ReturnAddressReg = INTREG_LR;
-const int PCReg = INTREG_PC;
-
const int ZeroReg = INTREG_ZERO;
-// Vec, PredVec indices
-const int VecSpecialElem = NumVecV8ArchRegs * NumVecElemPerNeonVecReg;
-const int INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs;
-const int INTRLVREG1 = INTRLVREG0 + 1;
-const int INTRLVREG2 = INTRLVREG0 + 2;
-const int INTRLVREG3 = INTRLVREG0 + 3;
-const int VECREG_UREG0 = 32;
-const int PREDREG_FFR = 16;
-const int PREDREG_UREG0 = 17;
-
-const int SyscallNumReg = ReturnValueReg;
-const int SyscallPseudoReturnReg = ReturnValueReg;
-const int SyscallSuccessReg = ReturnValueReg;
-
} // namespace ArmISA
#endif
diff --git a/src/arch/arm/regs/int.hh b/src/arch/arm/regs/int.hh
index 9f3b5fd..af11993 100644
--- a/src/arch/arm/regs/int.hh
+++ b/src/arch/arm/regs/int.hh
@@ -517,6 +517,25 @@
return reg == INTREG_SPX;
}
+// Semantically meaningful register indices
+const int ReturnValueReg = 0;
+const int ReturnValueReg1 = 1;
+const int ReturnValueReg2 = 2;
+const int NumArgumentRegs = 4;
+const int NumArgumentRegs64 = 8;
+const int ArgumentReg0 = 0;
+const int ArgumentReg1 = 1;
+const int ArgumentReg2 = 2;
+const int ArgumentReg3 = 3;
+const int FramePointerReg = 11;
+const int StackPointerReg = INTREG_SP;
+const int ReturnAddressReg = INTREG_LR;
+const int PCReg = INTREG_PC;
+
+const int SyscallNumReg = ReturnValueReg;
+const int SyscallPseudoReturnReg = ReturnValueReg;
+const int SyscallSuccessReg = ReturnValueReg;
+
}
#endif
diff --git a/src/arch/arm/regs/vec.hh b/src/arch/arm/regs/vec.hh
new file mode 100644
index 000..f00b2db
--- /dev/null
+++ b/src/arch/arm/regs/vec.hh
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2010-2011, 2014, 2016-2019 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that y
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Clean up new FP code in arch/registers.hh.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41735 )
Change subject: arch-riscv: Clean up new FP code in arch/registers.hh.
..
arch-riscv: Clean up new FP code in arch/registers.hh.
Delete unused macros, turn macros into inline functions, simplify them,
comment them, replace custom sign extension with the bitfield.hh
version.
Change-Id: I5962c1f0ac62245385052082e5897e14e4b5adf1
---
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/registers.hh
2 files changed, 60 insertions(+), 70 deletions(-)
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index b4cda8f..90ea03d 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -909,7 +909,8 @@
freg_t fd;
fd = freg(f32_mulAdd(f32(freg(Fs1_bits)),
f32(freg(Fs2_bits)),
-f32(f32(freg(Fs3_bits)).v ^
F32_SIGN)));
+f32(f32(freg(Fs3_bits)).v ^
+mask(31, 31;
Fd_bits = fd.v;
}}, FloatMultAccOp);
0x1: fmsub_d({{
@@ -917,7 +918,8 @@
freg_t fd;
fd = freg(f64_mulAdd(f64(freg(Fs1_bits)),
f64(freg(Fs2_bits)),
-f64(f64(freg(Fs3_bits)).v ^
F64_SIGN)));
+f64(f64(freg(Fs3_bits)).v ^
+mask(63, 63;
Fd_bits = fd.v;
}}, FloatMultAccOp);
}
@@ -925,7 +927,8 @@
0x0: fnmsub_s({{
RM_REQUIRED;
freg_t fd;
-fd = freg(f32_mulAdd(f32(f32(freg(Fs1_bits)).v ^
F32_SIGN),
+fd = freg(f32_mulAdd(f32(f32(freg(Fs1_bits)).v ^
+ mask(31, 31)),
f32(freg(Fs2_bits)),
f32(freg(Fs3_bits;
Fd_bits = fd.v;
@@ -933,7 +936,8 @@
0x1: fnmsub_d({{
RM_REQUIRED;
freg_t fd;
-fd = freg(f64_mulAdd(f64(f64(freg(Fs1_bits)).v ^
F64_SIGN),
+fd = freg(f64_mulAdd(f64(f64(freg(Fs1_bits)).v ^
+ mask(63, 63)),
f64(freg(Fs2_bits)),
f64(freg(Fs3_bits;
Fd_bits = fd.v;
@@ -943,17 +947,21 @@
0x0: fnmadd_s({{
RM_REQUIRED;
freg_t fd;
-fd = freg(f32_mulAdd(f32(f32(freg(Fs1_bits)).v ^
F32_SIGN),
+fd = freg(f32_mulAdd(f32(f32(freg(Fs1_bits)).v ^
+ mask(31, 31)),
f32(freg(Fs2_bits)),
-f32(f32(freg(Fs3_bits)).v ^
F32_SIGN)));
+f32(f32(freg(Fs3_bits)).v ^
+mask(31, 31;
Fd_bits = fd.v;
}}, FloatMultAccOp);
0x1: fnmadd_d({{
RM_REQUIRED;
freg_t fd;
-fd = freg(f64_mulAdd(f64(f64(freg(Fs1_bits)).v ^
F64_SIGN),
+fd = freg(f64_mulAdd(f64(f64(freg(Fs1_bits)).v ^
+ mask(63, 63)),
f64(freg(Fs2_bits)),
-f64(f64(freg(Fs3_bits)).v ^
F64_SIGN)));
+f64(f64(freg(Fs3_bits)).v ^
+mask(63, 63;
Fd_bits = fd.v;
}}, FloatMultAccOp);
}
@@ -1016,42 +1024,26 @@
}}, FloatDivOp);
0x10: decode ROUND_MODE {
0x0: fsgnj_s({{
-freg_t fd;
-fd = freg(fsgnj32(freg(Fs1_bits), freg(Fs2_bits),
- false, false));
-Fd_bits = fd.v;
+Fd_bits = insertBits(Fs1_bits, 31, Fs2_bits);
}}, FloatMiscOp);
0x1: fsgnjn_s({{
-freg_t fd;
-fd = freg(fsgnj32(freg(Fs1_bits), freg(Fs2_bits),
- true, false));
-Fd_bits = fd.v;
+Fd_bits = insertBits(Fs1_bits, 31, ~Fs2_bits);
}}, FloatMiscOp);
0x2: fsgnjx_s({{
-
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Move (most) non-public values out of registers.hh.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41742 )
Change subject: arch-x86: Move (most) non-public values out of registers.hh.
..
arch-x86: Move (most) non-public values out of registers.hh.
The unnecessary DependenceTags is already being removed by another
pending change, and so is left in place for that to remove. Once that's
happened, the regs/*.hh includes can be removed, and there may be other
include related tangles to sort out.
Change-Id: I1c02aa8fd2f2045017609b70523b3519c2a92b03
---
M src/arch/x86/linux/linux.hh
M src/arch/x86/process.cc
M src/arch/x86/registers.hh
M src/arch/x86/regs/float.hh
M src/arch/x86/regs/int.hh
M src/arch/x86/utility.cc
6 files changed, 20 insertions(+), 19 deletions(-)
diff --git a/src/arch/x86/linux/linux.hh b/src/arch/x86/linux/linux.hh
index 697892c..5b46aa1 100644
--- a/src/arch/x86/linux/linux.hh
+++ b/src/arch/x86/linux/linux.hh
@@ -62,7 +62,7 @@
}
if (stack)
-ctc->setIntReg(X86ISA::StackPointerReg, stack);
+ctc->setIntReg(X86ISA::INTREG_RSP, stack);
}
class SyscallABI {};
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index 925c836..cb69af9 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -978,7 +978,7 @@
ThreadContext *tc = system->threads[contextIds[0]];
// Set the stack pointer register
-tc->setIntReg(StackPointerReg, stack_min);
+tc->setIntReg(INTREG_RSP, stack_min);
// There doesn't need to be any segment base added in since we're
dealing
// with the flat segmentation model.
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index 572fa3d..e7c1d9f 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -41,23 +41,14 @@
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
-#include "arch/x86/regs/int.hh"
#include "arch/x86/regs/ccr.hh"
+#include "arch/x86/regs/float.hh"
+#include "arch/x86/regs/int.hh"
#include "arch/x86/regs/misc.hh"
-#include "arch/x86/x86_traits.hh"
namespace X86ISA
{
-const int NumIntArchRegs = NUM_INTREGS;
-const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs +
NumImplicitIntRegs;
-const int NumCCRegs = NUM_CCREGS;
-
-// Each 128 bit xmm register is broken into two effective 64 bit registers.
-// Add 8 for the indices that are mapped over the fp stack
-const int NumFloatRegs =
-NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs + 8;
-
// These enumerate all the registers for dependence tracking.
enum DependenceTags {
// FP_Reg_Base must be large enough to be bigger than any integer
@@ -65,14 +56,12 @@
// we just start at (1 << 7) == 128.
FP_Reg_Base = 128,
CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
-Misc_Reg_Base = CC_Reg_Base + NumCCRegs,
+Misc_Reg_Base = CC_Reg_Base + NUM_CCREGS,
Max_Reg_Index = Misc_Reg_Base + NUM_MISCREGS
};
-// semantically meaningful register indices
-//There is no such register in X86
+// There is no such register in X86.
const int ZeroReg = NUM_INTREGS;
-const int StackPointerReg = INTREG_RSP;
// Not applicable to x86
using VecElem = ::DummyVecElem;
diff --git a/src/arch/x86/regs/float.hh b/src/arch/x86/regs/float.hh
index 6cba603..963c111 100644
--- a/src/arch/x86/regs/float.hh
+++ b/src/arch/x86/regs/float.hh
@@ -148,6 +148,11 @@
{
return FLOATREG_FPR((top + index + 8) % 8);
}
+
+// Each 128 bit xmm register is broken into two effective 64 bit
registers.
+// Add 8 for the indices that are mapped over the fp stack
+const int NumFloatRegs =
+NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs + 8;
}
#endif // __ARCH_X86_FLOATREGS_HH__
diff --git a/src/arch/x86/regs/int.hh b/src/arch/x86/regs/int.hh
index aa26224..87b3190 100644
--- a/src/arch/x86/regs/int.hh
+++ b/src/arch/x86/regs/int.hh
@@ -169,6 +169,10 @@
index = (index - 4) | foldBit;
return (IntRegIndex)index;
}
+
+const int NumIntArchRegs = NUM_INTREGS;
+const int NumIntRegs =
+NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs;
}
#endif // __ARCH_X86_INTREGS_HH__
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index c664620..2872557 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -40,7 +40,10 @@
#include "arch/x86/interrupts.hh"
#include "arch/x86/mmu.hh"
-#include "arch/x86/registers.hh"
+#include "arch/x86/regs/ccr.hh"
+#include "arch/x86/regs/float.hh"
+#include "arch/x86/regs/int.hh"
+#include "arch/x86/regs/misc.hh"
#include "arch/x86/x86_traits.hh"
#include "cpu/base.hh"
#include "fputils/fp80.h"
@@ -79,7 +82,7 @@
for (int i = 0; i < NumFloatRegs; ++i)
dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
//copy condition-code regs
-for (int i = 0; i < NumCCRegs; ++i)
+for (int i = 0; i < NUM_CCREGS; ++i)
dest->setCCRegFla
[gem5-dev] Change in gem5/gem5[develop]: arch-mips: Pull non-public values out of registers.hh.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41739 )
Change subject: arch-mips: Pull non-public values out of registers.hh.
..
arch-mips: Pull non-public values out of registers.hh.
Change-Id: Ia15c75547e74bf2f784fac5b3063159e0c79a00c
---
M src/arch/mips/faults.hh
M src/arch/mips/isa.cc
M src/arch/mips/isa.hh
M src/arch/mips/isa/includes.isa
M src/arch/mips/locked_mem.hh
M src/arch/mips/mt.hh
M src/arch/mips/process.cc
M src/arch/mips/registers.hh
A src/arch/mips/regs/float.hh
A src/arch/mips/regs/int.hh
A src/arch/mips/regs/misc.hh
M src/arch/mips/remote_gdb.cc
M src/arch/mips/remote_gdb.hh
M src/arch/mips/se_workload.hh
M src/arch/mips/utility.cc
M src/arch/mips/utility.hh
16 files changed, 364 insertions(+), 230 deletions(-)
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index 68ba6b6..8df1c5d 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -31,6 +31,7 @@
#define __MIPS_FAULTS_HH__
#include "arch/mips/pra_constants.hh"
+#include "arch/mips/regs/misc.hh"
#include "cpu/thread_context.hh"
#include "debug/MipsPRA.hh"
#include "sim/faults.hh"
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 98dab66..3e4bb1e 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -31,6 +31,9 @@
#include "arch/mips/mt.hh"
#include "arch/mips/mt_constants.hh"
#include "arch/mips/pra_constants.hh"
+#include "arch/mips/regs/float.hh"
+#include "arch/mips/regs/int.hh"
+#include "arch/mips/regs/misc.hh"
#include "base/bitfield.hh"
#include "cpu/base.hh"
#include "cpu/reg_class.hh"
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index e2468ce..7805ea7 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -34,15 +34,15 @@
#include
#include "arch/generic/isa.hh"
-#include "arch/mips/registers.hh"
+#include "arch/mips/regs/misc.hh"
#include "arch/mips/types.hh"
+#include "base/types.hh"
#include "cpu/reg_class.hh"
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
class BaseCPU;
class Checkpoint;
-class EventManager;
struct MipsISAParams;
class ThreadContext;
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index d17bcf6..dd0a1e9 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -55,6 +55,9 @@
#include "arch/mips/mt_constants.hh"
#include "arch/mips/pagetable.hh"
#include "arch/mips/pra_constants.hh"
+#include "arch/mips/regs/float.hh"
+#include "arch/mips/regs/int.hh"
+#include "arch/mips/regs/misc.hh"
#include "arch/mips/tlb.hh"
#include "arch/mips/utility.hh"
#include "base/cprintf.hh"
@@ -79,6 +82,9 @@
#include "arch/mips/mt_constants.hh"
#include "arch/mips/pagetable.hh"
#include "arch/mips/pra_constants.hh"
+#include "arch/mips/regs/float.hh"
+#include "arch/mips/regs/int.hh"
+#include "arch/mips/regs/misc.hh"
#include "arch/mips/tlb.hh"
#include "arch/mips/utility.hh"
#include "base/condcodes.hh"
diff --git a/src/arch/mips/locked_mem.hh b/src/arch/mips/locked_mem.hh
index 73180af..42a4ed2 100644
--- a/src/arch/mips/locked_mem.hh
+++ b/src/arch/mips/locked_mem.hh
@@ -47,7 +47,7 @@
* ISA-specific helper functions for locked memory accesses.
*/
-#include "arch/mips/registers.hh"
+#include "arch/mips/regs/misc.hh"
#include "base/logging.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh
index 9ab3290..56099da 100644
--- a/src/arch/mips/mt.hh
+++ b/src/arch/mips/mt.hh
@@ -41,7 +41,7 @@
#include "arch/mips/isa_traits.hh"
#include "arch/mips/mt_constants.hh"
#include "arch/mips/pra_constants.hh"
-#include "arch/mips/registers.hh"
+#include "arch/mips/regs/misc.hh"
#include "base/bitfield.hh"
#include "base/logging.hh"
#include "base/trace.hh"
diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc
index e2f2bb9..ec1270a 100644
--- a/src/arch/mips/process.cc
+++ b/src/arch/mips/process.cc
@@ -29,6 +29,7 @@
#include "arch/mips/process.hh"
#include "arch/mips/isa_traits.hh"
+#include "arch/mips/regs/int.hh"
#include "base/loader/elf_object.hh"
#include "base/loader/object_file.hh"
#include "base/logging.hh"
diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index 67691c9..1f49262 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -32,234 +32,11 @@
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
-#include "base/logging.hh"
-#include "base/types.hh"
-
-class ThreadContext;
namespace MipsISA
{
-// Constants Related to the number of registers
-const int NumIntArchRegs = 32;
-const int NumIntSpecialRegs = 9;
-const int NumFloatArchRegs = 32;
-const int NumFloatSpecialRegs = 5;
-
-const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
-const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;//HI &
LO Regs
-const int NumFloatRegs = NumFloatAr
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Consolidate register related files into a directory.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41737 )
Change subject: arch-arm: Consolidate register related files into a
directory.
..
arch-arm: Consolidate register related files into a directory.
Create a directory called "regs" which holds files, primarily headers,
related to registers, with the exception of registers.hh. Hopefully
registers.hh will go away in the not too distant future, removing this
exception.
Change-Id: I631423c2b09bbcd14b20001380270718aeca619e
---
M src/arch/arm/SConscript
M src/arch/arm/aapcs32.hh
M src/arch/arm/aapcs64.hh
M src/arch/arm/decoder.hh
M src/arch/arm/fastmodel/iris/interrupts.cc
M src/arch/arm/fastmodel/iris/isa.cc
M src/arch/arm/faults.hh
M src/arch/arm/freebsd/se_workload.hh
M src/arch/arm/htm.cc
M src/arch/arm/htm.hh
M src/arch/arm/insts/fplib.hh
M src/arch/arm/insts/vfp.hh
M src/arch/arm/interrupts.hh
M src/arch/arm/isa.hh
M src/arch/arm/isa/includes.isa
M src/arch/arm/isa_device.cc
M src/arch/arm/isa_device.hh
M src/arch/arm/kvm/armv8_cpu.hh
M src/arch/arm/locked_mem.hh
M src/arch/arm/nativetrace.cc
M src/arch/arm/pmu.hh
M src/arch/arm/process.cc
M src/arch/arm/process.hh
M src/arch/arm/registers.hh
R src/arch/arm/regs/cc.hh
R src/arch/arm/regs/int.hh
R src/arch/arm/regs/misc.cc
R src/arch/arm/regs/misc.hh
R src/arch/arm/regs/misc_types.hh
M src/arch/arm/self_debug.cc
M src/arch/arm/self_debug.hh
M src/arch/arm/semihosting.hh
M src/arch/arm/table_walker.hh
M src/arch/arm/tracers/tarmac_base.cc
M src/arch/arm/tracers/tarmac_record.hh
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
37 files changed, 58 insertions(+), 56 deletions(-)
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 1d6799e..a51d794 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -81,7 +81,7 @@
Source('freebsd/fs_workload.cc')
Source('freebsd/se_workload.cc')
Source('fs_workload.cc')
-Source('miscregs.cc')
+Source('regs/misc.cc')
Source('mmu.cc')
Source('nativetrace.cc')
Source('pauth_helpers.cc')
diff --git a/src/arch/arm/aapcs32.hh b/src/arch/arm/aapcs32.hh
index a1345bd..151ff95 100644
--- a/src/arch/arm/aapcs32.hh
+++ b/src/arch/arm/aapcs32.hh
@@ -33,7 +33,7 @@
#include
#include
-#include "arch/arm/intregs.hh"
+#include "arch/arm/regs/int.hh"
#include "arch/arm/utility.hh"
#include "base/intmath.hh"
#include "cpu/thread_context.hh"
diff --git a/src/arch/arm/aapcs64.hh b/src/arch/arm/aapcs64.hh
index fb7b8f8..4d4ae92 100644
--- a/src/arch/arm/aapcs64.hh
+++ b/src/arch/arm/aapcs64.hh
@@ -33,7 +33,7 @@
#include
#include
-#include "arch/arm/intregs.hh"
+#include "arch/arm/regs/int.hh"
#include "arch/arm/utility.hh"
#include "base/intmath.hh"
#include "cpu/thread_context.hh"
diff --git a/src/arch/arm/decoder.hh b/src/arch/arm/decoder.hh
index 1f14328..1e7f80e 100644
--- a/src/arch/arm/decoder.hh
+++ b/src/arch/arm/decoder.hh
@@ -43,7 +43,7 @@
#include
-#include "arch/arm/miscregs.hh"
+#include "arch/arm/regs/misc.hh"
#include "arch/arm/types.hh"
#include "arch/generic/decode_cache.hh"
#include "arch/generic/decoder.hh"
diff --git a/src/arch/arm/fastmodel/iris/interrupts.cc
b/src/arch/arm/fastmodel/iris/interrupts.cc
index a3c777d..914f81e 100644
--- a/src/arch/arm/fastmodel/iris/interrupts.cc
+++ b/src/arch/arm/fastmodel/iris/interrupts.cc
@@ -29,8 +29,8 @@
#include "arch/arm/fastmodel/iris/thread_context.hh"
#include "arch/arm/interrupts.hh"
-#include "arch/arm/miscregs.hh"
-#include "arch/arm/miscregs_types.hh"
+#include "arch/arm/regs/misc.hh"
+#include "arch/arm/regs/misc_types.hh"
#include "arch/arm/types.hh"
#include "params/IrisInterrupts.hh"
diff --git a/src/arch/arm/fastmodel/iris/isa.cc
b/src/arch/arm/fastmodel/iris/isa.cc
index 1470434..4aac71f 100644
--- a/src/arch/arm/fastmodel/iris/isa.cc
+++ b/src/arch/arm/fastmodel/iris/isa.cc
@@ -27,7 +27,7 @@
#include "arch/arm/fastmodel/iris/isa.hh"
-#include "arch/arm/miscregs.hh"
+#include "arch/arm/regs/misc.hh"
#include "cpu/thread_context.hh"
#include "params/IrisISA.hh"
#include "sim/serialize.hh"
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index b911136..463af12 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -42,8 +42,8 @@
#ifndef __ARM_FAULTS_HH__
#define __ARM_FAULTS_HH__
-#include "arch/arm/miscregs.hh"
#include "arch/arm/pagetable.hh"
+#include "arch/arm/regs/misc.hh"
#include "arch/arm/types.hh"
#include "base/logging.hh"
#include "sim/faults.hh"
diff --git a/src/arch/arm/freebsd/se_workload.hh
b/src/arch/arm/freebsd/se_workload.hh
index 6f13201..2f5eb39 100644
--- a/src/arch/arm/freebsd/se_workload.hh
+++ b/src/arch/arm/freebsd/se_workload.hh
@@ -34,8 +34,8 @@
#ifndef __ARCH_ARM_FREEBSD_SE_WORKLOAD_HH__
#define __ARCH_ARM_FREEBSD_SE_WORKLOAD_HH__
-#include "arch/arm/ccregs.hh"
#include "arch/arm/freebsd/freebsd.hh"
+#include "
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Pull non-public information out of registers.hh.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/41740 )
Change subject: arch-power: Pull non-public information out of registers.hh.
..
arch-power: Pull non-public information out of registers.hh.
Also create a regs/ directory for register related headers.
Change-Id: Id376597b7b6254b26c05aa94e0141abacd807c79
---
M src/arch/power/isa.cc
M src/arch/power/isa.hh
M src/arch/power/isa/includes.isa
M src/arch/power/registers.hh
A src/arch/power/regs/float.hh
A src/arch/power/regs/int.hh
R src/arch/power/regs/misc.hh
M src/arch/power/remote_gdb.hh
M src/arch/power/se_workload.hh
M src/arch/power/utility.cc
10 files changed, 113 insertions(+), 34 deletions(-)
diff --git a/src/arch/power/isa.cc b/src/arch/power/isa.cc
index 0aa480c..8908645 100644
--- a/src/arch/power/isa.cc
+++ b/src/arch/power/isa.cc
@@ -37,8 +37,9 @@
#include "arch/power/isa.hh"
-#include "arch/power/miscregs.hh"
-#include "arch/power/registers.hh"
+#include "arch/power/regs/float.hh"
+#include "arch/power/regs/int.hh"
+#include "arch/power/regs/misc.hh"
#include "params/PowerISA.hh"
namespace PowerISA
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index 7ec9ac7..cc5aceb 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -31,8 +31,7 @@
#define __ARCH_POWER_ISA_HH__
#include "arch/generic/isa.hh"
-#include "arch/power/miscregs.hh"
-#include "arch/power/registers.hh"
+#include "arch/power/regs/misc.hh"
#include "arch/power/types.hh"
#include "base/logging.hh"
#include "cpu/reg_class.hh"
diff --git a/src/arch/power/isa/includes.isa
b/src/arch/power/isa/includes.isa
index c219d97..4aa9ff5 100644
--- a/src/arch/power/isa/includes.isa
+++ b/src/arch/power/isa/includes.isa
@@ -70,7 +70,7 @@
#include "arch/generic/memhelpers.hh"
#include "arch/power/faults.hh"
#include "arch/power/isa_traits.hh"
-#include "arch/power/miscregs.hh"
+#include "arch/power/regs/misc.hh"
#include "arch/power/utility.hh"
#include "base/condcodes.hh"
#include "cpu/base.hh"
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index b31f5f3..5bdc058 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -33,6 +33,7 @@
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
+#include "arch/power/regs/int.hh"
namespace PowerISA
{
@@ -52,35 +53,9 @@
constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
-// Constants Related to the number of registers
-const int NumIntArchRegs = 32;
-
-// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR
-// and zero register, which doesn't actually exist but needs a number
-const int NumIntSpecialRegs = 9;
-const int NumFloatArchRegs = 32;
-
-const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
-const int NumFloatRegs = NumFloatArchRegs;
-
-// Semantically meaningful register indices
-const int ReturnValueReg = 3;
-const int StackPointerReg = 1;
-
// There isn't one in Power, but we need to define one somewhere
const int ZeroReg = NumIntRegs - 1;
-enum MiscIntRegNums {
-INTREG_CR = NumIntArchRegs,
-INTREG_XER,
-INTREG_LR,
-INTREG_CTR,
-INTREG_FPSCR,
-INTREG_RSV,
-INTREG_RSV_LEN,
-INTREG_RSV_ADDR
-};
-
} // namespace PowerISA
#endif // __ARCH_POWER_REGISTERS_HH__
diff --git a/src/arch/power/regs/float.hh b/src/arch/power/regs/float.hh
new file mode 100644
index 000..c6e872d
--- /dev/null
+++ b/src/arch/power/regs/float.hh
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2009 The University of Edinburgh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
