[gem5-dev] Change in gem5/gem5[minor-release-staging-v21-0-1]: sim: Fix Temperature class
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/44745 ) Change subject: sim: Fix Temperature class .. sim: Fix Temperature class * Adding __str__ method: To fix its printing on config.ini (Replacing with the Temperature value) * Replacing "fromKelvin" with from_kelvin (that's how pybind exports it) * Fixing config_value to allow JSON serialization (JIRA: https://gem5.atlassian.net/browse/GEM5-951) Change-Id: I1aaea9c9df6466a5cbed0a29c5937243796948d2 Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44167 Reviewed-by: Andreas Sandberg Reviewed-by: Jason Lowe-Power Maintainer: Andreas Sandberg Tested-by: kokoro (cherry picked from commit 6cb9c3e87fa8034122310613079ae4f058f93233) --- M src/python/m5/params.py 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/python/m5/params.py b/src/python/m5/params.py index d2366f6..78be6f6 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -1705,12 +1705,15 @@ self.__init__(value) return value +def __str__(self): +return str(self.value) + def getValue(self): from _m5.core import Temperature -return Temperature.fromKelvin(self.value) +return Temperature.from_kelvin(self.value) def config_value(self): -return self +return self.value @classmethod def cxx_predecls(cls, code): -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/44745 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: minor-release-staging-v21-0-1 Gerrit-Change-Id: I1aaea9c9df6466a5cbed0a29c5937243796948d2 Gerrit-Change-Number: 44745 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-CC: Giacomo Travaglini Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[minor-release-staging-v21-0-1]: python,misc: Fix develop resources URL to v21-0
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/44725 ) Change subject: python,misc: Fix develop resources URL to v21-0 .. python,misc: Fix develop resources URL to v21-0 This was incorrectly kept as `http://dist.gem5.org/dist/develop` in the v21.0.0 release of gem5. The `dist/develop` directory is used by the develop branch, not by gem5 releases. This change updates the URL to point towards the currect v21-0 branch, which will remain stable and contain resoruces always compatible with the v21-0 release. Change-Id: I5d9a9497cebffa91f08be253f1637e11e0d5e62c --- M ext/testlib/configuration.py 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ext/testlib/configuration.py b/ext/testlib/configuration.py index 1fffab4..18bebdd 100644 --- a/ext/testlib/configuration.py +++ b/ext/testlib/configuration.py @@ -213,7 +213,7 @@ os.pardir, os.pardir)) defaults.result_path = os.path.join(os.getcwd(), 'testing-results') -defaults.resource_url = 'http://dist.gem5.org/dist/develop' +defaults.resource_url = 'http://dist.gem5.org/dist/v21-0' defaults.resource_path = os.path.abspath(os.path.join(defaults.base_dir, 'tests', 'gem5', -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/44725 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: minor-release-staging-v21-0-1 Gerrit-Change-Id: I5d9a9497cebffa91f08be253f1637e11e0d5e62c Gerrit-Change-Number: 44725 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Re: LTO causing headaches for users
I did create a patch for this: https://gem5-review.googlesource.com/c/public/gem5/+/44565. I _think_ this is the correct way to make LTO for .fast only. I won't submit until the community agrees this is the best course of action. Kind regards, Bobby -- Dr. Bobby R. Bruce Room 2235, Kemper Hall, UC Davis Davis, CA, 95616 web: https://www.bobbybruce.net On Tue, Apr 20, 2021 at 5:07 PM Gabe Black via gem5-dev wrote: > I think that's reasonable. I didn't think the performance difference would > be as much as it is, since my machine has more cores than that, 12 with 2 > threads per core. It actually speeds up the build for people who have > enough cores which offset the extra work the linker has to do, but I > suspect those people are not the common case. We should still make it > possible to use a flag to enable LTO explicitly for a given build, so > basically switch the polarity of the default and the override flag. > > Gabe > > On Tue, Apr 20, 2021 at 7:54 AM Jason Lowe-Power via gem5-dev < > gem5-dev@gem5.org> wrote: > >> Hi all, >> >> It seems the recent change to enable LTO by default is causing more harm >> than good. Especially for people debugging, it's a large overhead to wait >> 2-5 minutes for gem5 to link in opt mode. I even have encountered this with >> a 6 core 3.5+GHz Ryzen. It's quite annoying. We've gotten at least 3 >> different posts on gem5-users and gem5-dev complaining about this. I think >> this is a strong sign we need to change something. >> >> I suggest *only enabling* LTO for fast builds and not for any other. >> >> Thoughts? >> >> Jason >> ___ >> gem5-dev mailing list -- gem5-dev@gem5.org >> To unsubscribe send an email to gem5-dev-le...@gem5.org >> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > > ___ > gem5-dev mailing list -- gem5-dev@gem5.org > To unsubscribe send an email to gem5-dev-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Re: LTO causing headaches for users
I think that's reasonable. I didn't think the performance difference would be as much as it is, since my machine has more cores than that, 12 with 2 threads per core. It actually speeds up the build for people who have enough cores which offset the extra work the linker has to do, but I suspect those people are not the common case. We should still make it possible to use a flag to enable LTO explicitly for a given build, so basically switch the polarity of the default and the override flag. Gabe On Tue, Apr 20, 2021 at 7:54 AM Jason Lowe-Power via gem5-dev < gem5-dev@gem5.org> wrote: > Hi all, > > It seems the recent change to enable LTO by default is causing more harm > than good. Especially for people debugging, it's a large overhead to wait > 2-5 minutes for gem5 to link in opt mode. I even have encountered this with > a 6 core 3.5+GHz Ryzen. It's quite annoying. We've gotten at least 3 > different posts on gem5-users and gem5-dev complaining about this. I think > this is a strong sign we need to change something. > > I suggest *only enabling* LTO for fast builds and not for any other. > > Thoughts? > > Jason > ___ > gem5-dev mailing list -- gem5-dev@gem5.org > To unsubscribe send an email to gem5-dev-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] gem5 roadmap!
Hi all, It's that time again to create a roadmap for the next gem5 release! I've put together a draft with the things that we are planning to work on here at UCD and a couple of other things that are on Jira. Please let the community know what you're planning on working on over the next couple of months. By letting the community know what you're planning on working on it can help us all be more productive and allow gem5 to be an even better tool! Feel free to reply here with a couple of sentences of what you're planning on doing and I'll put it in the document. Or, you can add a comment on the gerrit page and I'll update. You can see the draft below for some examples of what we're planning. Draft: https://gem5-review.googlesource.com/c/public/gem5-website/+/44705 It would also be great to create Jira epics or issues for different parts of the project so that we can all follow what everyone is working on! Happy developing! Cheers, Jason ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: sim: Trap into GDB instead of panicking on SEGV
Boris Shingarov has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/44685 )
Change subject: sim: Trap into GDB instead of panicking on SEGV
..
sim: Trap into GDB instead of panicking on SEGV
When a segfault happens in the guest, report a SEGV trap to GDB (if
there is one attached) instead of bailing out immediately.
The obvious use-case for this, is the ability to debug guest crashes
in GDB in the standard manner.
The less-trivial use-case is for development of software in an
incomplete software stack (cf. Aarno-Engblom's "Virtual Platforms"
pp.105 et seq.) One particular example is Ingalls-Miranda simulation of
JIT compilers, where the VM's address space may be split between the
simulated and the real machine: in this case, GDB traps facilitate the
transparent illusion of an unbroken address space.
Change-Id: I9072ed5f6474e05e9a99dc42ae5754be28121355
---
M src/sim/faults.cc
M src/sim/system.cc
M src/sim/system.hh
3 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/src/sim/faults.cc b/src/sim/faults.cc
index 501b5d1..13de0fc 100644
--- a/src/sim/faults.cc
+++ b/src/sim/faults.cc
@@ -40,6 +40,8 @@
#include "sim/faults.hh"
+#include
+
#include "arch/decoder.hh"
#include "arch/locked_mem.hh"
#include "base/logging.hh"
@@ -94,15 +96,16 @@
Process *p = tc->getProcessPtr();
handled = p->fixupFault(vaddr);
}
-panic_if(!handled, "Page table fault when accessing virtual
address %#x",
- vaddr);
-
+if (handled) return;
+panic_if(tc->getSystemPtr()->trap_to_gdb(SIGSEGV),
+ "Page table fault when accessing virtual address %#x\n",
vaddr);
}
void
GenericAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr )
{
-panic("Alignment fault when accessing virtual address %#x\n", vaddr);
+panic_if(tc->getSystemPtr()->trap_to_gdb(SIGSEGV),
+ "Alignment fault when accessing virtual address %#x\n",
vaddr);
}
void GenericHtmFailureFault::invoke(ThreadContext *tc,
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 9fd312c..e8f881a 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -495,6 +495,18 @@
lastWorkItemStarted.erase(p);
}
+bool
+System::trap_to_gdb(int signal) const
+{
+if (!threads.size())
+return true; /* true if we failed, so caller needs to panic */
+auto *gdb = threads.thread(0).gdb;
+if (!gdb)
+return true;
+gdb->trap(signal);
+return false;
+}
+
void
System::printSystems()
{
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 6613217..fe02349 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -561,6 +561,8 @@
void workItemEnd(uint32_t tid, uint32_t workid);
+bool trap_to_gdb(int signal) const;
+
protected:
/**
* Range for memory-mapped m5 pseudo ops. The range will be
--
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Gerrit-Change-Id: I9072ed5f6474e05e9a99dc42ae5754be28121355
Gerrit-Change-Number: 44685
Gerrit-PatchSet: 1
Gerrit-Owner: Boris Shingarov
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[gem5-dev] LTO causing headaches for users
Hi all, It seems the recent change to enable LTO by default is causing more harm than good. Especially for people debugging, it's a large overhead to wait 2-5 minutes for gem5 to link in opt mode. I even have encountered this with a 6 core 3.5+GHz Ryzen. It's quite annoying. We've gotten at least 3 different posts on gem5-users and gem5-dev complaining about this. I think this is a strong sign we need to change something. I suggest *only enabling* LTO for fast builds and not for any other. Thoughts? Jason ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: configs: Fix stats name in arm/fs_power.py
Hoa Nguyen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/44626 )
Change subject: configs: Fix stats name in arm/fs_power.py
..
configs: Fix stats name in arm/fs_power.py
In the config, there are stats having name changed:
- overall_misses -> overallMisses
- sim_seconds -> simSeconds
- overall_accesses -> overallAccesses
JIRA: https://gem5.atlassian.net/browse/GEM5-957
Signed-off-by: Hoa Nguyen
Change-Id: I35faa72b12320e6b41833f601eb23604358b3d42
---
M configs/example/arm/fs_power.py
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/configs/example/arm/fs_power.py
b/configs/example/arm/fs_power.py
index 1c7b6b7..7ae9cf8 100644
--- a/configs/example/arm/fs_power.py
+++ b/configs/example/arm/fs_power.py
@@ -51,8 +51,8 @@
# 2A per IPC, 3pA per cache miss
# and then convert to Watt
self.dyn = "voltage * (2 * {}.ipc + 3 * 0.1 * " \
-"{}.dcache.overall_misses /
sim_seconds)".format(cpu_path,
-
cpu_path)
+"{}.dcache.overallMisses /
simSeconds)".format(cpu_path,
+
cpu_path)
self.st = "4 * temp"
class CpuPowerOff(MathExprPowerModel):
@@ -72,10 +72,10 @@
class L2PowerOn(MathExprPowerModel):
def __init__(self, l2_path, **kwargs):
super(L2PowerOn, self).__init__(**kwargs)
-# Example to report l2 Cache overall_accesses
+# Example to report l2 Cache overallAccesses
# The estimated power is converted to Watt and will vary based
# on the size of the cache
-self.dyn = "{}.overall_accesses * 0.18000".format(l2_path)
+self.dyn = "{}.overallAccesses * 0.18000".format(l2_path)
self.st = "(voltage * 3)/10"
class L2PowerOff(MathExprPowerModel):
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I35faa72b12320e6b41833f601eb23604358b3d42
Gerrit-Change-Number: 44626
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: add amba_to_tlm_bridge hooks before going to gem5
Yu-hsin Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/44645 )
Change subject: fastmodel: add amba_to_tlm_bridge hooks before going to gem5
..
fastmodel: add amba_to_tlm_bridge hooks before going to gem5
To handle atomic transaction, we need to convert amba far atomic
extension into gem5 atomic extension before going to gem5 world. This cl
prepares hooks that enables us to do the conversion.
Change-Id: I1b5a99c38f619689bd318253356928091a4fdb02
---
M src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
M src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
2 files changed, 55 insertions(+), 4 deletions(-)
diff --git a/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
b/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
index a011e35..c306c12 100644
--- a/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
+++ b/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
@@ -32,11 +32,23 @@
namespace FastModel
{
-AmbaToTlmBridge64::AmbaToTlmBridge64(const char *name) :
+AmbaToTlmBridge64::AmbaToTlmBridge64(const sc_core::sc_module_name& name) :
amba_pv::amba_pv_to_tlm_bridge<64>(name),
-tlmWrapper(tlm_m, std::string(name) + ".tlm", -1),
+proxy_tlm_s("proxy_tlm_s"),
+proxy_tlm_m("proxy_tlm_m"),
+tlmWrapper(proxy_tlm_m, std::string(name) + ".tlm", -1),
ambaWrapper(amba_pv_s, std::string(name) + ".amba", -1)
-{}
+{
+proxy_tlm_s.register_b_transport(
+this, ::proxy_b_transport);
+proxy_tlm_s.register_get_direct_mem_ptr(
+this, ::proxy_get_direct_mem_ptr);
+proxy_tlm_s.register_transport_dbg(
+this, ::proxy_transport_dbg);
+proxy_tlm_m.register_invalidate_direct_mem_ptr(
+this, ::proxy_invalidate_direct_mem_ptr);
+tlm_m(proxy_tlm_s);
+}
Port &
AmbaToTlmBridge64::gem5_getPort(const std::string _name, int idx)
@@ -49,6 +61,33 @@
return amba_pv::amba_pv_to_tlm_bridge<64>::gem5_getPort(if_name,
idx);
}
+void
+AmbaToTlmBridge64::proxy_b_transport(amba_pv::amba_pv_transaction ,
+ sc_core::sc_time )
+{
+return proxy_tlm_m->b_transport(trans, t);
+}
+
+bool
+AmbaToTlmBridge64::proxy_get_direct_mem_ptr(amba_pv::amba_pv_transaction
,
+tlm::tlm_dmi _data)
+{
+return proxy_tlm_m->get_direct_mem_ptr(trans, dmi_data);
+}
+
+unsigned int
+AmbaToTlmBridge64::proxy_transport_dbg(amba_pv::amba_pv_transaction )
+{
+return proxy_tlm_m->transport_dbg(trans);
+}
+
+void
+AmbaToTlmBridge64::proxy_invalidate_direct_mem_ptr(sc_dt::uint64
start_range,
+ sc_dt::uint64 end_range)
+{
+proxy_tlm_s->invalidate_direct_mem_ptr(start_range, end_range);
+}
+
} // namespace FastModel
FastModel::AmbaToTlmBridge64 *
diff --git a/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
b/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
index 8baee6a..ec8bed4 100644
--- a/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
+++ b/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
@@ -43,11 +43,23 @@
class AmbaToTlmBridge64 : public amba_pv::amba_pv_to_tlm_bridge<64>
{
public:
-AmbaToTlmBridge64(const char *name);
+AmbaToTlmBridge64(const sc_core::sc_module_name );
::Port _getPort(const std::string _name, int idx=-1) override;
private:
+void proxy_b_transport(amba_pv::amba_pv_transaction ,
+ sc_core::sc_time );
+bool proxy_get_direct_mem_ptr(amba_pv::amba_pv_transaction ,
+ tlm::tlm_dmi _data);
+unsigned int proxy_transport_dbg(amba_pv::amba_pv_transaction );
+void proxy_invalidate_direct_mem_ptr(sc_dt::uint64 start_range,
+ sc_dt::uint64 end_range);
+
+tlm_utils::simple_target_socket<
+AmbaToTlmBridge64, 64, tlm::tlm_base_protocol_types> proxy_tlm_s;
+tlm_utils::simple_initiator_socket<
+AmbaToTlmBridge64, 64, tlm::tlm_base_protocol_types> proxy_tlm_m;
sc_gem5::TlmInitiatorWrapper<64> tlmWrapper;
AmbaTarget ambaWrapper;
};
--
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Gerrit-Change-Id: I1b5a99c38f619689bd318253356928091a4fdb02
Gerrit-Change-Number: 44645
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang
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[gem5-dev] Change in gem5/gem5[develop]: fastmodel: handling amba far atomic transaction
Yu-hsin Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/44646 )
Change subject: fastmodel: handling amba far atomic transaction
..
fastmodel: handling amba far atomic transaction
Change-Id: I360c2a2bd415524b2a76434a13920f94360afa0f
---
M src/arch/arm/fastmodel/SConscript
M src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
M src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
3 files changed, 63 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/fastmodel/SConscript
b/src/arch/arm/fastmodel/SConscript
index c659434..f4c1bbf 100644
--- a/src/arch/arm/fastmodel/SConscript
+++ b/src/arch/arm/fastmodel/SConscript
@@ -107,6 +107,8 @@
pvlib_home.Dir('include/fmruntime'),
pvlib_home.Dir('include/fmruntime/eslapi'),
pvlib_home.Dir('Iris/include'),
+pvlib_home.Dir('include'),
+pvlib_home.Dir('examples/SystemCExport/Common/include'),
systemc_home.Dir('include'),
diff --git a/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
b/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
index c306c12..6a40d5a 100644
--- a/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
+++ b/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
@@ -27,7 +27,31 @@
#include "arch/arm/fastmodel/amba_to_tlm_bridge.hh"
+#include "base/amo.hh"
#include "params/AmbaToTlmBridge64.hh"
+#include "pv/FarAtomicService.h"
+#include "pv_userpayload_extension.h"
+#include "systemc/tlm_bridge/sc_ext.hh"
+
+namespace {
+
+uint8_t dummy_buffer[64] = {};
+
+struct FarAtomicOpFunctor : public AtomicOpFunctor {
+FarAtomicOpFunctor(far_atomic::FarAtomic *_fa) : fa(_fa) {}
+void operator()(uint8_t *p) override {
+fa->serviceWasFound();
+fa->doAtomicOperation(p);
+}
+
+AtomicOpFunctor* clone() override {
+return new FarAtomicOpFunctor(*this);
+};
+
+far_atomic::FarAtomic *fa;
+};
+
+}
namespace FastModel
{
@@ -65,6 +89,7 @@
AmbaToTlmBridge64::proxy_b_transport(amba_pv::amba_pv_transaction ,
sc_core::sc_time )
{
+maybeSetupAtomicExtension(trans);
return proxy_tlm_m->b_transport(trans, t);
}
@@ -88,6 +113,41 @@
proxy_tlm_s->invalidate_direct_mem_ptr(start_range, end_range);
}
+void
+AmbaToTlmBridge64::maybeSetupAtomicExtension(
+amba_pv::amba_pv_transaction )
+{
+Gem5SystemC::AtomicExtension *atomic_ex = nullptr;
+trans.get_extension(atomic_ex);
+if (atomic_ex) return;
+
+pv_userpayload_extension *user_ex = nullptr;
+trans.get_extension(user_ex);
+if (!user_ex) return;
+
+pv::UserPayloadBase *upb = user_ex->get_user_payload();
+uint32_t appid = upb->get_appID();
+if (appid != pv::UserPayloadBase::SERVICE_REQUEST) return;
+
+std::pair u_data = user_ex->get_user_data();
+far_atomic::FarAtomic *fa = static_cast(
+u_data.first);
+
+// Correct the request size manually and give it a dummy buffer
preventing
+// from segmentation fault.
+trans.set_data_length(fa->getDataValueSizeInBytes());
+trans.set_data_ptr(dummy_buffer);
+
+// The return value would store in the extension. We don't need to
specify
+// need_return here.
+atomic_ex = new Gem5SystemC::AtomicExtension(
+std::make_shared(fa), false);
+if (trans.has_mm())
+trans.set_auto_extension(atomic_ex);
+else
+trans.set_extension(atomic_ex);
+}
+
} // namespace FastModel
FastModel::AmbaToTlmBridge64 *
diff --git a/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
b/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
index ec8bed4..d13525a 100644
--- a/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
+++ b/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
@@ -55,6 +55,7 @@
unsigned int proxy_transport_dbg(amba_pv::amba_pv_transaction );
void proxy_invalidate_direct_mem_ptr(sc_dt::uint64 start_range,
sc_dt::uint64 end_range);
+void maybeSetupAtomicExtension(amba_pv::amba_pv_transaction );
tlm_utils::simple_target_socket<
AmbaToTlmBridge64, 64, tlm::tlm_base_protocol_types> proxy_tlm_s;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I360c2a2bd415524b2a76434a13920f94360afa0f
Gerrit-Change-Number: 44646
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim: Track ThreadContext-s in the Workload object.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/44616 )
Change subject: sim: Track ThreadContext-s in the Workload object.
..
sim: Track ThreadContext-s in the Workload object.
Change-Id: I00bf9fa36d3993f55d41e50196ad8a89a3d506c4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44616
Maintainer: Gabe Black
Tested-by: kokoro
Reviewed-by: Boris Shingarov
---
M src/sim/SConscript
M src/sim/system.cc
A src/sim/workload.cc
M src/sim/workload.hh
4 files changed, 75 insertions(+), 0 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/SConscript b/src/sim/SConscript
index fe18d24..fb87bfe 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -83,6 +83,7 @@
Source('power_state.cc')
Source('power_domain.cc')
Source('stats.cc')
+Source('workload.cc')
GTest('byteswap.test', 'byteswap.test.cc', '../base/types.cc')
GTest('guest_abi.test', 'guest_abi.test.cc')
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 7a3e248..9fd312c 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -301,6 +301,9 @@
{
threads.insert(tc, assigned);
+if (workload)
+workload->registerThreadContext(tc);
+
for (auto *e: liveEvents)
tc->schedule(e);
}
@@ -331,6 +334,9 @@
auto *otc = threads[context_id];
threads.replace(tc, context_id);
+if (workload)
+workload->replaceThreadContext(tc);
+
for (auto *e: liveEvents) {
otc->remove(e);
tc->schedule(e);
diff --git a/src/sim/workload.cc b/src/sim/workload.cc
new file mode 100644
index 000..c7dfcd4
--- /dev/null
+++ b/src/sim/workload.cc
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2021 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "sim/workload.hh"
+
+#include "cpu/thread_context.hh"
+
+void
+Workload::registerThreadContext(ThreadContext *tc)
+{
+std::set::iterator it;
+bool success;
+std::tie(it, success) = threads.insert(tc);
+panic_if(!success, "Failed to add thread context %d.",
+tc->contextId());
+}
+
+void
+Workload::replaceThreadContext(ThreadContext *tc)
+{
+ContextID id = tc->contextId();
+
+for (auto *old: threads) {
+if (old->contextId() != id)
+continue;
+threads.erase(old);
+
+std::set::iterator it;
+bool success;
+std::tie(it, success) = threads.insert(tc);
+panic_if(!success,
+"Failed to insert replacement thread context %d.", id);
+return;
+}
+panic("Replacement thread context %d doesn't match any known id.", id);
+}
diff --git a/src/sim/workload.hh b/src/sim/workload.hh
index 3458af7..f3b55ad 100644
--- a/src/sim/workload.hh
+++ b/src/sim/workload.hh
@@ -28,6 +28,9 @@
#ifndef __SIM_WORKLOAD_HH__
#define __SIM_WORKLOAD_HH__
+#include
+#include
+
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
#include "params/Workload.hh"
@@ -63,6 +66,8 @@
{}
} stats;
+std::set threads;
+
public:
Workload(const WorkloadParams ) : SimObject(params), stats(this)
{}
@@ -72,6 +77,9 @@
System *system = nullptr;
+virtual void registerThreadContext(ThreadContext *tc);
+virtual void replaceThreadContext(ThreadContext *tc);
+
virtual Addr getEntry() const = 0;
virtual Loader::Arch getArch() const =
[gem5-dev] Change in gem5/gem5[develop]: cpu,sim: Set ThreadContext's ContextID right away.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/44615 )
Change subject: cpu,sim: Set ThreadContext's ContextID right away.
..
cpu,sim: Set ThreadContext's ContextID right away.
The code which registers thread contexts originally returned the ID that
it had chosen, and let the CPU actually set the ID in the object itself.
That opened a window where calling contextId() on the ThreadContext
would return the wrong answer.
Instead, we can just set the ID immediately after it's decided. This
also localizes that logic and removes plumbing for the ID between that
decision and where it's actually applied.
Change-Id: I31ad84c3f9bf6f5b6f72457ca640ea929b24f6a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/44615
Tested-by: kokoro
Reviewed-by: Daniel Carvalho
Reviewed-by: Boris Shingarov
Maintainer: Gabe Black
---
M src/cpu/base.cc
M src/sim/system.cc
M src/sim/system.hh
3 files changed, 9 insertions(+), 11 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Daniel Carvalho: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index f98837c..c40c001 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -431,9 +431,9 @@
ThreadContext *tc = threadContexts[tid];
if (system->multiThread) {
-tc->setContextId(system->registerThreadContext(tc));
+system->registerThreadContext(tc);
} else {
-tc->setContextId(system->registerThreadContext(tc, _cpuId));
+system->registerThreadContext(tc, _cpuId);
}
if (!FullSystem)
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 0c42256..7a3e248 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -98,7 +98,7 @@
workload->recordQuiesce();
}
-ContextID
+void
System::Threads::insert(ThreadContext *tc, ContextID id)
{
if (id == InvalidContextID) {
@@ -108,6 +108,8 @@
}
}
+tc->setContextId(id);
+
if (id >= size())
threads.resize(id + 1);
@@ -129,8 +131,6 @@
t.gdb->listen();
}
# endif
-
-return id;
}
void
@@ -296,15 +296,13 @@
memoryMode = mode;
}
-ContextID
+void
System::registerThreadContext(ThreadContext *tc, ContextID assigned)
{
-ContextID id = threads.insert(tc, assigned);
+threads.insert(tc, assigned);
for (auto *e: liveEvents)
tc->schedule(e);
-
-return id;
}
bool
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 480b523..6613217 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -142,7 +142,7 @@
return threads[id];
}
-ContextID insert(ThreadContext *tc, ContextID id=InvalidContextID);
+void insert(ThreadContext *tc, ContextID id=InvalidContextID);
void replace(ThreadContext *tc, ContextID id);
friend class System;
@@ -586,7 +586,7 @@
/// @return Starting address of first page
Addr allocPhysPages(int npages);
-ContextID registerThreadContext(
+void registerThreadContext(
ThreadContext *tc, ContextID assigned=InvalidContextID);
void replaceThreadContext(ThreadContext *tc, ContextID context_id);
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I31ad84c3f9bf6f5b6f72457ca640ea929b24f6a0
Gerrit-Change-Number: 44615
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Daniel Carvalho
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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