[gem5-dev] Change in gem5/gem5[develop]: scons: Explicitly add librt to scons
Hoa Nguyen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47659 )
Change subject: scons: Explicitly add librt to scons
..
scons: Explicitly add librt to scons
Building gem5 requires linking to librt. Prior to this change, the
SConscript files do not include the librt explicitly, and building
gem5 on the preformatted disk of Ubuntu 21.04 for RISC-V results
in the missing reference to `shm_open`, which is part of librt.
This change tells scons to add librt to all combinations of building
gem5.
JIRA: https://gem5.atlassian.net/browse/GEM5-1015
Change-Id: I461400e3cb7474a80a995b264af2e03b19fea29c
Signed-off-by: Hoa Nguyen
---
M SConstruct
1 file changed, 3 insertions(+), 0 deletions(-)
diff --git a/SConstruct b/SConstruct
index f3af8ff..5593c17 100755
--- a/SConstruct
+++ b/SConstruct
@@ -698,6 +698,9 @@
env.Append(CCFLAGS='$CCFLAGS_EXTRA')
env.Append(LINKFLAGS='$LDFLAGS_EXTRA')
+# Add librt, which is required by gem5
+env.Append(LIBS=['rt'])
+
exports=['env']
if main['USE_PYTHON']:
exports.append('marshal_env')
--
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Gerrit-Change-Id: I461400e3cb7474a80a995b264af2e03b19fea29c
Gerrit-Change-Number: 47659
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: learning-gem5: Updated deprecated terms in simple.py
Laura Hinman has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/47639 ) Change subject: learning-gem5: Updated deprecated terms in simple.py .. learning-gem5: Updated deprecated terms in simple.py Updated terms include: -`slave` is now `cpu_side_ports` -`master` is now `mem_side_ports` -`int_master` is now `int_requestor` -`int_slave` is now `int_responder` Change-Id: Ic5a0d722f3c3c529ecbdc33413b17b4f72180ef3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47639 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M configs/learning_gem5/part1/simple.py 1 file changed, 7 insertions(+), 7 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/configs/learning_gem5/part1/simple.py b/configs/learning_gem5/part1/simple.py index 69521fe..235165b 100644 --- a/configs/learning_gem5/part1/simple.py +++ b/configs/learning_gem5/part1/simple.py @@ -59,8 +59,8 @@ system.membus = SystemXBar() # Hook the CPU ports up to the membus -system.cpu.icache_port = system.membus.slave -system.cpu.dcache_port = system.membus.slave +system.cpu.icache_port = system.membus.cpu_side_ports +system.cpu.dcache_port = system.membus.cpu_side_ports # create the interrupt controller for the CPU and connect to the membus system.cpu.createInterruptController() @@ -68,18 +68,18 @@ # For x86 only, make sure the interrupts are connected to the memory # Note: these are directly connected to the memory bus and are not cached if m5.defines.buildEnv['TARGET_ISA'] == "x86": -system.cpu.interrupts[0].pio = system.membus.master -system.cpu.interrupts[0].int_master = system.membus.slave -system.cpu.interrupts[0].int_slave = system.membus.master +system.cpu.interrupts[0].pio = system.membus.mem_side_ports +system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports +system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports # Create a DDR3 memory controller and connect it to the membus system.mem_ctrl = MemCtrl() system.mem_ctrl.dram = DDR3_1600_8x8() system.mem_ctrl.dram.range = system.mem_ranges[0] -system.mem_ctrl.port = system.membus.master +system.mem_ctrl.port = system.membus.mem_side_ports # Connect the system up to the membus -system.system_port = system.membus.slave +system.system_port = system.membus.cpu_side_ports # get ISA for the binary to run. isa = str(m5.defines.buildEnv['TARGET_ISA']).lower() -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/47639 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ic5a0d722f3c3c529ecbdc33413b17b4f72180ef3 Gerrit-Change-Number: 47639 Gerrit-PatchSet: 2 Gerrit-Owner: Laura Hinman Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Laura Hinman Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add clone support
Sandipan Das has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/47579 )
Change subject: arch-power: Add clone support
..
arch-power: Add clone support
This adds support for the clone() system call using
which multiple cpus can be utilized in SE mode. For
this change, it should be noted that Linux on Power
uses the CLONE_BACKWARDS argument order.
Change-Id: Iac91a7d110d9f7a133b8e102ac113f48a431a0d6
Signed-off-by: Kevin Joe <0keik...@gmail.com>
Signed-off-by: Chetan Agarwal
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47579
Reviewed-by: Boris Shingarov
Maintainer: Boris Shingarov
Tested-by: kokoro
---
M src/arch/power/linux/linux.hh
M src/arch/power/linux/se_workload.cc
M src/arch/power/regs/int.hh
3 files changed, 20 insertions(+), 1 deletion(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/linux/linux.hh b/src/arch/power/linux/linux.hh
index cdb1cda..646d642 100644
--- a/src/arch/power/linux/linux.hh
+++ b/src/arch/power/linux/linux.hh
@@ -32,6 +32,9 @@
#include
+#include "arch/power/isa.hh"
+#include "arch/power/regs/int.hh"
+#include "cpu/thread_context.hh"
#include "kern/linux/linux.hh"
namespace gem5
@@ -214,6 +217,21 @@
return false;
}
}
+
+static void
+archClone(uint64_t flags,
+ Process *pp, Process *cp,
+ ThreadContext *ptc, ThreadContext *ctc,
+ uint64_t stack, uint64_t tls)
+{
+ctc->getIsaPtr()->copyRegsFrom(ptc);
+
+if (flags & TGT_CLONE_SETTLS)
+ctc->setIntReg(PowerISA::ThreadPointerReg, tls);
+
+if (stack)
+ctc->setIntReg(PowerISA::StackPointerReg, stack);
+}
};
} // namespace gem5
diff --git a/src/arch/power/linux/se_workload.cc
b/src/arch/power/linux/se_workload.cc
index 9d5f9de..b49cb0b 100644
--- a/src/arch/power/linux/se_workload.cc
+++ b/src/arch/power/linux/se_workload.cc
@@ -227,7 +227,7 @@
{ 117, "ipc" },
{ 118, "fsync" },
{ 119, "sigreturn" },
-{ 120, "clone" },
+{ 120, "clone", cloneBackwardsFunc },
{ 121, "setdomainname" },
{ 122, "uname", unameFunc },
{ 123, "modify_ldt" },
diff --git a/src/arch/power/regs/int.hh b/src/arch/power/regs/int.hh
index 891eaa1..95fbb8a 100644
--- a/src/arch/power/regs/int.hh
+++ b/src/arch/power/regs/int.hh
@@ -55,6 +55,7 @@
const int ArgumentReg5 = 8;
const int StackPointerReg = 1;
const int TOCPointerReg = 2;
+const int ThreadPointerReg = 13;
enum MiscIntRegNums
{
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iac91a7d110d9f7a133b8e102ac113f48a431a0d6
Gerrit-Change-Number: 47579
Gerrit-PatchSet: 2
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Sandipan Das
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: learning-gem5: Updated deprecated terms in simple.py
Laura Hinman has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/47639 ) Change subject: learning-gem5: Updated deprecated terms in simple.py .. learning-gem5: Updated deprecated terms in simple.py Updated terms include: -`slave` is now `cpu_side_ports` -`master` is now `mem_side_ports` -`int_master` is now `int_requestor` -`int_slave` is now `int_responder` Change-Id: Ic5a0d722f3c3c529ecbdc33413b17b4f72180ef3 --- M configs/learning_gem5/part1/simple.py 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/configs/learning_gem5/part1/simple.py b/configs/learning_gem5/part1/simple.py index 69521fe..235165b 100644 --- a/configs/learning_gem5/part1/simple.py +++ b/configs/learning_gem5/part1/simple.py @@ -59,8 +59,8 @@ system.membus = SystemXBar() # Hook the CPU ports up to the membus -system.cpu.icache_port = system.membus.slave -system.cpu.dcache_port = system.membus.slave +system.cpu.icache_port = system.membus.cpu_side_ports +system.cpu.dcache_port = system.membus.cpu_side_ports # create the interrupt controller for the CPU and connect to the membus system.cpu.createInterruptController() @@ -68,18 +68,18 @@ # For x86 only, make sure the interrupts are connected to the memory # Note: these are directly connected to the memory bus and are not cached if m5.defines.buildEnv['TARGET_ISA'] == "x86": -system.cpu.interrupts[0].pio = system.membus.master -system.cpu.interrupts[0].int_master = system.membus.slave -system.cpu.interrupts[0].int_slave = system.membus.master +system.cpu.interrupts[0].pio = system.membus.mem_side_ports +system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports +system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports # Create a DDR3 memory controller and connect it to the membus system.mem_ctrl = MemCtrl() system.mem_ctrl.dram = DDR3_1600_8x8() system.mem_ctrl.dram.range = system.mem_ranges[0] -system.mem_ctrl.port = system.membus.master +system.mem_ctrl.port = system.membus.mem_side_ports # Connect the system up to the membus -system.system_port = system.membus.slave +system.system_port = system.membus.cpu_side_ports # get ISA for the binary to run. isa = str(m5.defines.buildEnv['TARGET_ISA']).lower() -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/47639 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ic5a0d722f3c3c529ecbdc33413b17b4f72180ef3 Gerrit-Change-Number: 47639 Gerrit-PatchSet: 1 Gerrit-Owner: Laura Hinman Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Forward declare kvm_reg_list
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47619 )
Change subject: arch-arm: Forward declare kvm_reg_list
..
arch-arm: Forward declare kvm_reg_list
The adoption of the gem5 namespace [1] broke aarch64 builds with
the following error:
build/ARM/arch/arm/kvm/base_cpu.cc:198:22: error: aggregate
'gem5::kvm_reg_list regs_probe' has incomplete type and cannot be
defined
In file included from build/ARM/arch/arm/kvm/base_cpu.cc:38:0:
build/ARM/arch/arm/kvm/base_cpu.hh:115:28: note: forward declaration of
'struct gem5::kvm_reg_list'
std::unique_ptr tryGetRegList(uint64_t nelem)
const;
Forward declaring the struct defined in linux/kvm.hh (included in source
file fixes the problem
[1]: https://gem5-review.googlesource.com/c/public/gem5/+/46323
Signed-off-by: Giacomo Travaglini
Change-Id: I96c7d31aa4810edcf98e23cefeaf4895620b6444
---
M src/arch/arm/kvm/base_cpu.hh
1 file changed, 2 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/kvm/base_cpu.hh b/src/arch/arm/kvm/base_cpu.hh
index 81e8596..37af099 100644
--- a/src/arch/arm/kvm/base_cpu.hh
+++ b/src/arch/arm/kvm/base_cpu.hh
@@ -43,6 +43,8 @@
#include "cpu/kvm/base.hh"
#include "dev/arm/base_gic.hh"
+struct kvm_reg_list;
+
namespace gem5
{
--
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Gerrit-Change-Id: I96c7d31aa4810edcf98e23cefeaf4895620b6444
Gerrit-Change-Number: 47619
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Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] Re: Kokoro bit
Yes, the POWER 64-bit SE is upstreamed now. I agree with your characterization of it as "fantastic news".I am now in the middle of a large-scale test before I can declare that we ("we" = the JIT-compiler group at LabWare) are happy with the state of POWER on gem5 for the coming release. This actually means more things than "just" this series of patches. The thing that LabWare cares about, is that the compiler community can start reproducing our experiments without the need to mess with 3rd-party patches to gem5. And POWER-64 is one part of it, the other part is the improved guest-debugging. So, I am re-testing now that these play together. After that, we are open to intriguing new worlds, from synthesizing a superoptimizer from the mdwn pseudocode, to multi-way co-verification (mdwn/gem5/valgrind), to translating mdwn to Coq definitions.-"lkcl" wrote: -To: "Boris Shingarov" From: "lkcl" Date: 07/04/2021 03:25PMCc: "Gabe Black" , "Jason Lowe-Power via gem5-dev" , "Sandipan Das" Subject: Re: Kokoro bithttps://urldefense.proofpoint.com/v2/url?u=https-3A__gem5-2Dreview.googlesource.com_c_public_gem5_-2B_40906_7=DwIBaQ=sPZ6DeHLiehUHQWKIrsNwWp3t7snrE-az24ztT0w7Jc=ecC5uu6ubGhPt6qQ8xWcSQh1QUJ8B1-CG4B9kRM0nd4=t7AgTiyWbVbY_S7RymZ-4qak05WVjImfP54H5HPEq1A=5mnKd36afIaUm7_mxCFLpYkgMgyyfgpFyuJ1KDAToyw= are all these done? i just checked and the entire list now says "merged"if so that's fantastic news. are there any more i need to keep an eye on?l.___
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: accuracy and coverage stat for prefetchers
Nathanael Premillieu has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47603 )
Change subject: mem-cache: accuracy and coverage stat for prefetchers
..
mem-cache: accuracy and coverage stat for prefetchers
Add an accuracy and coverage stat for the prefetchers.
Accuracy is defined as the ratio of the number of prefetch
request that have been counted as useful over the number
of prefetch request issued.
Accuracy tells whether the prefetcher is producing useful
requests or not.
Coverage is defined as the ratio of of the number of prefetch
request that have been counted as useful over the number of
demand misses if there was no prefetch, which is counted as
the number of useful prefetch request plus the remaining
demand misses. Due to the way stats are defined in the cache,
I have to add a stat to count the number of remaining demand
misses directly in the prefetcher stat. Demand is defined
as being one of this request type: ReadReq, WriteReq,
WriteLineReq, ReadExReq, ReadCleanReq, ReadSharedReq.
Coverage tells what part of misses are covered by the prefetcher.
Change-Id: I3bb8838f87b42665fdd782889f6ba56ca2a802fc
---
M src/mem/cache/base.cc
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
M src/mem/packet.hh
4 files changed, 36 insertions(+), 3 deletions(-)
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 17895ce..3b7468f 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -308,6 +308,8 @@
// no MSHR
assert(pkt->req->requestorId() < system->maxRequestors());
stats.cmdStats(pkt).mshrMisses[pkt->req->requestorId()]++;
+if (prefetcher && pkt->isDemand())
+prefetcher->incrDemandMhsrMisses();
if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean) {
// We use forward_time here because there is an
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index 724cebf..d7ccbfd 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -119,6 +119,8 @@
Base::StatGroup::StatGroup(statistics::Group *parent)
: statistics::Group(parent),
+ADD_STAT(demandMshrMisses, statistics::units::Count::get(),
+"demands not covered by prefetchs"),
ADD_STAT(pfIssued, statistics::units::Count::get(),
"number of hwpf issued"),
ADD_STAT(pfUnused, statistics::units::Count::get(),
@@ -127,11 +129,22 @@
"number of useful prefetch"),
ADD_STAT(pfUsefulButMiss, statistics::units::Count::get(),
"number of hit on prefetch but cache block is not in an usable "
-"state")
+"state"),
+ADD_STAT(accuracy, statistics::units::Count::get(),
+"accuracy of the prefetcher"),
+ADD_STAT(coverage, statistics::units::Count::get(),
+"coverage brought by this prefetcher")
{
-pfUnused.flags(statistics::nozero);
-}
+using namespace statistics;
+pfUnused.flags(nozero);
+
+accuracy.flags(total);
+accuracy = pfUseful / pfIssued;
+
+coverage.flags(total);
+coverage = pfUseful / (pfUseful + demandMshrMisses);
+}
bool
Base::observeAccess(const PacketPtr , bool miss) const
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index 87b7f55..3bb5024 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -328,6 +328,7 @@
struct StatGroup : public statistics::Group
{
StatGroup(statistics::Group *parent);
+statistics::Scalar demandMshrMisses;
statistics::Scalar pfIssued;
/** The number of times a HW-prefetched block is evicted w/o
* reference. */
@@ -337,6 +338,8 @@
/** The number of times there is a hit on prefetch but cache block
* is not in an usable state */
statistics::Scalar pfUsefulButMiss;
+statistics::Formula accuracy;
+statistics::Formula coverage;
} prefetchStats;
/** Total prefetches issued */
@@ -381,6 +384,12 @@
prefetchStats.pfUseful++;
}
+virtual void
+incrDemandMhsrMisses()
+{
+prefetchStats.demandMshrMisses++;
+}
+
/**
* Register probe points for this object.
*/
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 7ae6626..cf18d00 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -248,6 +248,14 @@
bool isPrint() const{ return testCmdAttrib(IsPrint); }
bool isFlush() const{ return testCmdAttrib(IsFlush); }
+bool
+isDemand() const
+{
+return (cmd == ReadReq || cmd == WriteReq ||
+cmd == WriteLineReq || cmd == ReadExReq ||
+cmd == ReadCleanReq || cmd == ReadSharedReq);
+}
+
Command
responseCommand() const
{
@@ -574,6 +582,7 @@
bool isRead() const { return cmd.isRead(); }
bool isWrite() const { return
[gem5-dev] Change in gem5/gem5[develop]: mem-cache: move unusedPrefetches stat to prefetcher
Nathanael Premillieu has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47599 )
Change subject: mem-cache: move unusedPrefetches stat to prefetcher
..
mem-cache: move unusedPrefetches stat to prefetcher
This stat belongs to prefetchers.
It has been renamed to pfUnused to match the naming of
exisiting prefetcher stats.
Change-Id: Iec350a62da544535dfc0c2527fcdf73217ae4db7
---
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
4 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 61396f0..2f145be 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -1570,7 +1570,7 @@
{
// If block is still marked as prefetched, then it hasn't been used
if (blk->wasPrefetched()) {
-stats.unusedPrefetches++;
+prefetcher->prefetchUnused(blk);
}
// Notify that the data contents for this address are no longer present
@@ -2126,9 +2126,8 @@
ADD_STAT(avgBlocked, statistics::units::Rate<
statistics::units::Cycle, statistics::units::Count>::get(),
"average number of cycles each access was blocked"),
-ADD_STAT(unusedPrefetches, statistics::units::Count::get(),
- "number of HardPF blocks evicted w/o reference"),
-ADD_STAT(writebacks, statistics::units::Count::get(), "number of
writebacks"),
+ADD_STAT(writebacks, statistics::units::Count::get(),
+ "number of writebacks"),
ADD_STAT(demandMshrHits, statistics::units::Count::get(),
"number of demand (read+write) MSHR hits"),
ADD_STAT(overallMshrHits, statistics::units::Count::get(),
@@ -2287,8 +2286,6 @@
;
avgBlocked = blockedCycles / blockedCauses;
-unusedPrefetches.flags(nozero);
-
writebacks
.init(max_requestors)
.flags(total | nozero | nonan)
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 581edf9..2afad5f 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -1084,10 +1084,6 @@
/** The average number of cycles blocked for each blocked cause. */
statistics::Formula avgBlocked;
-/** The number of times a HW-prefetched block is evicted w/o
- * reference. */
-statistics::Scalar unusedPrefetches;
-
/** Number of blocks written back per thread. */
statistics::Vector writebacks;
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index b5be0f9..58a7439 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -120,8 +120,11 @@
Base::StatGroup::StatGroup(statistics::Group *parent)
: statistics::Group(parent),
ADD_STAT(pfIssued, statistics::units::Count::get(),
-"number of hwpf issued")
+"number of hwpf issued"),
+ADD_STAT(pfUnused, statistics::units::Count::get(),
+ "number of HardPF blocks evicted w/o reference")
{
+pfUnused.flags(statistics::nozero);
}
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index 059f814..a4c3b97 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -52,6 +52,7 @@
#include "base/compiler.hh"
#include "base/statistics.hh"
#include "base/types.hh"
+#include "mem/cache/cache_blk.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "sim/byteswap.hh"
@@ -328,6 +329,9 @@
{
StatGroup(statistics::Group *parent);
statistics::Scalar pfIssued;
+/** The number of times a HW-prefetched block is evicted w/o
+ * reference. */
+statistics::Scalar pfUnused;
} prefetchStats;
/** Total prefetches issued */
@@ -358,6 +362,12 @@
virtual Tick nextPrefetchReadyTime() const = 0;
+virtual void
+prefetchUnused(CacheBlk * blk)
+{
+assert(blk->wasPrefetched());
+prefetchStats.pfUnused++;
+}
/**
* Register probe points for this object.
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: print when hitting on a prefetched line
Nathanael Premillieu has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47601 )
Change subject: mem-cache: print when hitting on a prefetched line
..
mem-cache: print when hitting on a prefetched line
Only print it on the first it on a prefetched line
(as the prefetched flag is removed after the first hit)
This is useful when debugging prefetchers.
Change-Id: Id67cc957c7366a244bedad93824a3c4fdf2055b5
---
M src/mem/cache/base.cc
1 file changed, 2 insertions(+), 0 deletions(-)
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 2f145be..303ae72 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -380,6 +380,8 @@
ppHit->notify(pkt);
if (prefetcher && blk && blk->wasPrefetched()) {
+DPRINTF(Cache, "Hit on prefetch for addr %#x on blk: %s\n",
+pkt->getAddr(), blk->print());
blk->clearPrefetched();
}
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: add a prefetch useful stat
Nathanael Premillieu has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47602 )
Change subject: mem-cache: add a prefetch useful stat
..
mem-cache: add a prefetch useful stat
Count how many time a prefetch is useful, meaning
a hit has happened on a prefetched cache block.
Another stat (pfUsefulButMiss) has been added to count
the special case where there is a hit on prefetched block
but it is counted as a miss because the block is not in
the requested coherency state.
Change-Id: I253216b9ac96d5f21139b710c489d6eb3fce7136
---
M src/mem/cache/base.cc
M src/mem/cache/prefetch/base.cc
M src/mem/cache/prefetch/base.hh
3 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 303ae72..17895ce 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -380,6 +380,7 @@
ppHit->notify(pkt);
if (prefetcher && blk && blk->wasPrefetched()) {
+prefetcher->prefetchUseful(blk);
DPRINTF(Cache, "Hit on prefetch for addr %#x on blk: %s\n",
pkt->getAddr(), blk->print());
blk->clearPrefetched();
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index 58a7439..724cebf 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -122,7 +122,12 @@
ADD_STAT(pfIssued, statistics::units::Count::get(),
"number of hwpf issued"),
ADD_STAT(pfUnused, statistics::units::Count::get(),
- "number of HardPF blocks evicted w/o reference")
+ "number of HardPF blocks evicted w/o reference"),
+ADD_STAT(pfUseful, statistics::units::Count::get(),
+"number of useful prefetch"),
+ADD_STAT(pfUsefulButMiss, statistics::units::Count::get(),
+"number of hit on prefetch but cache block is not in an usable "
+"state")
{
pfUnused.flags(statistics::nozero);
}
@@ -219,6 +224,10 @@
if (hasBeenPrefetched(pkt->getAddr(), pkt->isSecure())) {
usefulPrefetches += 1;
+if (miss)
+// This case happens when a demand hits on a prefetched line
+// that's not in the requested coherency state.
+prefetchStats.pfUsefulButMiss++;
}
// Verify this access type is observed by prefetcher
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index a4c3b97..87b7f55 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -332,6 +332,11 @@
/** The number of times a HW-prefetched block is evicted w/o
* reference. */
statistics::Scalar pfUnused;
+/** The number of times a HW-prefetch is useful. */
+statistics::Scalar pfUseful;
+/** The number of times there is a hit on prefetch but cache block
+ * is not in an usable state */
+statistics::Scalar pfUsefulButMiss;
} prefetchStats;
/** Total prefetches issued */
@@ -369,6 +374,13 @@
prefetchStats.pfUnused++;
}
+virtual void
+prefetchUseful(CacheBlk *blk)
+{
+assert(blk->wasPrefetched());
+prefetchStats.pfUseful++;
+}
+
/**
* Register probe points for this object.
*/
--
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: add pfIssued stat in MultiPrefetcher
Nathanael Premillieu has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47600 )
Change subject: mem-cache: add pfIssued stat in MultiPrefetcher
..
mem-cache: add pfIssued stat in MultiPrefetcher
Count issued prefetches for each prefetchter in a MultiPrefetcher
Change-Id: If03fb0669af9bb92ce9cf210b6201a9719a7c771
---
M src/mem/cache/prefetch/multi.cc
1 file changed, 1 insertion(+), 0 deletions(-)
diff --git a/src/mem/cache/prefetch/multi.cc
b/src/mem/cache/prefetch/multi.cc
index ab3a90d..47f1816 100644
--- a/src/mem/cache/prefetch/multi.cc
+++ b/src/mem/cache/prefetch/multi.cc
@@ -77,6 +77,7 @@
if (pf->nextPrefetchReadyTime() <= curTick()) {
PacketPtr pkt = pf->getPacket();
panic_if(!pkt, "Prefetcher is ready but didn't return a
packet.");
+prefetchStats.pfIssued++;
return pkt;
}
}
--
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[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add clone support
Sandipan Das has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/47579 )
Change subject: arch-power: Add clone support
..
arch-power: Add clone support
This adds support for the clone() system call using
which multiple cpus can be utilized in SE mode. For
this change, it should be noted that Linux on Power
uses the CLONE_BACKWARDS argument order.
Change-Id: Iac91a7d110d9f7a133b8e102ac113f48a431a0d6
Signed-off-by: Kevin Joe <0keik...@gmail.com>
Signed-off-by: Chetan Agarwal
Signed-off-by: Sandipan Das
---
M src/arch/power/linux/linux.hh
M src/arch/power/linux/se_workload.cc
M src/arch/power/regs/int.hh
3 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/src/arch/power/linux/linux.hh b/src/arch/power/linux/linux.hh
index cdb1cda..646d642 100644
--- a/src/arch/power/linux/linux.hh
+++ b/src/arch/power/linux/linux.hh
@@ -32,6 +32,9 @@
#include
+#include "arch/power/isa.hh"
+#include "arch/power/regs/int.hh"
+#include "cpu/thread_context.hh"
#include "kern/linux/linux.hh"
namespace gem5
@@ -214,6 +217,21 @@
return false;
}
}
+
+static void
+archClone(uint64_t flags,
+ Process *pp, Process *cp,
+ ThreadContext *ptc, ThreadContext *ctc,
+ uint64_t stack, uint64_t tls)
+{
+ctc->getIsaPtr()->copyRegsFrom(ptc);
+
+if (flags & TGT_CLONE_SETTLS)
+ctc->setIntReg(PowerISA::ThreadPointerReg, tls);
+
+if (stack)
+ctc->setIntReg(PowerISA::StackPointerReg, stack);
+}
};
} // namespace gem5
diff --git a/src/arch/power/linux/se_workload.cc
b/src/arch/power/linux/se_workload.cc
index 9d5f9de..b49cb0b 100644
--- a/src/arch/power/linux/se_workload.cc
+++ b/src/arch/power/linux/se_workload.cc
@@ -227,7 +227,7 @@
{ 117, "ipc" },
{ 118, "fsync" },
{ 119, "sigreturn" },
-{ 120, "clone" },
+{ 120, "clone", cloneBackwardsFunc },
{ 121, "setdomainname" },
{ 122, "uname", unameFunc },
{ 123, "modify_ldt" },
diff --git a/src/arch/power/regs/int.hh b/src/arch/power/regs/int.hh
index 891eaa1..95fbb8a 100644
--- a/src/arch/power/regs/int.hh
+++ b/src/arch/power/regs/int.hh
@@ -55,6 +55,7 @@
const int ArgumentReg5 = 8;
const int StackPointerReg = 1;
const int TOCPointerReg = 2;
+const int ThreadPointerReg = 13;
enum MiscIntRegNums
{
--
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