[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: Revert "Split up read/write and read only CSR instructions."

2021-07-14 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Attention is currently required from: Daniel Carvalho, Bobby R. Bruce, Gabe  
Black, Ayaz Akram.

Hello kokoro, Daniel Carvalho, Bobby R. Bruce, Gabe Black, Ayaz Akram,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/48099

to review the following change.


Change subject: arch-riscv: Revert "Split up read/write and read only CSR  
instructions."

..

arch-riscv: Revert "Split up read/write and read only CSR instructions."

This reverts commit 1cf41d4c54c988ef4808d8efc1f6212e54a4c120.

Reason for revert:

The above commit caused booting Linux using RISCV either to
hang or to take significantly time more than to finish.

For the v21-1 release, the above commit will be reverted.

Change-Id: I58fbe96d7ea50031eba40ff49dabdef971faf6ff
---
M src/arch/riscv/isa/formats/standard.isa
1 file changed, 46 insertions(+), 94 deletions(-)



diff --git a/src/arch/riscv/isa/formats/standard.isa  
b/src/arch/riscv/isa/formats/standard.isa

index dba460f..e0b270b 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -274,7 +274,7 @@
 }
 }};

-def template CSRExecuteRo {{
+def template CSRExecute {{
 Fault
 %(class_name)s::execute(ExecContext *xc,
 Trace::InstRecord *traceData) const
@@ -287,6 +287,8 @@
 %(op_decl)s;
 %(op_rd)s;

+RegVal data, olddata;
+
 switch (csr) {
   case CSR_SATP: {
 auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
@@ -311,91 +313,55 @@
 break;
 }

-RegVal data;
 if (csr == CSR_FCSR) {
-data = xc->readMiscReg(MISCREG_FFLAGS) |
-   (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
-} else {
-data = xc->readMiscReg(midx);
-}
-
-DPRINTF(RiscvMisc, "Reading CSR %s: %#x\n", csrName, data);
-
-%(code)s;
-%(op_wb)s;
-
-return NoFault;
-}
-}};
-
-def template CSRExecuteRw {{
-Fault
-%(class_name)s::execute(ExecContext *xc,
-Trace::InstRecord *traceData) const
-{
-if (!valid) {
-return std::make_shared(
-csprintf("Illegal CSR index %#x\n", csr), machInst);
-}
-if (bits(csr, 11, 10) == 0x3) {
-return std::make_shared(
-csprintf("CSR %s is read-only\n", csrName), machInst);
-}
-
-%(op_decl)s;
-%(op_rd)s;
-
-switch (csr) {
-  case CSR_SATP: {
-auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
-STATUS status = xc->readMiscReg(MISCREG_STATUS);
-if (pm == PRV_U || (pm == PRV_S && status.tvm == 1)) {
-return std::make_shared(
-"SATP access in user mode or with TVM enabled\n",
-machInst);
-}
-break;
-  }
-  case CSR_MSTATUS: {
-auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
-if (pm != PrivilegeMode::PRV_M) {
-return std::make_shared(
-"MSTATUS is only accessibly in machine mode\n",
-machInst);
-}
-break;
-  }
-  default:
-break;
-}
-
-RegVal data;
-if (csr == CSR_FCSR) {
-data = xc->readMiscReg(MISCREG_FFLAGS) |
+olddata = xc->readMiscReg(MISCREG_FFLAGS) |
   (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
 } else {
-data = xc->readMiscReg(midx);
+olddata = xc->readMiscReg(midx);
 }
+auto olddata_all = olddata;

-RegVal original = data;
-
-DPRINTF(RiscvMisc, "Reading CSR %s: %#x\n", csrName, data &  
maskVal);

+olddata &= maskVal;
+DPRINTF(RiscvMisc, "Reading CSR %s: %#x\n", csrName, olddata);
+data = olddata;

 %(code)s;

-// We must keep those original bits not in the mask. Hidden bits  
should

-// keep their original value.
-data = (original & ~maskVal) | (data & maskVal);
-
-DPRINTF(RiscvMisc, "Writing %#x to CSR %s.\n", data, csrName);
-
-if (csr == CSR_FCSR) {
-xc->setMiscReg(MISCREG_FFLAGS, bits(data, 4, 0));
-xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5));
-} else {
-xc->setMiscReg(midx, data);
+data &= maskVal;
+if (data != olddata) {
+if (bits(csr, 11, 10) == 0x3) {
+return std::make_shared(
+csprintf("CSR %s is read-only\n", csrName),  
machInst);

+}
+auto newdata_all = data;
+// We must keep those original bits not in mask.
+// olddata and data only contain the bits visable
+// in current privilige level.
+newdata_all =

[gem5-dev] Change in gem5/gem5[develop]: cpu: remove O3 dependency of CheckerCPU

2021-07-14 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48080 )



Change subject: cpu: remove O3 dependency of CheckerCPU
..

cpu: remove O3 dependency of CheckerCPU

Currently, compiling CheckerCPU uses the dyn_inst.hh header from
O3CPU. However, including this header is not required and it
causes gem5 failed to build when O3CPU is not part of CPU_MODELS.

This change also involves moving the the dependency on
src/cpu/o3/dyn_inst.hh to src/cpu/o3/cpu.cc and src/cpu/lsq_unit.cc,
which previously includes src/cpu/o3/dyn_inst.hh implicitly through
src/cpu/checker/cpu.hh.

JIRA: https://gem5.atlassian.net/browse/GEM5-1025

Change-Id: I7664cd4b9591bf0a4635338fff576cb5f5cbfa10
Signed-off-by: Hoa Nguyen 
---
M src/cpu/checker/cpu.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/lsq_unit.cc
3 files changed, 2 insertions(+), 1 deletion(-)



diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index aebf522..a191ae4 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -51,7 +51,6 @@
 #include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/inst_res.hh"
-#include "cpu/o3/dyn_inst.hh"
 #include "cpu/pc_event.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/static_inst.hh"
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index fbdfcbd..e352236 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -46,6 +46,7 @@
 #include "cpu/activity.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/checker/thread_context.hh"
+#include "cpu/o3/dyn_inst.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/o3/thread_context.hh"
 #include "cpu/simple_thread.hh"
diff --git a/src/cpu/o3/lsq_unit.cc b/src/cpu/o3/lsq_unit.cc
index 5394e4f..039184d 100644
--- a/src/cpu/o3/lsq_unit.cc
+++ b/src/cpu/o3/lsq_unit.cc
@@ -46,6 +46,7 @@
 #include "base/str.hh"
 #include "config/the_isa.hh"
 #include "cpu/checker/cpu.hh"
+#include "cpu/o3/dyn_inst.hh"
 #include "cpu/o3/limits.hh"
 #include "cpu/o3/lsq.hh"
 #include "debug/Activity.hh"

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7664cd4b9591bf0a4635338fff576cb5f5cbfa10
Gerrit-Change-Number: 48080
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[release-staging-v21-1]: arch-gcn3: Free dest registers in non-memory Load DS insts

2021-07-14 Thread Kyle Roarty (Gerrit) via gem5-dev 
Kyle Roarty has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48019 )


Change subject: arch-gcn3: Free dest registers in non-memory Load DS insts
..

arch-gcn3: Free dest registers in non-memory Load DS insts

Certain DS insts are classfied as Loads, but don't actually go through
the memory pipeline. However, any instruction classified as a load
marks its destination registers as free in the memory pipeline.

Because these instructions didn't use the memory pipeline, they
never freed their destination registers, which led to a deadlock.

This patch explicitly calls the function used to free the destination
registers in the execute() method of those Load instructions that
don't use the memory pipeline.

Change-Id: Ic2ac2e232c8fbad63d0c62c1862f2bdaeaba4edf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48019
Reviewed-by: Matt Sinclair 
Reviewed-by: Bobby R. Bruce 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/arch/amdgpu/gcn3/insts/instructions.cc
1 file changed, 27 insertions(+), 0 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/amdgpu/gcn3/insts/instructions.cc  
b/src/arch/amdgpu/gcn3/insts/instructions.cc

index a421454..21ab58d 100644
--- a/src/arch/amdgpu/gcn3/insts/instructions.cc
+++ b/src/arch/amdgpu/gcn3/insts/instructions.cc
@@ -32397,6 +32397,15 @@
 }

 vdst.write();
+
+/**
+ * This is needed because we treat this instruction as a load
+ * but it's not an actual memory request.
+ * Without this, the destination register never gets marked as
+ * free, leading to a  possible deadlock
+ */
+wf->computeUnit->vrf[wf->simdId]->
+scheduleWriteOperandsFromLoad(wf, gpuDynInst);
 } // execute
 // --- Inst_DS__DS_PERMUTE_B32 class methods ---

@@ -32468,6 +32477,15 @@
 wf->decLGKMInstsIssued();
 wf->rdLmReqsInPipe--;
 wf->validateRequestCounters();
+
+/**
+ * This is needed because we treat this instruction as a load
+ * but it's not an actual memory request.
+ * Without this, the destination register never gets marked as
+ * free, leading to a  possible deadlock
+ */
+wf->computeUnit->vrf[wf->simdId]->
+scheduleWriteOperandsFromLoad(wf, gpuDynInst);
 } // execute
 // --- Inst_DS__DS_BPERMUTE_B32 class methods ---

@@ -32539,6 +32557,15 @@
 wf->decLGKMInstsIssued();
 wf->rdLmReqsInPipe--;
 wf->validateRequestCounters();
+
+/**
+ * This is needed because we treat this instruction as a load
+ * but it's not an actual memory request.
+ * Without this, the destination register never gets marked as
+ * free, leading to a possible deadlock
+ */
+wf->computeUnit->vrf[wf->simdId]->
+scheduleWriteOperandsFromLoad(wf, gpuDynInst);
 } // execute

 // --- Inst_DS__DS_ADD_U64 class methods ---

--
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v21-1
Gerrit-Change-Id: Ic2ac2e232c8fbad63d0c62c1862f2bdaeaba4edf
Gerrit-Change-Number: 48019
Gerrit-PatchSet: 2
Gerrit-Owner: Kyle Roarty 
Gerrit-Reviewer: Alex Dutu 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[release-staging-v21-1]: gpu-compute: Fix off-by-one when creating an AddrRange

2021-07-14 Thread Kyle Roarty (Gerrit) via gem5-dev 
Kyle Roarty has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48020 )


Change subject: gpu-compute: Fix off-by-one when creating an AddrRange
..

gpu-compute: Fix off-by-one when creating an AddrRange

The end value of an AddrRange is already not included in the range,
so subtracting one from the end creates an off-by-one error.

This patch removes the extra -1 that was used when determining the
end of an AddrRange in allocateGpuVma

Change-Id: I75659e9a7fabd991bb37be9aa40f8e409eb21154
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48020
Reviewed-by: Matt Sinclair 
Reviewed-by: Bobby R. Bruce 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/gpu-compute/gpu_compute_driver.cc
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Matt Sinclair: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/gpu-compute/gpu_compute_driver.cc  
b/src/gpu-compute/gpu_compute_driver.cc

index 92ac641..f794b43 100644
--- a/src/gpu-compute/gpu_compute_driver.cc
+++ b/src/gpu-compute/gpu_compute_driver.cc
@@ -985,7 +985,7 @@
 GPUComputeDriver::allocateGpuVma(Request::CacheCoherenceFlags mtype,
  Addr start, Addr length)
 {
-AddrRange range = AddrRange(start, start + length - 1);
+AddrRange range = AddrRange(start, start + length);
 DPRINTF(GPUDriver, "Registering [%p - %p] with MTYPE %d\n",
 range.start(), range.end(), mtype);
 fatal_if(gpuVmas.insert(range, mtype) == gpuVmas.end(),

--
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Gerrit-Change-Id: I75659e9a7fabd991bb37be9aa40f8e409eb21154
Gerrit-Change-Number: 48020
Gerrit-PatchSet: 2
Gerrit-Owner: Kyle Roarty 
Gerrit-Reviewer: Alex Dutu 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: cpu: remove O3 dependency of CheckerCPU

2021-07-14 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48079 )



Change subject: cpu: remove O3 dependency of CheckerCPU
..

cpu: remove O3 dependency of CheckerCPU

Currently, compiling CheckerCPU uses the dyn_inst.hh header from
O3CPU. However, including this header is not required and it
causes gem5 failed to build when O3CPU is not part of CPU_MODELS.

JIRA: https://gem5.atlassian.net/browse/GEM5-1025

Change-Id: I7664cd4b9591bf0a4635338fff576cb5f5cbfa10
Signed-off-by: Hoa Nguyen 
---
M src/cpu/checker/cpu.hh
1 file changed, 0 insertions(+), 1 deletion(-)



diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index aebf522..a191ae4 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -51,7 +51,6 @@
 #include "cpu/base.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/inst_res.hh"
-#include "cpu/o3/dyn_inst.hh"
 #include "cpu/pc_event.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/static_inst.hh"

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I7664cd4b9591bf0a4635338fff576cb5f5cbfa10
Gerrit-Change-Number: 48079
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
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[gem5-dev] Change in gem5/gem5[release-staging-v21-1]: docker-util,gpu-compute: Move ROCclr.patch to the repo

2021-07-14 Thread Bobby R. Bruce (Gerrit) via gem5-dev 
Bobby R. Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48059 )



Change subject: docker-util,gpu-compute: Move ROCclr.patch to the repo
..

docker-util,gpu-compute: Move ROCclr.patch to the repo

This was previously pulled from our Cloud Bucket. This doesn't seem
necessary for such a small patch. Keep this in the repo will make it
easier to change, if needed, in future revisions.

Change-Id: I9b7dbafcd3e750222972850b98fa317aed9d5881
---
M util/dockerfiles/gcn-gpu/Dockerfile
A util/dockerfiles/gcn-gpu/ROCclr.patch
2 files changed, 52 insertions(+), 1 deletion(-)



diff --git a/util/dockerfiles/gcn-gpu/Dockerfile  
b/util/dockerfiles/gcn-gpu/Dockerfile

index 360ab1f..807f7da 100644
--- a/util/dockerfiles/gcn-gpu/Dockerfile
+++ b/util/dockerfiles/gcn-gpu/Dockerfile
@@ -25,6 +25,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 FROM ubuntu:20.04
 ENV DEBIAN_FRONTEND=noninteractive
+
 RUN apt -y update
 RUN apt -y upgrade
 RUN apt -y install build-essential git m4 scons zlib1g zlib1g-dev \
@@ -70,7 +71,8 @@

 WORKDIR /ROCclr
 # The patch allows us to avoid building blit kernels on-the-fly in gem5
-RUN wget -q -O - dist.gem5.org/dist/develop/rocm_patches/ROCclr.patch |  
git apply -v

+COPY ROCclr.patch /ROCclr/ROCclr.patch
+RUN git apply -v ROCclr.patch

 WORKDIR /ROCclr/build
 RUN cmake -DOPENCL_DIR="/ROCm-OpenCL-Runtime" \
diff --git a/util/dockerfiles/gcn-gpu/ROCclr.patch  
b/util/dockerfiles/gcn-gpu/ROCclr.patch

new file mode 100644
index 000..0606298
--- /dev/null
+++ b/util/dockerfiles/gcn-gpu/ROCclr.patch
@@ -0,0 +1,49 @@
+diff --git a/device/rocm/rocblit.cpp b/device/rocm/rocblit.cpp
+index 716790c8..67b37913 100644
+--- a/device/rocm/rocblit.cpp
 b/device/rocm/rocblit.cpp
+@@ -794,29 +794,7 @@ bool KernelBlitManager::createProgram(Device& device)  
{

+   // Save context and program for this device
+   context_ = device.blitProgram()->context_;
+   context_->retain();
+-  program_ = device.blitProgram()->program_;
+-  program_->retain();
+-
+-  bool result = false;
+-  do {
+-// Create kernel objects for all blits
+-for (uint i = 0; i < BlitTotal; ++i) {
+-  const amd::Symbol* symbol = program_->findSymbol(BlitName[i]);
+-  if (symbol == nullptr) {
+-break;
+-  }
+-  kernels_[i] = new amd::Kernel(*program_, *symbol, BlitName[i]);
+-  if (kernels_[i] == nullptr) {
+-break;
+-  }
+-  // Validate blit kernels for the scratch memory usage (pre SI)
+-  if (!device.validateKernel(*kernels_[i], ())) {
+-break;
+-  }
+-}
+-
+-result = true;
+-  } while (!result);
++  bool result = true;
+
+   // Create an internal constant buffer
+   constantBuffer_ = new (*context_) amd::Buffer(*context_,  
CL_MEM_ALLOC_HOST_PTR, 4 * Ki);

+diff --git a/device/rocm/rocdevice.cpp b/device/rocm/rocdevice.cpp
+index 32cc259c..97950ed7 100755
+--- a/device/rocm/rocdevice.cpp
 b/device/rocm/rocdevice.cpp
+@@ -794,6 +794,9 @@ bool Device::createBlitProgram() {
+ #endif  // USE_COMGR_LIBRARY
+
+   blitProgram_ = new BlitProgram(context_);
++  if (blitProgram_ != nullptr) {
++return true;
++  }
+   // Create blit programs
+   if (blitProgram_ == nullptr || !blitProgram_->create(this, scheduler)) {
+ delete blitProgram_;

--
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Gerrit-Change-Number: 48059
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Gerrit-Owner: Bobby R. Bruce 
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[gem5-dev] Change in gem5/gem5[release-staging-v21-1]: arch-arm: Fixes an error related to HTM error code handling

2021-07-14 Thread Javier Garcia (Gerrit) via gem5-dev 
Javier Garcia has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/47939 )


Change subject: arch-arm: Fixes an error related to HTM error code handling
..

arch-arm: Fixes an error related to HTM error code handling

Arguments of the function bits(), called in restore method,
are the other way around.

This leads to wrong retry handling.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1041

Change-Id: I0748b1cad57bea5527ca585852d183bd75b4c9ef
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47939
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/htm.cc
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/htm.cc b/src/arch/arm/htm.cc
index 0062b56..e94e437 100644
--- a/src/arch/arm/htm.cc
+++ b/src/arch/arm/htm.cc
@@ -129,7 +129,7 @@
   case HtmFailureFaultCause::EXPLICIT:
 replaceBits(error_code, 14, 0, tcreason);
 replaceBits(error_code, 16, 1);
-retry = bits(15, tcreason);
+retry = bits(tcreason, 15);
 break;
   case HtmFailureFaultCause::MEMORY:
 replaceBits(error_code, 17, 1);

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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v21-1
Gerrit-Change-Id: I0748b1cad57bea5527ca585852d183bd75b4c9ef
Gerrit-Change-Number: 47939
Gerrit-PatchSet: 3
Gerrit-Owner: Javier Garcia 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Javier Garcia 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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