[gem5-dev] Change in gem5/gem5[master]: misc: Test
Hoa Nguyen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/48223 ) Change subject: misc: Test .. misc: Test Change-Id: Ie28dd4b13ee36b5f4c0a27646645180dd211e90a --- A hello 1 file changed, 1 insertion(+), 0 deletions(-) diff --git a/hello b/hello new file mode 100644 index 000..9daeafb --- /dev/null +++ b/hello @@ -0,0 +1 @@ +test -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/48223 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ie28dd4b13ee36b5f4c0a27646645180dd211e90a Gerrit-Change-Number: 48223 Gerrit-PatchSet: 1 Gerrit-Owner: Hoa Nguyen Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[stable]: misc: Test
Hoa Nguyen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/48222 ) Change subject: misc: Test .. misc: Test Change-Id: I99f6723061e3564c63b94fe5dd309cfdc32202f1 --- A hello 1 file changed, 1 insertion(+), 0 deletions(-) diff --git a/hello b/hello new file mode 100644 index 000..9daeafb --- /dev/null +++ b/hello @@ -0,0 +1 @@ +test -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/48222 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: stable Gerrit-Change-Id: I99f6723061e3564c63b94fe5dd309cfdc32202f1 Gerrit-Change-Number: 48222 Gerrit-PatchSet: 1 Gerrit-Owner: Hoa Nguyen Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[stable]: misc: Test
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/48221 ) Change subject: misc: Test .. misc: Test Change-Id: Iaa21175b402250172a31d216d3a770359d4cc024 --- A hello 1 file changed, 1 insertion(+), 0 deletions(-) diff --git a/hello b/hello new file mode 100644 index 000..9daeafb --- /dev/null +++ b/hello @@ -0,0 +1 @@ +test -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/48221 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: stable Gerrit-Change-Id: Iaa21175b402250172a31d216d3a770359d4cc024 Gerrit-Change-Number: 48221 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[master]: misc: Test
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/48220 ) Change subject: misc: Test .. misc: Test Change-Id: Iaa21175b402250172a31d216d3a770359d4cc024 --- A hello 1 file changed, 1 insertion(+), 0 deletions(-) diff --git a/hello b/hello new file mode 100644 index 000..9daeafb --- /dev/null +++ b/hello @@ -0,0 +1 @@ +test -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/48220 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Iaa21175b402250172a31d216d3a770359d4cc024 Gerrit-Change-Number: 48220 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby R. Bruce Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[release-staging-v21-1]: arch-riscv: Revert change-45522
Hoa Nguyen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/48099 )
Change subject: arch-riscv: Revert change-45522
..
arch-riscv: Revert change-45522
This reverts change:
https://gem5-review.googlesource.com/c/public/gem5/+/45522.
This reverts commit 1cf41d4c54c988ef4808d8efc1f6212e54a4c120.
Reason for revert:
The above commit caused booting Linux using RISCV either to
hang or to take significantly time more than to finish.
For the v21-1 release, the above commit will be reverted.
JIRA: https://gem5.atlassian.net/browse/GEM5-1043
Change-Id: I58fbe96d7ea50031eba40ff49dabdef971faf6ff
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48099
Reviewed-by: Bobby R. Bruce
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/arch/riscv/isa/formats/standard.isa
1 file changed, 46 insertions(+), 94 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/isa/formats/standard.isa
b/src/arch/riscv/isa/formats/standard.isa
index edb2268..dad2c2b 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -274,7 +274,7 @@
}
}};
-def template CSRExecuteRo {{
+def template CSRExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
@@ -287,6 +287,8 @@
%(op_decl)s;
%(op_rd)s;
+RegVal data, olddata;
+
switch (csr) {
case CSR_SATP: {
auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
@@ -311,91 +313,55 @@
break;
}
-RegVal data;
if (csr == CSR_FCSR) {
-data = xc->readMiscReg(MISCREG_FFLAGS) |
- (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
-} else {
-data = xc->readMiscReg(midx);
-}
-
-DPRINTF(RiscvMisc, "Reading CSR %s: %#x\n", csrName, data);
-
-%(code)s;
-%(op_wb)s;
-
-return NoFault;
-}
-}};
-
-def template CSRExecuteRw {{
-Fault
-%(class_name)s::execute(ExecContext *xc,
-Trace::InstRecord *traceData) const
-{
-if (!valid) {
-return std::make_shared(
-csprintf("Illegal CSR index %#x\n", csr), machInst);
-}
-if (bits(csr, 11, 10) == 0x3) {
-return std::make_shared(
-csprintf("CSR %s is read-only\n", csrName), machInst);
-}
-
-%(op_decl)s;
-%(op_rd)s;
-
-switch (csr) {
- case CSR_SATP: {
-auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
-STATUS status = xc->readMiscReg(MISCREG_STATUS);
-if (pm == PRV_U || (pm == PRV_S && status.tvm == 1)) {
-return std::make_shared(
-"SATP access in user mode or with TVM enabled\n",
-machInst);
-}
-break;
- }
- case CSR_MSTATUS: {
-auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
-if (pm != PrivilegeMode::PRV_M) {
-return std::make_shared(
-"MSTATUS is only accessibly in machine mode\n",
-machInst);
-}
-break;
- }
- default:
-break;
-}
-
-RegVal data;
-if (csr == CSR_FCSR) {
-data = xc->readMiscReg(MISCREG_FFLAGS) |
+olddata = xc->readMiscReg(MISCREG_FFLAGS) |
(xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
} else {
-data = xc->readMiscReg(midx);
+olddata = xc->readMiscReg(midx);
}
+auto olddata_all = olddata;
-RegVal original = data;
-
-DPRINTF(RiscvMisc, "Reading CSR %s: %#x\n", csrName, data &
maskVal);
+olddata &= maskVal;
+DPRINTF(RiscvMisc, "Reading CSR %s: %#x\n", csrName, olddata);
+data = olddata;
%(code)s;
-// We must keep those original bits not in the mask. Hidden bits
should
-// keep their original value.
-data = (original & ~maskVal) | (data & maskVal);
-
-DPRINTF(RiscvMisc, "Writing %#x to CSR %s.\n", data, csrName);
-
-if (csr == CSR_FCSR) {
-xc->setMiscReg(MISCREG_FFLAGS, bits(data, 4, 0));
-xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5));
-} else {
-xc->setMiscReg(midx, data);
+data &= maskVal;
+if (data != olddata) {
+if (bits(csr, 11, 10) == 0x3) {
+return std::make_shared(
+csprintf("CSR %s is read-only\n", csrName),
machInst);
+}
+auto newdata_all = data;
+// We must keep those original bits not in mask.
+// olddata and data only
[gem5-dev] Change in gem5/gem5[release-staging-v21-1]: arch-arm: Stage1&2 TableWalkers sharing same port
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/48200 )
Change subject: arch-arm: Stage1&2 TableWalkers sharing same port
..
arch-arm: Stage1&2 TableWalkers sharing same port
This patch reverts part of the changes made by the removal of
the Stage2MMU class [1]:
Prior to that patch the stage1 and stage2 walkers were sharing
the same port (which was instantiated in the Stage2MMU).
By removing the Stage2MMU we provided every table walker a
unique port.
With this patch we are reintroducing port sharing to temporarily fix
existing platforms using walker caches.
(The long term design goal will be to have a unique page table walker)
Those complain if we try to connect a single ported cache to 2 table
walker ports (stage1 and stage2)
[1]: https://gem5-review.googlesource.com/c/public/gem5/+/45780
Change-Id: Ib68ef97f1e9772a698771269c9a4ec4514f5d4d7
Signed-off-by: Giacomo Travaglini
---
M src/arch/arm/ArmMMU.py
M src/arch/arm/mmu.cc
M src/arch/arm/mmu.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
5 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/src/arch/arm/ArmMMU.py b/src/arch/arm/ArmMMU.py
index 00a0b31..1880f6f 100644
--- a/src/arch/arm/ArmMMU.py
+++ b/src/arch/arm/ArmMMU.py
@@ -65,6 +65,8 @@
itb = ArmITB()
dtb = ArmDTB()
+sys = Param.System(Parent.any, "system object parameter")
+
stage2_itb = Param.ArmTLB(ArmStage2TLB(), "Stage 2 Instruction TLB")
stage2_dtb = Param.ArmTLB(ArmStage2TLB(), "Stage 2 Data TLB")
@@ -80,12 +82,8 @@
@classmethod
def walkerPorts(cls):
-return ["mmu.itb_walker.port", "mmu.dtb_walker.port",
-"mmu.stage2_itb_walker.port", "mmu.stage2_dtb_walker.port"]
+return ["mmu.itb_walker.port", "mmu.dtb_walker.port"]
def connectWalkerPorts(self, iport, dport):
self.itb_walker.port = iport
self.dtb_walker.port = dport
-
-self.stage2_itb_walker.port = iport
-self.stage2_dtb_walker.port = dport
diff --git a/src/arch/arm/mmu.cc b/src/arch/arm/mmu.cc
index 7392947..30164b6 100644
--- a/src/arch/arm/mmu.cc
+++ b/src/arch/arm/mmu.cc
@@ -47,10 +47,17 @@
MMU::MMU(const ArmMMUParams )
: BaseMMU(p),
itbStage2(p.stage2_itb), dtbStage2(p.stage2_dtb),
+iport(p.itb_walker, p.sys->getRequestorId(p.itb_walker)),
+dport(p.dtb_walker, p.sys->getRequestorId(p.dtb_walker)),
itbWalker(p.itb_walker), dtbWalker(p.dtb_walker),
itbStage2Walker(p.stage2_itb_walker),
dtbStage2Walker(p.stage2_dtb_walker)
-{}
+{
+itbWalker->setPort();
+dtbWalker->setPort();
+itbStage2Walker->setPort();
+dtbStage2Walker->setPort();
+}
void
MMU::init()
diff --git a/src/arch/arm/mmu.hh b/src/arch/arm/mmu.hh
index f9ebeb3..a129831 100644
--- a/src/arch/arm/mmu.hh
+++ b/src/arch/arm/mmu.hh
@@ -38,6 +38,7 @@
#ifndef __ARCH_ARM_MMU_HH__
#define __ARCH_ARM_MMU_HH__
+#include "arch/arm/table_walker.hh"
#include "arch/arm/tlb.hh"
#include "arch/generic/mmu.hh"
@@ -69,6 +70,9 @@
TLB *itbStage2;
TLB *dtbStage2;
+TableWalker::Port iport;
+TableWalker::Port dport;
+
TableWalker *itbWalker;
TableWalker *dtbWalker;
TableWalker *itbStage2Walker;
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 5632be1..6dc00eb 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -61,7 +61,7 @@
TableWalker::TableWalker(const Params )
: ClockedObject(p),
requestorId(p.sys->getRequestorId(this)),
- port(new Port(this, requestorId)),
+ port(nullptr),
isStage2(p.is_stage2), tlb(NULL),
currState(NULL), pending(false),
numSquashable(p.num_squash_per_cycle),
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 992e224..165a922 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -1037,6 +1037,7 @@
void setMmu(MMU *_mmu) { mmu = _mmu; }
void setTlb(TLB *_tlb) { tlb = _tlb; }
+void setPort(Port *_port) { port = _port; }
TLB* getTlb() { return tlb; }
void memAttrs(ThreadContext *tc, TlbEntry , SCTLR sctlr,
uint8_t texcb, bool s);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/48200
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v21-1
Gerrit-Change-Id: Ib68ef97f1e9772a698771269c9a4ec4514f5d4d7
Gerrit-Change-Number: 48200
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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