[gem5-dev] Change in gem5/gem5[develop]: tests: add DNNMark to weekly regression
Matt Sinclair has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/51187 )
Change subject: tests: add DNNMark to weekly regression
..
tests: add DNNMark to weekly regression
DNNMark is representative of several simple (fast) layers within ML
applications, which are heavily used in modern GPU applications. Thus,
we want to make sure support for these applications are tested. This
commit updates the weekly regression to run three variants: fwd_softmax,
bwd_bn, and fwd_pool -- ensuring we test both inference and training as
well as a variety of ML layers.
Change-Id: I38bfa9bd3a2817099ece46afc2d6132ce346e21a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51187
Reviewed-by: Bobby R. Bruce
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M tests/weekly.sh
1 file changed, 103 insertions(+), 1 deletion(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/tests/weekly.sh b/tests/weekly.sh
index b697c29..c699f65 100755
--- a/tests/weekly.sh
+++ b/tests/weekly.sh
@@ -58,4 +58,86 @@
# LULESH is heavily used in the HPC community on GPUs, and does a good job
of
# stressing several GPU compute and memory components
-docker run --rm -v ${PWD}:${PWD} -w ${PWD} -u $UID:$GID
gcr.io/gem5-test/gcn-gpu gem5/build/GCN3_X86/gem5.opt
gem5/configs/example/apu_se.py -n3 --mem-size=8GB
--benchmark-root=gem5-resources/src/gpu/lulesh/bin -clulesh
+docker run --rm -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \
+"${gem5_root}" gcr.io/gem5-test/gcn-gpu:latest build/GCN3_X86/gem5.opt
\
+configs/example/apu_se.py -n3 --mem-size=8GB -clulesh
+
+# get DNNMark
+# Delete gem5 resources repo if it already exists -- need to do in docker
+# because of cachefiles DNNMark creates
+docker run --rm --volume "${gem5_root}":"${gem5_root}" -w \
+ "${gem5_root}" gcr.io/gem5-test/gcn-gpu:latest bash -c \
+ "rm -rf ${gem5_root}/gem5-resources"
+
+# Pull the gem5 resources to the root of the gem5 directory -- DNNMark
+# builds a library and thus doesn't have a binary, so we need to build
+# it before we run it
+git clone -b develop https://gem5.googlesource.com/public/gem5-resources \
+"${gem5_root}/gem5-resources"
+
+# setup cmake for DNNMark
+docker run --rm -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \
+ "${gem5_root}/gem5-resources/src/gpu/DNNMark" \
+ gcr.io/gem5-test/gcn-gpu:latest bash -c "./setup.sh HIP"
+
+# make the DNNMark library
+docker run --rm -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \
+"${gem5_root}/gem5-resources/src/gpu/DNNMark/build" \
+gcr.io/gem5-test/gcn-gpu:latest bash -c "make -j${threads}"
+
+# generate cachefiles -- since we are testing gfx801 and 4 CUs (default
config)
+# in tester, we want cachefiles for this setup
+docker run --rm --volume "${gem5_root}":"${gem5_root}" -w \
+"${gem5_root}/gem5-resources/src/gpu/DNNMark" \
+"-v${gem5_root}/gem5-resources/src/gpu/DNNMark/cachefiles:/root/.cache/miopen/2.9.0"
\
+gcr.io/gem5-test/gcn-gpu:latest bash -c \
+"python3 generate_cachefiles.py cachefiles.csv --gfx-version=gfx801 \
+--num-cus=4"
+
+# generate mmap data for DNNMark (makes simulation much faster)
+docker run --rm -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \
+"${gem5_root}/gem5-resources/src/gpu/DNNMark"
gcr.io/gem5-test/gcn-gpu:latest bash -c \
+"g++ -std=c++0x generate_rand_data.cpp -o generate_rand_data"
+
+docker run --rm -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \
+"${gem5_root}/gem5-resources/src/gpu/DNNMark"
gcr.io/gem5-test/gcn-gpu:latest bash -c \
+"./generate_rand_data"
+
+# now we can run DNNMark!
+# DNNMark is representative of several simple (fast) layers within ML
+# applications, which are heavily used in modern GPU applications. So, we
want
+# to make sure support for these applications are tested. Run three
variants:
+# fwd_softmax, bwd_bn, fwd_pool; these tests ensure we run a variety of ML
kernels,
+# including both inference and training
+docker run --rm --volume "${gem5_root}":"${gem5_root}" -v \
+ "${gem5_root}/gem5-resources/src/gpu/DNNMark/cachefiles:/root/.cache/miopen/2.9.0"
\
+ -w "${gem5_root}/gem5-resources/src/gpu/DNNMark"
gcr.io/gem5-test/gcn-gpu \
+ "${gem5_root}/build/GCN3_X86/gem5.opt" "${gem5_root}/configs/example/apu_se.py"
-n3
\
+
--benchmark-root="${gem5_root}/gem5-resources/src/gpu/DNNMark/build/benchmarks/test_fwd_softmax"
\
+ -cdnnmark_test_fwd_softmax \
+ --options="-config
${gem5_root}/gem5-resources/src/gpu/DNNMark/config_example/softmax_config.dnnmark
\
+ -mmap ${gem5_root}/gem5-resources/src/gpu/DNNMark/mmap.bin"
+
+docker run --rm --volume "${gem5_root}":"${gem5_root}" -v \
+
[gem5-dev] Change in gem5/gem5[develop]: sim: Align process memory allocations.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/50757 )
Change subject: sim: Align process memory allocations.
..
sim: Align process memory allocations.
Align allocation requests in Process::allocateMem to page boundaries,
rather than assume that they already are. This frees the caller from
having to know what boundary to align things to. The older version would
make the caller more aware of the extent of the allocation in theory,
but in reality the caller would just blindly perform the alignment like
this function is anyway.
Change-Id: I897714d4481d961255a9e44ae080135e507be199
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50757
Reviewed-by: Matthew Poremba
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/sim/process.cc
M src/sim/process.hh
2 files changed, 42 insertions(+), 5 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Matthew Poremba: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/sim/process.cc b/src/sim/process.cc
index 71bb494..3a631a5 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -316,6 +316,10 @@
void
Process::allocateMem(Addr vaddr, int64_t size, bool clobber)
{
+const auto page_size = pTable->pageSize();
+
+const Addr page_addr = roundDown(vaddr, page_size);
+
// Check if the page has been mapped by other cores if not to clobber.
// When running multithreaded programs in SE-mode with DerivO3CPU
model,
// there are cases where two or more cores have page faults on the same
@@ -324,16 +328,17 @@
// a physical page frame to map with the virtual page. Other cores can
// return if the page has been mapped and `!clobber`.
if (!clobber) {
-const EmulationPageTable::Entry *pte = pTable->lookup(vaddr);
+const EmulationPageTable::Entry *pte = pTable->lookup(page_addr);
if (pte) {
warn("Process::allocateMem: addr %#x already mapped\n", vaddr);
return;
}
}
-int npages = divCeil(size, pTable->pageSize());
-Addr paddr = seWorkload->allocPhysPages(npages);
-pTable->map(vaddr, paddr, size,
+const int npages = divCeil(size, page_size);
+const Addr paddr = seWorkload->allocPhysPages(npages);
+const Addr pages_size = npages * page_size;
+pTable->map(page_addr, paddr, pages_size,
clobber ? EmulationPageTable::Clobber :
EmulationPageTable::MappingFlags(0));
}
diff --git a/src/sim/process.hh b/src/sim/process.hh
index 880b34b..cece212 100644
--- a/src/sim/process.hh
+++ b/src/sim/process.hh
@@ -108,7 +108,18 @@
Addr getStartPC();
loader::ObjectFile *getInterpreter();
-void allocateMem(Addr vaddr, int64_t size, bool clobber = false);
+// This function allocates physical memory as backing store, and then
maps
+// it into the virtual address space of the process. The range of
virtual
+// addresses being configured starts at the address "vaddr" and is of
size
+// "size" bytes. If some part of this range of virtual addresses is
already
+// configured, this function will error out unless "clobber" is set. If
+// clobber is set, then those existing mappings will be replaced.
+//
+// If the beginning or end of the virtual address range does not
perfectly
+// align to page boundaries, it will be expanded in either direction
until
+// it does. This function will therefore set up *at least* the range
+// requested, and may configure more if necessary.
+void allocateMem(Addr vaddr, int64_t size, bool clobber=false);
/// Attempt to fix up a fault at vaddr by allocating a page on the
stack.
/// @return Whether the fault has been fixed.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50757
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I897714d4481d961255a9e44ae080135e507be199
Gerrit-Change-Number: 50757
Gerrit-PatchSet: 8
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: WIP: ARM: Set up virtio console ports
Alistair Delva has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/51427 ) Change subject: WIP: ARM: Set up virtio console ports .. WIP: ARM: Set up virtio console ports Change-Id: Ia421a6e26250957af8ed77b466d53ccd4186aef3 --- M configs/example/arm/starter_fs.py 1 file changed, 47 insertions(+), 2 deletions(-) diff --git a/configs/example/arm/starter_fs.py b/configs/example/arm/starter_fs.py index 55f4f2a..3432e3b 100644 --- a/configs/example/arm/starter_fs.py +++ b/configs/example/arm/starter_fs.py @@ -116,6 +116,42 @@ for disk in args.disk_image: device = PciVirtIO(vio=VirtIOBlock(image=create_cow_image(disk))) pci_devices.append(device) + +# Kernel messages (kmsg) - hvc0 +device = PciVirtIO(vio=VirtIOConsole(device=Terminal(number=0, + name="kernel.log"))) +pci_devices.append(device) + +# Boot console - hvc1 (not used currently; goes via ttyAMA0 instead) +device = PciVirtIO(vio=VirtIOConsole(device=Terminal(number=1, + outfile="none"))) +pci_devices.append(device) + +# Android logcat - hvc2 +device = PciVirtIO(vio=VirtIOConsole(device=Terminal(number=2, + name="logcat"))) +pci_devices.append(device) + +# Keymint - hvc3 (not used currently) +device = PciVirtIO(vio=VirtIOConsole(device=Terminal(number=3, + outfile="none"))) +pci_devices.append(device) + +# Gatekeeper - hvc4 (not used currently) +device = PciVirtIO(vio=VirtIOConsole(device=Terminal(number=4, + outfile="none"))) +pci_devices.append(device) + +# Bluetooth - hvc5 (not used currently) +device = PciVirtIO(vio=VirtIOConsole(device=Terminal(number=5, + outfile="none"))) +pci_devices.append(device) + +# GNSS - hvc6 (not used currently) +device = PciVirtIO(vio=VirtIOConsole(device=Terminal(number=6, + outfile="none"))) +pci_devices.append(device) + system.pci_devices = pci_devices # Attach the PCI devices to the system. The helper method in the @@ -156,8 +192,6 @@ # Linux boot command flags kernel_cmd = [ -# Tell Linux to use the simulated serial port as a console -"console=ttyAMA0", # Hard-code timi "lpj=19988480", # Disable address space randomisation to get a consistent @@ -165,6 +199,8 @@ "norandmaps", # Tell Linux about the amount of physical memory present. "mem=%s" % args.mem_size, +# Tell Linux to use the virtio console port as a console +"console=hvc0", # Reboot immediately on panic "panic=-1", # Earlycon debug support -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51427 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ia421a6e26250957af8ed77b466d53ccd4186aef3 Gerrit-Change-Number: 51427 Gerrit-PatchSet: 1 Gerrit-Owner: Alistair Delva Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Jenkins' server moved; https://jenkins.gem5.org now live
Dear all, Our gem5 Jenkins' server has finally found a permanent home at the University of Wisconsin. Prior to this we were hosting here at UC Davis, but this came with restrictions on what we could expose to the wider world (i.e., no website). As such, the https://jenkins.gem5.org/ web portal is now live. You can now jump in and see the status of the gem5 tests and other jobs we run. Emails to the gem5 dev mailing list will continue to be sent if the compiler, nightly, or weekly tests fail. A special thank you to those at the University of Wisconsin for helping us set up this service. Kind regards, Bobby -- Dr. Bobby R. Bruce Room 3050, Kemper Hall, UC Davis Davis, CA, 95616 web: https://www.bobbybruce.net ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: util: Make gerrit bot respect reviewer removal
Hoa Nguyen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/50187 )
Change subject: util: Make gerrit bot respect reviewer removal
..
util: Make gerrit bot respect reviewer removal
Currently, if a maintainer is removed from a change, the maintainer
will be added again. This change prevents the bot from adding the
removed maintainer again.
The bot will query all updates related to reviewer addition/removal
for each new change. If a reviewer has ever been added/removed
from a change, that reviewer won't be added to that change again.
Change-Id: Ifaab5ebd7ebf3e6453b2551d3e37c1b9e214c906
Signed-off-by: Hoa Nguyen
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50187
Reviewed-by: Jason Lowe-Power
Tested-by: kokoro
Maintainer: Bobby R. Bruce
---
M util/gerrit-bot/bot.py
M util/gerrit-bot/util.py
2 files changed, 36 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/util/gerrit-bot/bot.py b/util/gerrit-bot/bot.py
index 709279c..6f6b018 100755
--- a/util/gerrit-bot/bot.py
+++ b/util/gerrit-bot/bot.py
@@ -170,9 +170,10 @@
def __query_new_changes(self, query_age):
query = (f"projects:{self.config.projects_prefix} "
f"status:open -is:wip -age:{query_age}")
-response = self.gerrit_api.query_changes(query,
- self.config.query_limit,
- "CURRENT_REVISION")
+response = self.gerrit_api.query_changes(
+query, self.config.query_limit,
+["CURRENT_REVISION", "REVIEWER_UPDATES", "DETAILED_ACCOUNTS"]
+)
if response.status_code >= 300:
print("Error: Couldn't query new Gerrit changes")
diff --git a/util/gerrit-bot/util.py b/util/gerrit-bot/util.py
index d836690..1d00372 100644
--- a/util/gerrit-bot/util.py
+++ b/util/gerrit-bot/util.py
@@ -60,6 +60,14 @@
tags, message = parse_commit_subject(change["subject"])
change_id = change["id"]
maintainer_emails = set()
+
+# There are cases that a reviewer being removed from the reviewer list
+# by another reviewer. We want to respect this removal. To do this,
+# we can avoid adding reviewers that have been added/removed to the
+# reviewer list.
+avoid_emails = set()
+for update in change["reviewer_updates"]:
+avoid_emails.add(update["reviewer"]["email"])
for tag in tags:
try:
for name, email in maintainers[tag].maintainers:
@@ -68,6 +76,8 @@
print((f"warning: `change-{change_id}` has an unknown tag: "
f"`{tag}`"))
for email in maintainer_emails:
+if email in avoid_emails:
+continue
try:
account_id = maintainers_account_ids[email]
gerrit_api.add_reviewer(change_id, account_id)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50187
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifaab5ebd7ebf3e6453b2551d3e37c1b9e214c906
Gerrit-Change-Number: 50187
Gerrit-PatchSet: 4
Gerrit-Owner: Hoa Nguyen
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Hoa Nguyen
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-CC: Jason Lowe-Power
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Use ArmRelease in MMU and TableWalker
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51408 )
Change subject: arch-arm: Use ArmRelease in MMU and TableWalker
..
arch-arm: Use ArmRelease in MMU and TableWalker
Change-Id: I210c73e0e66390f702dad6e7d737c8271b119091
Signed-off-by: Giacomo Travaglini
---
M src/arch/arm/mmu.cc
M src/arch/arm/mmu.hh
M src/arch/arm/ArmMMU.py
M src/arch/arm/table_walker.cc
M src/arch/arm/table_walker.hh
5 files changed, 42 insertions(+), 24 deletions(-)
diff --git a/src/arch/arm/ArmMMU.py b/src/arch/arm/ArmMMU.py
index d32cbff..3a6b921 100644
--- a/src/arch/arm/ArmMMU.py
+++ b/src/arch/arm/ArmMMU.py
@@ -35,6 +35,7 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+from m5.objects.ArmISA import ArmDefaultSERelease
from m5.objects.ArmTLB import ArmTLB, ArmStage2TLB
from m5.objects.BaseMMU import BaseMMU
from m5.objects.ClockedObject import ClockedObject
@@ -89,6 +90,9 @@
sys = Param.System(Parent.any, "system object parameter")
+release_se = Param.ArmRelease(ArmDefaultSERelease(),
+"Set of features/extensions to use in SE mode")
+
@classmethod
def walkerPorts(cls):
return ["mmu.itb_walker.port", "mmu.dtb_walker.port",
diff --git a/src/arch/arm/mmu.cc b/src/arch/arm/mmu.cc
index 52606b0..278a113 100644
--- a/src/arch/arm/mmu.cc
+++ b/src/arch/arm/mmu.cc
@@ -66,21 +66,22 @@
miscRegContext(0),
s1State(this, false), s2State(this, true),
_attr(0),
+_release(nullptr),
stats(this)
{
// Cache system-level properties
if (FullSystem) {
ArmSystem *arm_sys = dynamic_cast(p.sys);
assert(arm_sys);
-haveLPAE = arm_sys->has(ArmExtension::LPAE);
-haveVirtualization = arm_sys->has(ArmExtension::VIRTUALIZATION);
haveLargeAsid64 = arm_sys->haveLargeAsid64();
physAddrRange = arm_sys->physAddrRange();
+
+_release = arm_sys->releaseFS();
} else {
-haveLPAE = false;
-haveVirtualization = false;
haveLargeAsid64 = false;
physAddrRange = 48;
+
+_release = p.release_se;
}
m5opRange = p.sys->m5opRange();
@@ -1238,7 +1239,7 @@
scr = tc->readMiscReg(MISCREG_SCR_EL3);
isPriv = aarch64EL != EL0;
-if (mmu->haveVirtualization) {
+if (mmu->release()->has(ArmExtension::VIRTUALIZATION)) {
vmid = getVMID(tc);
isHyp = aarch64EL == EL2;
isHyp |= tran_type & HypMode;
@@ -1301,7 +1302,7 @@
!isSecure));
hcr = tc->readMiscReg(MISCREG_HCR);
-if (mmu->haveVirtualization) {
+if (mmu->release()->has(ArmExtension::VIRTUALIZATION)) {
vmid = bits(tc->readMiscReg(MISCREG_VTTBR), 55, 48);
isHyp = cpsr.mode == MODE_HYP;
isHyp |= tran_type & HypMode;
diff --git a/src/arch/arm/mmu.hh b/src/arch/arm/mmu.hh
index b80968b..7947373 100644
--- a/src/arch/arm/mmu.hh
+++ b/src/arch/arm/mmu.hh
@@ -327,6 +327,8 @@
_attr = attr;
}
+const ArmRelease* release() const { return _release; }
+
/**
* Determine the EL to use for the purpose of a translation given
* a specific translation type. If the translation type doesn't
@@ -417,8 +419,7 @@
uint64_t _attr; // Memory attributes for last accessed TLB entry
// Cached copies of system-level properties
-bool haveLPAE;
-bool haveVirtualization;
+const ArmRelease *_release;
bool haveLargeAsid64;
uint8_t physAddrRange;
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index ba1b4a4..41cdeba 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -65,6 +65,7 @@
isStage2(p.is_stage2), tlb(NULL),
currState(NULL), pending(false),
numSquashable(p.num_squash_per_cycle),
+ release(nullptr),
stats(this),
pendingReqs(0),
pendingChangeTick(curTick()),
@@ -84,13 +85,9 @@
if (FullSystem) {
ArmSystem *arm_sys = dynamic_cast(p.sys);
assert(arm_sys);
-haveSecurity = arm_sys->has(ArmExtension::SECURITY);
-_haveLPAE = arm_sys->has(ArmExtension::LPAE);
-_haveVirtualization = arm_sys->has(ArmExtension::VIRTUALIZATION);
_physAddrRange = arm_sys->physAddrRange();
_haveLargeAsid64 = arm_sys->haveLargeAsid64();
} else {
-haveSecurity = _haveLPAE = _haveVirtualization = false;
_haveLargeAsid64 = false;
_physAddrRange = 48;
}
@@ -117,6 +114,13 @@
return ClockedObject::getPort(if_name, idx);
}
+void
+TableWalker::setMmu(MMU *_mmu)
+{
+mmu = _mmu;
+release = mmu->release();
+}
+
TableWalker::WalkerState::WalkerState() :
tc(nullptr), aarch64(false), el(EL0), physAddrRange(0), req(nullptr),
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: HTMSequencer stats initialized twice
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/51407 )
Change subject: mem-ruby: HTMSequencer stats initialized twice
..
mem-ruby: HTMSequencer stats initialized twice
HTMSequencer stats are already initialized in the constructor
This is a bug from:
[1]: https://gem5-review.googlesource.com/c/public/gem5/+/36478
Change-Id: Id7d9b11f45035a46af32584ed86470c65d2a80b6
Signed-off-by: Giacomo Travaglini
---
M src/mem/ruby/system/HTMSequencer.cc
M src/mem/ruby/system/HTMSequencer.hh
2 files changed, 16 insertions(+), 35 deletions(-)
diff --git a/src/mem/ruby/system/HTMSequencer.cc
b/src/mem/ruby/system/HTMSequencer.cc
index 5157842..98f6d35 100644
--- a/src/mem/ruby/system/HTMSequencer.cc
+++ b/src/mem/ruby/system/HTMSequencer.cc
@@ -210,40 +210,6 @@
}
void
-HTMSequencer::regStats()
-{
-// hardware transactional memory
-m_htm_transaction_cycles
-.init(10)
-.name(name() + ".htm_transaction_cycles")
-.desc("number of cycles spent in an outer transaction")
-.flags(statistics::pdf | statistics::dist | statistics::nozero |
-statistics::nonan)
-;
-m_htm_transaction_instructions
-.init(10)
-.name(name() + ".htm_transaction_instructions")
-.desc("number of instructions spent in an outer transaction")
-.flags(statistics::pdf | statistics::dist | statistics::nozero |
-statistics::nonan)
-;
-auto num_causes = static_cast(HtmFailureFaultCause::NUM_CAUSES);
-m_htm_transaction_abort_cause
-.init(num_causes)
-.name(name() + ".htm_transaction_abort_cause")
-.desc("cause of htm transaction abort")
-.flags(statistics::total | statistics::pdf | statistics::dist |
-statistics::nozero)
-;
-
-for (unsigned cause_idx = 0; cause_idx < num_causes; ++cause_idx) {
-m_htm_transaction_abort_cause.subname(
-cause_idx,
-htmFailureToStr(HtmFailureFaultCause(cause_idx)));
-}
-}
-
-void
HTMSequencer::rubyHtmCallback(PacketPtr pkt,
const HtmFailedInCacheReason htm_return_code)
{
diff --git a/src/mem/ruby/system/HTMSequencer.hh
b/src/mem/ruby/system/HTMSequencer.hh
index 2f19f39..3b39331 100644
--- a/src/mem/ruby/system/HTMSequencer.hh
+++ b/src/mem/ruby/system/HTMSequencer.hh
@@ -68,7 +68,6 @@
bool empty() const override;
void print(std::ostream& out) const override;
-void regStats() override;
void wakeup() override;
private:
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id7d9b11f45035a46af32584ed86470c65d2a80b6
Gerrit-Change-Number: 51407
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: Naming cleanup for LSQRequest and Request
Tom Rollet has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/51067 )
Change subject: cpu-o3: Naming cleanup for LSQRequest and Request
..
cpu-o3: Naming cleanup for LSQRequest and Request
'LSQRequest' are now referred as 'request'
'Request' are now referred as 'req'
It makes the code easier to read.
Also it makes the naming of Request consistent with the cache.
Change-Id: I8ba75b75bd8408e411300d522cc2c8582c334cf5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51067
Tested-by: kokoro
Reviewed-by: Bobby R. Bruce
Reviewed-by: Gabe Black
Maintainer: Bobby R. Bruce
Maintainer: Gabe Black
---
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/lsq.cc
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_unit.cc
M src/cpu/o3/lsq_unit.hh
5 files changed, 240 insertions(+), 222 deletions(-)
Approvals:
Gabe Black: Looks good to me, but someone else must approve; Looks good
to me, approved
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index f26ea22..45d7b12 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -400,7 +400,7 @@
* Saved memory request (needed when the DTB address translation is
* delayed due to a hw page table walk).
*/
-LSQ::LSQRequest *savedReq;
+LSQ::LSQRequest *savedRequest;
/// Checker //
// Need a copy of main request pointer to verify on writes.
diff --git a/src/cpu/o3/lsq.cc b/src/cpu/o3/lsq.cc
index 61823df..b9f3e89 100644
--- a/src/cpu/o3/lsq.cc
+++ b/src/cpu/o3/lsq.cc
@@ -773,7 +773,7 @@
ThreadID tid = cpu->contextToThread(inst->contextId());
auto cacheLineSize = cpu->cacheLineSize();
bool needs_burst = transferNeedsBurst(addr, size, cacheLineSize);
-LSQRequest* req = nullptr;
+LSQRequest* request = nullptr;
// Atomic requests that access data across cache line boundary are
// currently not allowed since the cache does not guarantee
corresponding
@@ -786,47 +786,47 @@
const bool htm_cmd = isLoad && (flags & Request::HTM_CMD);
if (inst->translationStarted()) {
-req = inst->savedReq;
-assert(req);
+request = inst->savedRequest;
+assert(request);
} else {
if (htm_cmd) {
assert(addr == 0x0lu);
assert(size == 8);
-req = new HtmCmdRequest([tid], inst, flags);
+request = new HtmCmdRequest([tid], inst, flags);
} else if (needs_burst) {
-req = new SplitDataRequest([tid], inst, isLoad, addr,
+request = new SplitDataRequest([tid], inst, isLoad,
addr,
size, flags, data, res);
} else {
-req = new SingleDataRequest([tid], inst, isLoad, addr,
+request = new SingleDataRequest([tid], inst, isLoad,
addr,
size, flags, data, res, std::move(amo_op));
}
-assert(req);
-req->_byteEnable = byte_enable;
+assert(request);
+request->_byteEnable = byte_enable;
inst->setRequest();
-req->taskId(cpu->taskId());
+request->taskId(cpu->taskId());
// There might be fault from a previous execution attempt if this
is
// a strictly ordered load
inst->getFault() = NoFault;
-req->initiateTranslation();
+request->initiateTranslation();
}
/* This is the place were instructions get the effAddr. */
-if (req->isTranslationComplete()) {
-if (req->isMemAccessRequired()) {
-inst->effAddr = req->getVaddr();
+if (request->isTranslationComplete()) {
+if (request->isMemAccessRequired()) {
+inst->effAddr = request->getVaddr();
inst->effSize = size;
inst->effAddrValid(true);
if (cpu->checker) {
-inst->reqToVerify =
std::make_shared(*req->request());
+inst->reqToVerify =
std::make_shared(*request->req());
}
Fault fault;
if (isLoad)
-fault = read(req, inst->lqIdx);
+fault = read(request, inst->lqIdx);
else
-fault = write(req, data, inst->sqIdx);
+fault = write(request, data, inst->sqIdx);
// inst->getFault() may have the first-fault of a
// multi-access split request at this point.
// Overwrite that only if we got another type of fault
@@ -848,7 +848,7 @@
}
void
-LSQ::SingleDataRequest::finish(const Fault , const RequestPtr ,
+LSQ::SingleDataRequest::finish(const Fault , const RequestPtr
,
gem5::ThreadContext* tc, BaseMMU::Mode mode)
{
_fault.push_back(fault);
@@ -859,15 +859,15 @@
if (_inst->isSquashed()) {
squashTranslation();
} else {
-
[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: remove LSQSenderState
Tom Rollet has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/50733 )
Change subject: cpu-o3: remove LSQSenderState
..
cpu-o3: remove LSQSenderState
The LSQSenderState that was attached to Request was not useful.
All the fields were either a duplicate of information in the
LSQRequest or totally unused.
The LSQRequest class now inherits from Packet::SenderState and is
attached to the Packet that are sent to memory. We do not need
anymore the indirection Packet->SenderState->LSQRequest.
This helps making the code clearer as it was sometimes hard to
follow the difference between what the LSQRequest and
LSQSenserState was doing
(ex: number of outstanding requests in the memory).
Change-Id: I5b21e007e6d183c6aa79c27c1787ca56dcbc3fb0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50733
Reviewed-by: Bobby R. Bruce
Maintainer: Bobby R. Bruce
Tested-by: kokoro
---
M src/cpu/o3/lsq.cc
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_unit.cc
M src/cpu/o3/lsq_unit.hh
4 files changed, 103 insertions(+), 217 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/o3/lsq.cc b/src/cpu/o3/lsq.cc
index babfa92..61823df 100644
--- a/src/cpu/o3/lsq.cc
+++ b/src/cpu/o3/lsq.cc
@@ -64,16 +64,6 @@
namespace o3
{
-LSQ::LSQSenderState::LSQSenderState(LSQRequest *request, bool is_load) :
-_request(request), isLoad(is_load), needWB(is_load)
-{}
-
-ContextID
-LSQ::LSQSenderState::contextId()
-{
-return inst->contextId();
-}
-
LSQ::DcachePort::DcachePort(LSQ *_lsq, CPU *_cpu) :
RequestPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq), cpu(_cpu)
{}
@@ -402,8 +392,8 @@
void
LSQ::completeDataAccess(PacketPtr pkt)
{
-auto senderState = dynamic_cast(pkt->senderState);
-thread[cpu->contextToThread(senderState->contextId())]
+LSQRequest *request = dynamic_cast(pkt->senderState);
+thread[cpu->contextToThread(request->contextId())]
.completeDataAccess(pkt);
}
@@ -414,10 +404,10 @@
DPRINTF(LSQ, "Got error packet back for address: %#X\n",
pkt->getAddr());
-auto senderState = dynamic_cast(pkt->senderState);
-panic_if(!senderState, "Got packet back with unknown sender state\n");
+LSQRequest *request = dynamic_cast(pkt->senderState);
+panic_if(!request, "Got packet back with unknown sender state\n");
-
thread[cpu->contextToThread(senderState->contextId())].recvTimingResp(pkt);
+thread[cpu->contextToThread(request->contextId())].recvTimingResp(pkt);
if (pkt->isInvalidate()) {
// This response also contains an invalidate; e.g. this can be the
case
@@ -439,7 +429,7 @@
}
}
// Update the LSQRequest state (this may delete the request)
-senderState->request()->packetReplied();
+request->packetReplied();
return true;
}
@@ -1041,14 +1031,15 @@
LSQ::LSQRequest::LSQRequest(
LSQUnit *port, const DynInstPtr& inst, bool isLoad) :
-_state(State::NotIssued), _senderState(nullptr),
+_state(State::NotIssued),
_port(*port), _inst(inst), _data(nullptr),
_res(nullptr), _addr(0), _size(0), _flags(0),
_numOutstandingPackets(0), _amo_op(nullptr)
{
flags.set(Flag::IsLoad, isLoad);
-flags.set(Flag::WbStore,
- _inst->isStoreConditional() || _inst->isAtomic());
+flags.set(Flag::WriteBackToRegister,
+ _inst->isStoreConditional() || _inst->isAtomic() ||
+ _inst->isLoad());
flags.set(Flag::IsAtomic, _inst->isAtomic());
install();
}
@@ -1057,7 +1048,7 @@
LSQUnit *port, const DynInstPtr& inst, bool isLoad,
const Addr& addr, const uint32_t& size, const Request::Flags&
flags_,
PacketDataPtr data, uint64_t* res, AtomicOpFunctorPtr amo_op)
-: _state(State::NotIssued), _senderState(nullptr),
+: _state(State::NotIssued),
numTranslatedFragments(0),
numInTranslationFragments(0),
_port(*port), _inst(inst), _data(data),
@@ -1067,8 +1058,9 @@
_amo_op(std::move(amo_op))
{
flags.set(Flag::IsLoad, isLoad);
-flags.set(Flag::WbStore,
- _inst->isStoreConditional() || _inst->isAtomic());
+flags.set(Flag::WriteBackToRegister,
+ _inst->isStoreConditional() || _inst->isAtomic() ||
+ _inst->isLoad());
flags.set(Flag::IsAtomic, _inst->isAtomic());
install();
}
@@ -1105,13 +1097,17 @@
{
assert(!isAnyOutstandingRequest());
_inst->savedReq = nullptr;
-if (_senderState)
-delete _senderState;
for (auto r: _packets)
delete r;
};
+ContextID
+LSQ::LSQRequest::contextId() const
+{
+return _inst->contextId();
+}
+
void
LSQ::LSQRequest::sendFragmentToTranslation(int i)
{
@@ -1124,9 +1120,7 @@
LSQ::SingleDataRequest::recvTimingResp(PacketPtr pkt)
{
assert(_numOutstandingPackets ==
[gem5-dev] Change in gem5/gem5[develop]: cpu-o3: remove useless 'using'-s
Tom Rollet has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/51347 )
Change subject: cpu-o3: remove useless 'using'-s
..
cpu-o3: remove useless 'using'-s
Change-Id: Ifa8ef516d0deabb4308bdf3c4b61b88ece149d0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51347
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/cpu/o3/lsq.hh
1 file changed, 13 insertions(+), 69 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index c909f54..798ceb9 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -562,34 +562,6 @@
class SingleDataRequest : public LSQRequest
{
- protected:
-/* Given that we are inside templates, children need explicit
- * declaration of the names in the parent class. */
-using Flag = LSQRequest::Flag;
-using State = LSQRequest::State;
-using LSQRequest::_addr;
-using LSQRequest::_fault;
-using LSQRequest::_flags;
-using LSQRequest::_size;
-using LSQRequest::_byteEnable;
-using LSQRequest::_reqs;
-using LSQRequest::_inst;
-using LSQRequest::_packets;
-using LSQRequest::_port;
-using LSQRequest::_res;
-using LSQRequest::_taskId;
-using LSQRequest::_state;
-using LSQRequest::flags;
-using LSQRequest::isLoad;
-using LSQRequest::isTranslationComplete;
-using LSQRequest::lsqUnit;
-using LSQRequest::req;
-using LSQRequest::sendFragmentToTranslation;
-using LSQRequest::setState;
-using LSQRequest::numInTranslationFragments;
-using LSQRequest::numTranslatedFragments;
-using LSQRequest::_numOutstandingPackets;
-using LSQRequest::_amo_op;
public:
SingleDataRequest(LSQUnit* port, const DynInstPtr& inst,
bool isLoad, const Addr& addr, const uint32_t& size,
@@ -616,19 +588,6 @@
// of encapsulating hardware transactional memory command requests
class HtmCmdRequest : public SingleDataRequest
{
- protected:
-/* Given that we are inside templates, children need explicit
- * declaration of the names in the parent class. */
-using Flag = LSQRequest::Flag;
-using State = LSQRequest::State;
-using LSQRequest::_addr;
-using LSQRequest::_size;
-using LSQRequest::_byteEnable;
-using LSQRequest::_reqs;
-using LSQRequest::_inst;
-using LSQRequest::_taskId;
-using LSQRequest::flags;
-using LSQRequest::setState;
public:
HtmCmdRequest(LSQUnit* port, const DynInstPtr& inst,
const Request::Flags& flags_);
@@ -642,34 +601,6 @@
class SplitDataRequest : public LSQRequest
{
protected:
-/* Given that we are inside templates, children need explicit
- * declaration of the names in the parent class. */
-using Flag = LSQRequest::Flag;
-using State = LSQRequest::State;
-using LSQRequest::_addr;
-using LSQRequest::_data;
-using LSQRequest::_fault;
-using LSQRequest::_flags;
-using LSQRequest::_inst;
-using LSQRequest::_packets;
-using LSQRequest::_port;
-using LSQRequest::_reqs;
-using LSQRequest::_res;
-using LSQRequest::_byteEnable;
-using LSQRequest::_size;
-using LSQRequest::_state;
-using LSQRequest::_taskId;
-using LSQRequest::flags;
-using LSQRequest::isLoad;
-using LSQRequest::isTranslationComplete;
-using LSQRequest::lsqUnit;
-using LSQRequest::numInTranslationFragments;
-using LSQRequest::numTranslatedFragments;
-using LSQRequest::req;
-using LSQRequest::sendFragmentToTranslation;
-using LSQRequest::setState;
-using LSQRequest::_numOutstandingPackets;
-
uint32_t numFragments;
uint32_t numReceivedPackets;
RequestPtr _mainReq;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/51347
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifa8ef516d0deabb4308bdf3c4b61b88ece149d0e
Gerrit-Change-Number: 51347
Gerrit-PatchSet: 2
Gerrit-Owner: Tom Rollet
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Tom Rollet
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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