[gem5-dev] Change in gem5/gem5[develop]: arch,sim-se: Update the PC before emulating a system call.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53983 )



Change subject: arch,sim-se: Update the PC before emulating a system call.
..

arch,sim-se: Update the PC before emulating a system call.

For most system calls, it doesn't matter if the PC is advanced to the
instruction after the system call instruction before or after the system
call itself is invoked, because the system call itself doesn't interact
with it.

For some system calls however, specifically "clone" and "execve",
advancing the PC *after* the system call complicates things, because it
means the system call needs to set the PC to something that will equal
the desired value only *after* it's advanced.

By setting the PC *before* the system call, the system call can set the
PC to whatever it needs to. This means the new cloned context doesn't
need to advance the PC because it's already advanced, and execve doesn't
need to set NPC, it can leave the PC set to the correct value from the
entry point set during Process initialization.

Change-Id: I830607c2e9adcc22e738178fd3663417512e2e56
---
M src/arch/x86/linux/se_workload.cc
M src/sim/faults.cc
M src/arch/arm/faults.cc
M src/sim/syscall_emul.hh
M src/arch/riscv/faults.cc
5 files changed, 35 insertions(+), 14 deletions(-)



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index e340d07..ba5bcc9 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -881,15 +881,15 @@
 return;
 }

-// As of now, there isn't a 32 bit thumb version of this instruction.
-assert(!machInst.bigThumb);
-tc->getSystemPtr()->workload->syscall(tc);
-
 // Advance the PC since that won't happen automatically.
 PCState pc = tc->pcState().as();
 assert(inst);
 inst->advancePC(pc);
 tc->pcState(pc);
+
+// As of now, there isn't a 32 bit thumb version of this instruction.
+assert(!machInst.bigThumb);
+tc->getSystemPtr()->workload->syscall(tc);
 }

 bool
diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 129e767..eea42fe 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -157,11 +157,12 @@
 if (isInterrupt() && bits(tc->readMiscReg(tvec), 1, 0) == 1)
 addr += 4 * _code;
 pc_state.set(addr);
+tc->pcState(pc_state);
 } else {
-invokeSE(tc, inst);
 inst->advancePC(pc_state);
+tc->pcState(pc_state);
+invokeSE(tc, inst);
 }
-tc->pcState(pc_state);
 }

 void
diff --git a/src/arch/x86/linux/se_workload.cc  
b/src/arch/x86/linux/se_workload.cc

index f5fa519..d280c7c 100644
--- a/src/arch/x86/linux/se_workload.cc
+++ b/src/arch/x86/linux/se_workload.cc
@@ -120,7 +120,7 @@
 Addr eip = pc.pc();
 const auto  = proc32->getVSyscallPage();
 if (eip >= vsyscall.base && eip < vsyscall.base + vsyscall.size) {
-pc.npc(vsyscall.base + vsyscall.vsysexitOffset);
+pc.set(vsyscall.base + vsyscall.vsysexitOffset);
 tc->pcState(pc);
 }
 syscallDescs32.get(rax)->doSyscall(tc);
diff --git a/src/sim/faults.cc b/src/sim/faults.cc
index 98778f2..115c0ed 100644
--- a/src/sim/faults.cc
+++ b/src/sim/faults.cc
@@ -71,11 +71,12 @@
 void
 SESyscallFault::invoke(ThreadContext *tc, const StaticInstPtr )
 {
-tc->getSystemPtr()->workload->syscall(tc);
 // Move the PC forward since that doesn't happen automatically.
 std::unique_ptr pc(tc->pcState().clone());
 inst->advancePC(*pc);
 tc->pcState(*pc);
+
+tc->getSystemPtr()->workload->syscall(tc);
 }

 void
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index a74aabf..546ae75 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1703,9 +1703,6 @@

 desc->returnInto(ctc, 0);

-std::unique_ptr cpc(tc->pcState().clone());
-cpc->advance();
-ctc->pcState(*cpc);
 ctc->activate();

 if (flags & OS::TGT_CLONE_VFORK) {
@@ -2267,9 +2264,6 @@
 new_p->init();
 new_p->initState();
 tc->activate();
-std::unique_ptr pc_state(tc->pcState().clone());
-pc_state->advance();
-tc->pcState(*pc_state);

 return SyscallReturn();
 }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I830607c2e9adcc22e738178fd3663417512e2e56
Gerrit-Change-Number: 53983
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] Re: Broken SST due to python changes

[Bobby Bruce via gem5-dev]

Hey gabe.

No idea if this is the _best_ solution to your problem, but my solution
would be to rebuild the image with this installed. Modify the
`util/dockerfiles/sst-11.1.0/Dockerfile` to the environment you want. Then
run `docker build -t  util/dockerfiles/sst-11.1.0` to build
an image with the name "".

Then you can execute `docker run -u $UID:$GID --volume $(pwd):$(pwd) -w
$(pwd) -it ` within the gem5 directory to spin up and enter
a container from the image you just built. I think you'll be able to do
what you want inside the container.

Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 3050,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Fri, Dec 10, 2021 at 7:24 PM Gabe Black  wrote:
>
> Dumb question: I'm trying to run gdb inside this container on the sst
thing. How do I do that? It's not installed in the container now, and I
can't (easily) figure out how to get it installed. I can tell docker to
install it, but then it seems to throw that away as soon as the command
ends.
>
> Gabe
>
> On Fri, Dec 10, 2021 at 5:09 PM Bobby Bruce  wrote:
>>
>> Thanks Gabe,
>>
>> This is very much appreciated. I'm going to create the release staging
once a couple more things get in. Feel free to push any patches related to
these bugs to the release staging branch.
>>
>> If there is an order of priority I'd say the bug affecting SST is of
higher importance than that affecting the Weeklies (as far as I can see the
latter is hard to trigger). That being said, we'll apply both to the new
release one way or another.
>>
>> --
>> Dr. Bobby R. Bruce
>> Room 3050,
>> Kemper Hall, UC Davis
>> Davis,
>> CA, 95616
>>
>> web: https://www.bobbybruce.net
>>
>>
>> On Fri, Dec 10, 2021 at 5:02 PM Gabe Black  wrote:
>>>
>>> Hi Bobby, not yet, I meant to look into this for the last couple days
but kept running out of time. I'm sitting down to work on it right now.
>>>
>>> Gabe
>>>
>>> On Fri, Dec 10, 2021 at 1:21 PM Bobby Bruce  wrote:

 Hey Gabe,

 Is there any update on this?

 Kind regards,
 Bobby
 --
 Dr. Bobby R. Bruce
 Room 3050,
 Kemper Hall, UC Davis
 Davis,
 CA, 95616

 web: https://www.bobbybruce.net


 On Wed, Dec 8, 2021 at 5:51 PM Hoa Nguyen via gem5-dev <
gem5-dev@gem5.org> wrote:
>
> Hi Gabe,
>
> I have more details about this. In this use case, SST initialized the
> Python environment before adding the "gem5 object". This gem5 object
> will add more Python stuff from gem5 to the environment.
>
> The function that does that is initPython()
>
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/ext/sst/gem5.cc#415
>
> The following commands will pull the docker image for SST testing
> purposes (note that host_gem5_root and guest_gem5_root must be
> specified),
>
> ```
> docker run -u $UID:$GID --volume
"${host_gem5_root}":"${guest_gem5_root}" -w \
>  "${guest_gem5_root}" --rm gcr.io/gem5-test/sst-env \
>  bash -c "\
> scons build/RISCV/libgem5_opt.so -j${nproc} --without-tcmalloc; \
> cd ext/sst; \
> make clean; make; \
> sst --add-lib-path=./ sst/example.py;
> ```
>
> We appreciate your help!
>
> Regards,
> Hoa Nguyen
>
> On 12/8/21, Jason Lowe-Power  wrote:
> > Hey Gabe,
> >
> > This change breaks the SST integration. In the SST integration
python is
> > initialized from the SST module, not from init.cc (this is because
SST has
> > their own python interpreter).
> >
> > We would appreciate some help in fixing this. Hoa and Giacomo can
give you
> > an example that's breaking to help you fix it, I believe.
> >
> > https://gem5-review.googlesource.com/c/public/gem5/+/49413
> >
> > There's strong interest in having the SST integration working in
this
> > current release. We've spent a lot of time figuring out all of the
> > intricacies and would appreciate any help you can provide in these
last few
> > days before the release!
> >
> > Thanks!
> >
> > Jason
> >
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[gem5-dev] Change in gem5/gem5[develop]: python: Add simulator instantiation checks

[Bobby Bruce (Gerrit) via gem5-dev]

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53923 )


Change subject: python: Add simulator instantiation checks
..

python: Add simulator instantiation checks

Check that m5.instantiate() has been called before m5.simulate() and
that m5.instantiate() is only called once.

Change-Id: Iced129cfd3d09564e2ef619eba829fd294c8a6ac
Signed-off-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53923
Reviewed-by: Giacomo Travaglini 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/python/m5/simulate.py
1 file changed, 32 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/m5/simulate.py b/src/python/m5/simulate.py
index b5b8c78..0e222cf 100644
--- a/src/python/m5/simulate.py
+++ b/src/python/m5/simulate.py
@@ -62,11 +62,19 @@

 _drain_manager = _m5.drain.DrainManager.instance()

-# The final hook to generate .ini files.  Called from the user script
-# once the config is built.
+_instantiated = False # Has m5.instantiate() been called?
+
+# The final call to instantiate the SimObject graph and initialize the
+# system.
 def instantiate(ckpt_dir=None):
+global _instantiated
 from m5 import options

+if _instantiated:
+fatal("m5.instantiate() called twice.")
+
+_instantiated = True
+
 root = objects.Root.getInstance()

 if not root:
@@ -148,6 +156,10 @@
 need_startup = True
 def simulate(*args, **kwargs):
 global need_startup
+global _instantiated
+
+if not _instantiated:
+fatal("m5.instantiate() must be called before m5.simulate().")

 if need_startup:
 root = objects.Root.getInstance()

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iced129cfd3d09564e2ef619eba829fd294c8a6ac
Gerrit-Change-Number: 53923
Gerrit-PatchSet: 2
Gerrit-Owner: Andreas Sandberg 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-vega: Implement V_LSHL_ADD_U32

[Bobby Bruce (Gerrit) via gem5-dev]

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53865 )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-vega: Implement V_LSHL_ADD_U32
..

arch-vega: Implement V_LSHL_ADD_U32

Change-Id: I986f82e8c6c02b0d62e55fbaed1c3f9e5b2b4a43
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53865
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
M src/arch/amdgpu/vega/decoder.cc
3 files changed, 96 insertions(+), 2 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/amdgpu/vega/decoder.cc  
b/src/arch/amdgpu/vega/decoder.cc

index cc24d96..54fcda9 100644
--- a/src/arch/amdgpu/vega/decoder.cc
+++ b/src/arch/amdgpu/vega/decoder.cc
@@ -6927,8 +6927,7 @@
 GPUStaticInst*
 Decoder::decode_OPU_VOP3__V_LSHL_ADD_U32(MachInst iFmt)
 {
-fatal("Trying to decode instruction without a class\n");
-return nullptr;
+return new Inst_VOP3__V_LSHL_ADD_U32(>iFmt_VOP3A);
 }

 GPUStaticInst*
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc  
b/src/arch/amdgpu/vega/insts/instructions.cc

index be3966d..d699a9a 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -32004,6 +32004,52 @@
 vcc.write();
 vdst.write();
 } // execute
+// --- Inst_VOP3__V_LSHL_ADD_U32 class methods ---
+
+Inst_VOP3__V_LSHL_ADD_U32::Inst_VOP3__V_LSHL_ADD_U32(InFmt_VOP3A *iFmt)
+: Inst_VOP3A(iFmt, "v_lshl_add_u32", false)
+{
+setFlag(ALU);
+} // Inst_VOP3__V_LSHL_ADD_U32
+
+Inst_VOP3__V_LSHL_ADD_U32::~Inst_VOP3__V_LSHL_ADD_U32()
+{
+} // ~Inst_VOP3__V_LSHL_ADD_U32
+
+// --- description from .arch file ---
+// D.u = (S0.u << S1.u[4:0]) + S2.u.
+void
+Inst_VOP3__V_LSHL_ADD_U32::execute(GPUDynInstPtr gpuDynInst)
+{
+Wavefront *wf = gpuDynInst->wavefront();
+ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+src0.readSrc();
+src1.readSrc();
+src2.readSrc();
+
+/**
+ * input modifiers are supported by FP operations only
+ */
+assert(!(instData.ABS & 0x1));
+assert(!(instData.ABS & 0x2));
+assert(!(instData.ABS & 0x4));
+assert(!(extData.NEG & 0x1));
+assert(!(extData.NEG & 0x2));
+assert(!(extData.NEG & 0x4));
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (wf->execMask(lane)) {
+vdst[lane] = (src0[lane] << bits(src1[lane], 4, 0))
+   + src2[lane];
+}
+}
+
+vdst.write();
+} // execute
 // --- Inst_VOP3__V_LSHL_OR_B32 class methods ---

 Inst_VOP3__V_LSHL_OR_B32::Inst_VOP3__V_LSHL_OR_B32(InFmt_VOP3A *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh  
b/src/arch/amdgpu/vega/insts/instructions.hh

index 0c30ca4..e3e390b 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -29496,6 +29496,42 @@
 void execute(GPUDynInstPtr) override;
 }; // Inst_VOP3__V_MAD_I64_I32

+class Inst_VOP3__V_LSHL_ADD_U32 : public Inst_VOP3A
+{
+  public:
+Inst_VOP3__V_LSHL_ADD_U32(InFmt_VOP3A*);
+~Inst_VOP3__V_LSHL_ADD_U32();
+
+int
+getNumOperands() override
+{
+return numDstRegOperands() + numSrcRegOperands();
+} // getNumOperands
+
+int numDstRegOperands() override { return 1; }
+int numSrcRegOperands() override { return 3; }
+
+int
+getOperandSize(int opIdx) override
+{
+switch (opIdx) {
+  case 0: //src_0
+return 4;
+  case 1: //src_1
+return 4;
+  case 2: //src_2
+return 4;
+  case 3: //vdst
+return 4;
+  default:
+fatal("op idx %i out of bounds\n", opIdx);
+return -1;
+}
+} // getOperandSize
+
+void execute(GPUDynInstPtr) override;
+}; // Inst_VOP3__V_LSHL_ADD_U32
+
 class Inst_VOP3__V_LSHL_OR_B32 : public Inst_VOP3A
 {
   public:

--
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Gerrit-Branch: develop

[gem5-dev] Change in gem5/gem5[develop]: arch-vega: Implement V_OR3_B32

[Bobby Bruce (Gerrit) via gem5-dev]

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53863 )


Change subject: arch-vega: Implement V_OR3_B32
..

arch-vega: Implement V_OR3_B32

Change-Id: Id6c074033b08058b739e056f06b40ee5735f8f00
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53863
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
M src/arch/amdgpu/vega/decoder.cc
3 files changed, 96 insertions(+), 2 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/amdgpu/vega/decoder.cc  
b/src/arch/amdgpu/vega/decoder.cc

index 6b478d7..814f7de 100644
--- a/src/arch/amdgpu/vega/decoder.cc
+++ b/src/arch/amdgpu/vega/decoder.cc
@@ -6962,8 +6962,7 @@
 GPUStaticInst*
 Decoder::decode_OPU_VOP3__V_OR3_B32(MachInst iFmt)
 {
-fatal("Trying to decode instruction without a class\n");
-return nullptr;
+return new Inst_VOP3__V_OR_B32(>iFmt_VOP3A);
 }

 GPUStaticInst*
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc  
b/src/arch/amdgpu/vega/insts/instructions.cc

index 1e07f0b..d709bb1 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -26176,6 +26176,52 @@

 vdst.write();
 } // execute
+// --- Inst_VOP3__V_OR3_B32 class methods ---
+
+Inst_VOP3__V_OR3_B32::Inst_VOP3__V_OR3_B32(InFmt_VOP3A *iFmt)
+: Inst_VOP3A(iFmt, "v_or3_b32", false)
+{
+setFlag(ALU);
+} // Inst_VOP3__V_OR3_B32
+
+Inst_VOP3__V_OR3_B32::~Inst_VOP3__V_OR3_B32()
+{
+} // ~Inst_VOP3__V_OR3_B32
+
+// --- description from .arch file ---
+// D.u = S0.u | S1.u | S2.u.
+// Input and output modifiers not supported.
+void
+Inst_VOP3__V_OR3_B32::execute(GPUDynInstPtr gpuDynInst)
+{
+Wavefront *wf = gpuDynInst->wavefront();
+ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+src0.readSrc();
+src1.readSrc();
+src2.readSrc();
+
+/**
+ * input modifiers are supported by FP operations only
+ */
+assert(!(instData.ABS & 0x1));
+assert(!(instData.ABS & 0x2));
+assert(!(instData.ABS & 0x4));
+assert(!(extData.NEG & 0x1));
+assert(!(extData.NEG & 0x2));
+assert(!(extData.NEG & 0x4));
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (wf->execMask(lane)) {
+vdst[lane] = src0[lane] | src1[lane] | src2[lane];
+}
+}
+
+vdst.write();
+} // execute
 // --- Inst_VOP3__V_XOR_B32 class methods ---

 Inst_VOP3__V_XOR_B32::Inst_VOP3__V_XOR_B32(InFmt_VOP3A *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh  
b/src/arch/amdgpu/vega/insts/instructions.hh

index 5a5c91f..453327f 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -24674,6 +24674,42 @@
 void execute(GPUDynInstPtr) override;
 }; // Inst_VOP3__V_OR_B32

+class Inst_VOP3__V_OR3_B32 : public Inst_VOP3A
+{
+  public:
+Inst_VOP3__V_OR3_B32(InFmt_VOP3A*);
+~Inst_VOP3__V_OR3_B32();
+
+int
+getNumOperands() override
+{
+return numDstRegOperands() + numSrcRegOperands();
+} // getNumOperands
+
+int numDstRegOperands() override { return 1; }
+int numSrcRegOperands() override { return 3; }
+
+int
+getOperandSize(int opIdx) override
+{
+switch (opIdx) {
+  case 0: //src_0
+return 4;
+  case 1: //src_1
+return 4;
+  case 2: //src_2
+return 4;
+  case 3: //vdst
+return 4;
+  default:
+fatal("op idx %i out of bounds\n", opIdx);
+return -1;
+}
+} // getOperandSize
+
+void execute(GPUDynInstPtr) override;
+}; // Inst_VOP3__V_OR_B32
+
 class Inst_VOP3__V_XOR_B32 : public Inst_VOP3A
 {
   public:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id6c074033b08058b739e056f06b40ee5735f8f00
Gerrit-Change-Number: 53863
Gerrit-PatchSet: 4
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: kokoro 

[gem5-dev] Change in gem5/gem5[develop]: arch-vega: Implement V_LSHL_OR_B32

[Bobby Bruce (Gerrit) via gem5-dev]

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53864 )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-vega: Implement V_LSHL_OR_B32
..

arch-vega: Implement V_LSHL_OR_B32

Change-Id: I237410e05df9a96323a6ceb7d09ae2a2a8608f16
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53864
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
M src/arch/amdgpu/vega/decoder.cc
3 files changed, 96 insertions(+), 2 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/amdgpu/vega/decoder.cc  
b/src/arch/amdgpu/vega/decoder.cc

index 814f7de..cc24d96 100644
--- a/src/arch/amdgpu/vega/decoder.cc
+++ b/src/arch/amdgpu/vega/decoder.cc
@@ -6948,8 +6948,7 @@
 GPUStaticInst*
 Decoder::decode_OPU_VOP3__V_LSHL_OR_B32(MachInst iFmt)
 {
-fatal("Trying to decode instruction without a class\n");
-return nullptr;
+return new Inst_VOP3__V_LSHL_OR_B32(>iFmt_VOP3A);
 }

 GPUStaticInst*
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc  
b/src/arch/amdgpu/vega/insts/instructions.cc

index d709bb1..be3966d 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -32004,6 +32004,52 @@
 vcc.write();
 vdst.write();
 } // execute
+// --- Inst_VOP3__V_LSHL_OR_B32 class methods ---
+
+Inst_VOP3__V_LSHL_OR_B32::Inst_VOP3__V_LSHL_OR_B32(InFmt_VOP3A *iFmt)
+: Inst_VOP3A(iFmt, "v_lshl_or_b32", false)
+{
+setFlag(ALU);
+} // Inst_VOP3__V_LSHL_OR_B32
+
+Inst_VOP3__V_LSHL_OR_B32::~Inst_VOP3__V_LSHL_OR_B32()
+{
+} // ~Inst_VOP3__V_LSHL_OR_B32
+
+// --- description from .arch file ---
+// D.u = (S0.u << S1.u[4:0]) | S2.u.
+void
+Inst_VOP3__V_LSHL_OR_B32::execute(GPUDynInstPtr gpuDynInst)
+{
+Wavefront *wf = gpuDynInst->wavefront();
+ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+src0.readSrc();
+src1.readSrc();
+src2.readSrc();
+
+/**
+ * input modifiers are supported by FP operations only
+ */
+assert(!(instData.ABS & 0x1));
+assert(!(instData.ABS & 0x2));
+assert(!(instData.ABS & 0x4));
+assert(!(extData.NEG & 0x1));
+assert(!(extData.NEG & 0x2));
+assert(!(extData.NEG & 0x4));
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (wf->execMask(lane)) {
+vdst[lane] = (src0[lane] << bits(src1[lane], 4, 0))
+   | src2[lane];
+}
+}
+
+vdst.write();
+} // execute
 // --- Inst_VOP3__V_MAD_F16 class methods ---

 Inst_VOP3__V_MAD_F16::Inst_VOP3__V_MAD_F16(InFmt_VOP3A *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh  
b/src/arch/amdgpu/vega/insts/instructions.hh

index 453327f..0c30ca4 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -29496,6 +29496,42 @@
 void execute(GPUDynInstPtr) override;
 }; // Inst_VOP3__V_MAD_I64_I32

+class Inst_VOP3__V_LSHL_OR_B32 : public Inst_VOP3A
+{
+  public:
+Inst_VOP3__V_LSHL_OR_B32(InFmt_VOP3A*);
+~Inst_VOP3__V_LSHL_OR_B32();
+
+int
+getNumOperands() override
+{
+return numDstRegOperands() + numSrcRegOperands();
+} // getNumOperands
+
+int numDstRegOperands() override { return 1; }
+int numSrcRegOperands() override { return 3; }
+
+int
+getOperandSize(int opIdx) override
+{
+switch (opIdx) {
+  case 0: //src_0
+return 4;
+  case 1: //src_1
+return 4;
+  case 2: //src_2
+return 4;
+  case 3: //vdst
+return 4;
+  default:
+fatal("op idx %i out of bounds\n", opIdx);
+return -1;
+}
+} // getOperandSize
+
+void execute(GPUDynInstPtr) override;
+}; // Inst_VOP3__V_LSHL_OR_B32
+
 class Inst_VOP3__V_MAD_F16 : public Inst_VOP3A
 {
   public:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: 

[gem5-dev] Change in gem5/gem5[develop]: arch-vega: Impelemnt V_ADD_LSHL_U32

[Bobby Bruce (Gerrit) via gem5-dev]

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53866 )


 (

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-vega: Impelemnt V_ADD_LSHL_U32
..

arch-vega: Impelemnt V_ADD_LSHL_U32

Change-Id: Ia4e465ef2534fe28dc846f728b2e1da3dfe4f7d6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53866
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
M src/arch/amdgpu/vega/decoder.cc
3 files changed, 96 insertions(+), 2 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/amdgpu/vega/decoder.cc  
b/src/arch/amdgpu/vega/decoder.cc

index 54fcda9..e616a7f 100644
--- a/src/arch/amdgpu/vega/decoder.cc
+++ b/src/arch/amdgpu/vega/decoder.cc
@@ -6933,8 +6933,7 @@
 GPUStaticInst*
 Decoder::decode_OPU_VOP3__V_ADD_LSHL_U32(MachInst iFmt)
 {
-fatal("Trying to decode instruction without a class\n");
-return nullptr;
+return new Inst_VOP3__V_ADD_LSHL_U32(>iFmt_VOP3A);
 }

 GPUStaticInst*
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc  
b/src/arch/amdgpu/vega/insts/instructions.cc

index d699a9a..114859c 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -32050,6 +32050,52 @@

 vdst.write();
 } // execute
+// --- Inst_VOP3__V_ADD_LSHL_U32 class methods ---
+
+Inst_VOP3__V_ADD_LSHL_U32::Inst_VOP3__V_ADD_LSHL_U32(InFmt_VOP3A *iFmt)
+: Inst_VOP3A(iFmt, "v_add_lshl_u32", false)
+{
+setFlag(ALU);
+} // Inst_VOP3__V_ADD_LSHL_U32
+
+Inst_VOP3__V_ADD_LSHL_U32::~Inst_VOP3__V_ADD_LSHL_U32()
+{
+} // ~Inst_VOP3__V_ADD_LSHL_U32
+
+// --- description from .arch file ---
+// D.u = (S0.u + S1.u) << S2.u[4:0].
+void
+Inst_VOP3__V_ADD_LSHL_U32::execute(GPUDynInstPtr gpuDynInst)
+{
+Wavefront *wf = gpuDynInst->wavefront();
+ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+src0.readSrc();
+src1.readSrc();
+src2.readSrc();
+
+/**
+ * input modifiers are supported by FP operations only
+ */
+assert(!(instData.ABS & 0x1));
+assert(!(instData.ABS & 0x2));
+assert(!(instData.ABS & 0x4));
+assert(!(extData.NEG & 0x1));
+assert(!(extData.NEG & 0x2));
+assert(!(extData.NEG & 0x4));
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (wf->execMask(lane)) {
+vdst[lane] =
+(src0[lane] + src1[lane]) << bits(src2[lane], 4, 0);
+}
+}
+
+vdst.write();
+} // execute
 // --- Inst_VOP3__V_LSHL_OR_B32 class methods ---

 Inst_VOP3__V_LSHL_OR_B32::Inst_VOP3__V_LSHL_OR_B32(InFmt_VOP3A *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh  
b/src/arch/amdgpu/vega/insts/instructions.hh

index e3e390b..1107c24 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -29532,6 +29532,42 @@
 void execute(GPUDynInstPtr) override;
 }; // Inst_VOP3__V_LSHL_ADD_U32

+class Inst_VOP3__V_ADD_LSHL_U32 : public Inst_VOP3A
+{
+  public:
+Inst_VOP3__V_ADD_LSHL_U32(InFmt_VOP3A*);
+~Inst_VOP3__V_ADD_LSHL_U32();
+
+int
+getNumOperands() override
+{
+return numDstRegOperands() + numSrcRegOperands();
+} // getNumOperands
+
+int numDstRegOperands() override { return 1; }
+int numSrcRegOperands() override { return 3; }
+
+int
+getOperandSize(int opIdx) override
+{
+switch (opIdx) {
+  case 0: //src_0
+return 4;
+  case 1: //src_1
+return 4;
+  case 2: //src_2
+return 4;
+  case 3: //vdst
+return 4;
+  default:
+fatal("op idx %i out of bounds\n", opIdx);
+return -1;
+}
+} // getOperandSize
+
+void execute(GPUDynInstPtr) override;
+}; // Inst_VOP3__V_ADD_LSHL_U32
+
 class Inst_VOP3__V_LSHL_OR_B32 : public Inst_VOP3A
 {
   public:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: 

[gem5-dev] Change in gem5/gem5[develop]: arch-vega: Implement V_AND_OR_B32

[Bobby Bruce (Gerrit) via gem5-dev]

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53868 )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-vega: Implement V_AND_OR_B32
..

arch-vega: Implement V_AND_OR_B32

Change-Id: I8daeb8de2db5996e132cf7ed729f02c3c94a6862
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53868
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
M src/arch/amdgpu/vega/decoder.cc
3 files changed, 96 insertions(+), 2 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/amdgpu/vega/decoder.cc  
b/src/arch/amdgpu/vega/decoder.cc

index b798bd0..b7bd344 100644
--- a/src/arch/amdgpu/vega/decoder.cc
+++ b/src/arch/amdgpu/vega/decoder.cc
@@ -6951,8 +6951,7 @@
 GPUStaticInst*
 Decoder::decode_OPU_VOP3__V_AND_OR_B32(MachInst iFmt)
 {
-fatal("Trying to decode instruction without a class\n");
-return nullptr;
+return new Inst_VOP3__V_AND_OR_B32(>iFmt_VOP3A);
 }

 GPUStaticInst*
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc  
b/src/arch/amdgpu/vega/insts/instructions.cc

index c60ba62..d12709a 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -32187,6 +32187,52 @@

 vdst.write();
 } // execute
+// --- Inst_VOP3__V_AND_OR_B32 class methods ---
+
+Inst_VOP3__V_AND_OR_B32::Inst_VOP3__V_AND_OR_B32(InFmt_VOP3A *iFmt)
+: Inst_VOP3A(iFmt, "v_and_or_b32", false)
+{
+setFlag(ALU);
+} // Inst_VOP3__V_AND_OR_B32
+
+Inst_VOP3__V_AND_OR_B32::~Inst_VOP3__V_AND_OR_B32()
+{
+} // ~Inst_VOP3__V_AND_OR_B32
+
+// --- description from .arch file ---
+// D.u = (S0.u & S1.u) | S2.u.
+// Input and output modifiers not supported.
+void
+Inst_VOP3__V_AND_OR_B32::execute(GPUDynInstPtr gpuDynInst)
+{
+Wavefront *wf = gpuDynInst->wavefront();
+ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+src0.readSrc();
+src1.readSrc();
+src2.readSrc();
+
+/**
+ * input modifiers are supported by FP operations only
+ */
+assert(!(instData.ABS & 0x1));
+assert(!(instData.ABS & 0x2));
+assert(!(instData.ABS & 0x4));
+assert(!(extData.NEG & 0x1));
+assert(!(extData.NEG & 0x2));
+assert(!(extData.NEG & 0x4));
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (wf->execMask(lane)) {
+vdst[lane] = (src0[lane] & src1[lane]) | src2[lane];
+}
+}
+
+vdst.write();
+} // execute
 // --- Inst_VOP3__V_MAD_F16 class methods ---

 Inst_VOP3__V_MAD_F16::Inst_VOP3__V_MAD_F16(InFmt_VOP3A *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh  
b/src/arch/amdgpu/vega/insts/instructions.hh

index 91edc10..88c133c 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -29640,6 +29640,42 @@
 void execute(GPUDynInstPtr) override;
 }; // Inst_VOP3__V_LSHL_OR_B32

+class Inst_VOP3__V_AND_OR_B32 : public Inst_VOP3A
+{
+  public:
+Inst_VOP3__V_AND_OR_B32(InFmt_VOP3A*);
+~Inst_VOP3__V_AND_OR_B32();
+
+int
+getNumOperands() override
+{
+return numDstRegOperands() + numSrcRegOperands();
+} // getNumOperands
+
+int numDstRegOperands() override { return 1; }
+int numSrcRegOperands() override { return 3; }
+
+int
+getOperandSize(int opIdx) override
+{
+switch (opIdx) {
+  case 0: //src_0
+return 4;
+  case 1: //src_1
+return 4;
+  case 2: //src_2
+return 4;
+  case 3: //vdst
+return 4;
+  default:
+fatal("op idx %i out of bounds\n", opIdx);
+return -1;
+}
+} // getOperandSize
+
+void execute(GPUDynInstPtr) override;
+}; // Inst_VOP3__V_AND_OR_B32
+
 class Inst_VOP3__V_MAD_F16 : public Inst_VOP3A
 {
   public:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8daeb8de2db5996e132cf7ed729f02c3c94a6862

[gem5-dev] Change in gem5/gem5[develop]: arch-vega: Implement V_ADD3_U32

[Bobby Bruce (Gerrit) via gem5-dev]

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53867 )


Change subject: arch-vega: Implement V_ADD3_U32
..

arch-vega: Implement V_ADD3_U32

Change-Id: I4d01265f946e289cbff56090c2dd193ea66d5c70
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53867
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/arch/amdgpu/vega/insts/instructions.cc
M src/arch/amdgpu/vega/insts/instructions.hh
M src/arch/amdgpu/vega/decoder.cc
3 files changed, 95 insertions(+), 2 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/amdgpu/vega/decoder.cc  
b/src/arch/amdgpu/vega/decoder.cc

index e616a7f..b798bd0 100644
--- a/src/arch/amdgpu/vega/decoder.cc
+++ b/src/arch/amdgpu/vega/decoder.cc
@@ -6939,8 +6939,7 @@
 GPUStaticInst*
 Decoder::decode_OPU_VOP3__V_ADD3_U32(MachInst iFmt)
 {
-fatal("Trying to decode instruction without a class\n");
-return nullptr;
+return new Inst_VOP3__V_ADD3_U32(>iFmt_VOP3A);
 }

 GPUStaticInst*
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc  
b/src/arch/amdgpu/vega/insts/instructions.cc

index 114859c..c60ba62 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -32096,6 +32096,51 @@

 vdst.write();
 } // execute
+// --- Inst_VOP3__V_ADD3_U32 class methods ---
+
+Inst_VOP3__V_ADD3_U32::Inst_VOP3__V_ADD3_U32(InFmt_VOP3A *iFmt)
+: Inst_VOP3A(iFmt, "v_add3_u32", false)
+{
+setFlag(ALU);
+} // Inst_VOP3__V_ADD3_U32
+
+Inst_VOP3__V_ADD3_U32::~Inst_VOP3__V_ADD3_U32()
+{
+} // ~Inst_VOP3__V_ADD3_U32
+
+// --- description from .arch file ---
+// D.u = S0.u + S1.u + S2.u.
+void
+Inst_VOP3__V_ADD3_U32::execute(GPUDynInstPtr gpuDynInst)
+{
+Wavefront *wf = gpuDynInst->wavefront();
+ConstVecOperandU32 src0(gpuDynInst, extData.SRC0);
+ConstVecOperandU32 src1(gpuDynInst, extData.SRC1);
+ConstVecOperandU32 src2(gpuDynInst, extData.SRC2);
+VecOperandU32 vdst(gpuDynInst, instData.VDST);
+
+src0.readSrc();
+src1.readSrc();
+src2.readSrc();
+
+/**
+ * input modifiers are supported by FP operations only
+ */
+assert(!(instData.ABS & 0x1));
+assert(!(instData.ABS & 0x2));
+assert(!(instData.ABS & 0x4));
+assert(!(extData.NEG & 0x1));
+assert(!(extData.NEG & 0x2));
+assert(!(extData.NEG & 0x4));
+
+for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
+if (wf->execMask(lane)) {
+vdst[lane] = src0[lane] + src1[lane] + src2[lane];
+}
+}
+
+vdst.write();
+} // execute
 // --- Inst_VOP3__V_LSHL_OR_B32 class methods ---

 Inst_VOP3__V_LSHL_OR_B32::Inst_VOP3__V_LSHL_OR_B32(InFmt_VOP3A *iFmt)
diff --git a/src/arch/amdgpu/vega/insts/instructions.hh  
b/src/arch/amdgpu/vega/insts/instructions.hh

index 1107c24..91edc10 100644
--- a/src/arch/amdgpu/vega/insts/instructions.hh
+++ b/src/arch/amdgpu/vega/insts/instructions.hh
@@ -29568,6 +29568,42 @@
 void execute(GPUDynInstPtr) override;
 }; // Inst_VOP3__V_ADD_LSHL_U32

+class Inst_VOP3__V_ADD3_U32 : public Inst_VOP3A
+{
+  public:
+Inst_VOP3__V_ADD3_U32(InFmt_VOP3A*);
+~Inst_VOP3__V_ADD3_U32();
+
+int
+getNumOperands() override
+{
+return numDstRegOperands() + numSrcRegOperands();
+} // getNumOperands
+
+int numDstRegOperands() override { return 1; }
+int numSrcRegOperands() override { return 3; }
+
+int
+getOperandSize(int opIdx) override
+{
+switch (opIdx) {
+  case 0: //src_0
+return 4;
+  case 1: //src_1
+return 4;
+  case 2: //src_2
+return 4;
+  case 3: //vdst
+return 4;
+  default:
+fatal("op idx %i out of bounds\n", opIdx);
+return -1;
+}
+} // getOperandSize
+
+void execute(GPUDynInstPtr) override;
+}; // Inst_VOP3__V_ADD3_U32
+
 class Inst_VOP3__V_LSHL_OR_B32 : public Inst_VOP3A
 {
   public:

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Gerrit-Change-Id: I4d01265f946e289cbff56090c2dd193ea66d5c70
Gerrit-Change-Number: 53867
Gerrit-PatchSet: 4
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: 

[gem5-dev] Change in gem5/gem5[develop]: arch-vega: Implement S_SLEEP

[Bobby Bruce (Gerrit) via gem5-dev]

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53883 )


Change subject: arch-vega: Implement S_SLEEP
..

arch-vega: Implement S_SLEEP

This is merely copied from arch-gcn3.

Change-Id: Ibd2bda37fe9adc083a35efab0f59617d386019b9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53883
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/arch/amdgpu/vega/insts/instructions.cc
1 file changed, 21 insertions(+), 1 deletion(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/amdgpu/vega/insts/instructions.cc  
b/src/arch/amdgpu/vega/insts/instructions.cc

index d12709a..28473d7 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -4608,6 +4608,8 @@
 Inst_SOPP__S_SLEEP::Inst_SOPP__S_SLEEP(InFmt_SOPP *iFmt)
 : Inst_SOPP(iFmt, "s_sleep")
 {
+setFlag(ALU);
+setFlag(Sleep);
 } // Inst_SOPP__S_SLEEP

 Inst_SOPP__S_SLEEP::~Inst_SOPP__S_SLEEP()
@@ -4620,7 +4622,10 @@
 void
 Inst_SOPP__S_SLEEP::execute(GPUDynInstPtr gpuDynInst)
 {
-panicUnimplemented();
+ScalarRegI32 simm16 = (ScalarRegI32)instData.SIMM16;
+gpuDynInst->wavefront()->setStatus(Wavefront::S_STALLED_SLEEP);
+// sleep duration is specified in multiples of 64 cycles
+gpuDynInst->wavefront()->setSleepTime(64 * simm16);
 } // execute
 // --- Inst_SOPP__S_SETPRIO class methods ---


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Gerrit-Change-Id: Ibd2bda37fe9adc083a35efab0f59617d386019b9
Gerrit-Change-Number: 53883
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: stdlib: Add beta simulate module to the gem5 stdlib

[Bobby Bruce (Gerrit) via gem5-dev]

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/50753 )


Change subject: stdlib: Add beta simulate module to the gem5 stdlib
..

stdlib: Add beta simulate module to the gem5 stdlib

This module is used to semi-automate the running of gem5 simulation,
mostly by handling exit events automatically and removing instantiation
boilerplate code.

NOTE: This module is still in beta.

Change-Id: I4706119478464efcf4d92e3a1da05bddd0953b6a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50753
Maintainer: Bobby Bruce 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
---
M configs/example/gem5_library/riscv-fs.py
M configs/example/gem5_library/arm-hello.py
A src/python/gem5/simulate/__init__.py
A src/python/gem5/simulate/exit_event.py
M tests/gem5/configs/parsec_disk_run.py
M tests/gem5/configs/boot_kvm_switch_exit.py
M configs/example/gem5_library/x86-ubuntu-run-with-kvm.py
M src/python/SConscript
A src/python/gem5/simulate/simulator.py
M configs/example/gem5_library/x86-ubuntu-run.py
M tests/gem5/configs/riscv_boot_exit_run.py
M tests/gem5/configs/simple_binary_run.py
A src/python/gem5/simulate/exit_event_generators.py
M tests/gem5/configs/x86_boot_exit_run.py
14 files changed, 646 insertions(+), 197 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/gem5_library/arm-hello.py  
b/configs/example/gem5_library/arm-hello.py

index 5a2f46c..b1f6f38 100644
--- a/configs/example/gem5_library/arm-hello.py
+++ b/configs/example/gem5_library/arm-hello.py
@@ -41,9 +41,6 @@
 ```
 """

-import m5
-from m5.objects import Root
-
 from gem5.isas import ISA
 from gem5.utils.requires import requires
 from gem5.resources.resource import Resource
@@ -52,6 +49,7 @@
 from gem5.components.boards.simple_board import SimpleBoard
 from gem5.components.cachehierarchies.classic.no_cache import NoCache
 from gem5.components.processors.simple_processor import SimpleProcessor
+from gem5.simulate.simulator import Simulator

 # This check ensures the gem5 binary is compiled to the ARM ISA target. If  
not,

 # an exception will be thrown.
@@ -89,12 +87,13 @@
 Resource("arm-hello64-static")
 )

-# Lastly we setup the root, instantiate the design, and run the simulation.
-root = Root(full_system=False, system=board)
+# Lastly we run the simulation.
+simulator = Simulator(board=board, full_system=False)
+simulator.run()

-m5.instantiate()
-
-exit_event = m5.simulate()
 print(
-"Exiting @ tick {} because {}.".format(m5.curTick(),  
exit_event.getCause())

+"Exiting @ tick {} because {}.".format(
+simulator.get_current_tick(),
+simulator.get_last_exit_event_cause(),
+)
 )
diff --git a/configs/example/gem5_library/riscv-fs.py  
b/configs/example/gem5_library/riscv-fs.py

index 4d0a2c8..4c1f117 100644
--- a/configs/example/gem5_library/riscv-fs.py
+++ b/configs/example/gem5_library/riscv-fs.py
@@ -39,9 +39,6 @@
   password: `root`)
 """

-import m5
-from m5.objects import Root
-
 from gem5.components.boards.riscv_board import RiscvBoard
 from gem5.components.memory import SingleChannelDDR3_1600
 from gem5.components.processors.simple_processor import SimpleProcessor
@@ -53,6 +50,7 @@
 from gem5.isas import ISA
 from gem5.utils.requires import requires
 from gem5.resources.resource import Resource
+from gem5.simulate.simulator import Simulator

 # Run a check to ensure the right version of gem5 is being used.
 requires(isa_required=ISA.RISCV)
@@ -84,13 +82,10 @@
disk_image=Resource("riscv-disk-img"),
 )

-root = Root(full_system=True, system=board)
-
-m5.instantiate()
-
+simulator = Simulator(board=board)
 print("Beginning simulation!")
 # Note: This simulation will never stop. You can access the terminal upon  
boot
 # using m5term (`./util/term`): `./m5term localhost `. Note the  
``

 # value is obtained from the gem5 terminal stdout. Look out for
 # "system.platform.terminal: Listening for connections on port ".
-exit_event = m5.simulate()
\ No newline at end of file
+simulator.run()
\ No newline at end of file
diff --git a/configs/example/gem5_library/x86-ubuntu-run-with-kvm.py  
b/configs/example/gem5_library/x86-ubuntu-run-with-kvm.py

index 630cb09..fa84960 100644
--- a/configs/example/gem5_library/x86-ubuntu-run-with-kvm.py
+++ b/configs/example/gem5_library/x86-ubuntu-run-with-kvm.py
@@ -35,14 +35,11 @@
 -

 ```
-scons build/X86_MESI_Two_Level/gem5.opt
+scons build/X86/gem5.opt
 ./build/X86/gem5.opt  
configs/example/gem5_library/x86-ubuntu-run-with-kvm.py

 ```
 """

-import m5
-from m5.objects import Root
-
 from gem5.utils.requires import requires
 from gem5.components.boards.x86_board import X86Board
 from gem5.components.memory.single_channel import 

[gem5-dev] Change in gem5/gem5[develop]: tests: Add default DRAM class for riscv/x86 boot tests

[Bobby Bruce (Gerrit) via gem5-dev]

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53848 )


Change subject: tests: Add default DRAM class for riscv/x86 boot tests
..

tests: Add default DRAM class for riscv/x86 boot tests

These scripts can be quite useful for running quick boot tests. However,
having to specify the DRAM each time is laborious. A sensible default
has therefore been set.

Change-Id: I2714b479853f686246383411a46a98494ba617da
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53848
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M tests/gem5/configs/riscv_boot_exit_run.py
M tests/gem5/configs/x86_boot_exit_run.py
2 files changed, 21 insertions(+), 2 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/gem5/configs/riscv_boot_exit_run.py  
b/tests/gem5/configs/riscv_boot_exit_run.py

index 38f57d8..cf6d0f7 100644
--- a/tests/gem5/configs/riscv_boot_exit_run.py
+++ b/tests/gem5/configs/riscv_boot_exit_run.py
@@ -80,7 +80,8 @@
 "-d",
 "--dram-class",
 type=str,
-required=True,
+required=False,
+default="DualChannelDDR3_1600",
 help="The python class for the memory interface to use"
 )

diff --git a/tests/gem5/configs/x86_boot_exit_run.py  
b/tests/gem5/configs/x86_boot_exit_run.py

index 96d1dad..217a823 100644
--- a/tests/gem5/configs/x86_boot_exit_run.py
+++ b/tests/gem5/configs/x86_boot_exit_run.py
@@ -78,7 +78,8 @@
 "-d",
 "--dram-class",
 type=str,
-required=True,
+required=False,
+default="DualChannelDDR3_1600",
 help="The python class for the memory interface to use"
 )
 parser.add_argument(

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2714b479853f686246383411a46a98494ba617da
Gerrit-Change-Number: 53848
Gerrit-PatchSet: 5
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: configs: Fix terminology to 'ticks' in NPB configs

[Bobby Bruce (Gerrit) via gem5-dev]

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53847 )


 (

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: configs: Fix terminology to 'ticks' in NPB configs
..

configs: Fix terminology to 'ticks' in NPB configs

Instructions was not the correct terminolgy here. It should be ticks.

Change-Id: I08c125049e8dc2cc8c488a820530c6c6a45d7367
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53847
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/example/gem5_library/x86-npb-benchmarks.py
1 file changed, 26 insertions(+), 11 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/gem5_library/x86-npb-benchmarks.py  
b/configs/example/gem5_library/x86-npb-benchmarks.py

index ba7b17c..1609521 100644
--- a/configs/example/gem5_library/x86-npb-benchmarks.py
+++ b/configs/example/gem5_library/x86-npb-benchmarks.py
@@ -108,10 +108,10 @@
 )

 parser.add_argument(
-"--maxinsts",
+"--ticks",
 type = int,
-help = "Optionally put the maximum number of instructions to execute \
-during ROI simulation. It accepts an integer number."
+help = "Optionally put the maximum number of ticks to execute during  
the "\

+"ROI. It accepts an integer value."
 )

 args = parser.parse_args()
@@ -259,13 +259,13 @@
 # The next exit_event is to simulate the ROI. It should be exited with a  
cause

 # marked by `workend`.

-# Next, we need to check if the user passed a value for --maxinsts. If yes,
-# then we limit out execution to this time only. Otherwise, we simulate  
until

-# the ROI ends.
-if args.maxinsts is None:
-exit_event = m5.simulate()
+# Next, we need to check if the user passed a value for --ticks. If yes,
+# then we limit out execution to this number of ticks during the ROI.
+# Otherwise, we simulate until the ROI ends.
+if args.ticks:
+exit_event = m5.simulate(args.ticks)
 else:
-exit_event = m5.simulate(args.maxinsts)
+exit_event = m5.simulate()


 # Reached the end of ROI.
@@ -279,8 +279,8 @@
 m5.stats.dump()
 end_tick = m5.curTick()
 elif exit_event.getCause() == "simulate() limit reached" and \
-args.maxinsts is not None:
-print("Dump stats at the end of {} instructions".format(args.maxinsts))
+args.ticks is not None:
+print("Dump stats at the end of {} ticks in the  
ROI".format(args.ticks))


 m5.stats.dump()
 end_tick = m5.curTick()

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I08c125049e8dc2cc8c488a820530c6c6a45d7367
Gerrit-Change-Number: 53847
Gerrit-PatchSet: 4
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: tests: Add test for the lupv example

[Bobby Bruce (Gerrit) via gem5-dev]

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53903 )


Change subject: tests: Add test for the lupv example
..

tests: Add test for the lupv example

Change-Id: Ib17f59b5b6ab9704be14e73d203bbab61caada90
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53903
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/example/lupv/run_lupv.py
M tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
2 files changed, 38 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/lupv/run_lupv.py  
b/configs/example/lupv/run_lupv.py

index 721adcd..93eaa86 100644
--- a/configs/example/lupv/run_lupv.py
+++ b/configs/example/lupv/run_lupv.py
@@ -64,6 +64,13 @@
 parser.add_argument(
 "num_cpus", type=int, help="The number of CPU in the system"
 )
+parser.add_argument(
+"--max-ticks",
+type=int,
+required=False,
+default=m5.MaxTick,
+help="The maximum number of ticks to simulate. Used for testing.",
+)

 args = parser.parse_args()

@@ -105,7 +112,7 @@
 m5.instantiate()
 print("Beginning simulation!")

-exit_event = m5.simulate()
+exit_event = m5.simulate(args.max_ticks)

 print(
 "Exiting @ tick {} because {}.".format(m5.curTick(),  
exit_event.getCause())
diff --git  
a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py  
b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py

index 8b0c48b..2aca184 100644
--- a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
+++ b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py
@@ -174,3 +174,20 @@
 valid_hosts=constants.supported_hosts,
 length=constants.long_tag,
 )
+
+gem5_verify_config(
+name="test-lupv-example",
+fixtures=(),
+verifiers=(),
+config=joinpath(
+config.base_dir,
+"configs",
+"example",
+"lupv",
+"run_lupv.py",
+),
+config_args=["timing", "1", "--max-ticks", "10"],
+valid_isas=(constants.riscv_tag,),
+valid_hosts=constants.supported_hosts,
+length=constants.long_tag,
+)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib17f59b5b6ab9704be14e73d203bbab61caada90
Gerrit-Change-Number: 53903
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-Reviewer: melissa jost 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: stdlib,configs: Set SPEC examples partition param to optional

[Bobby Bruce (Gerrit) via gem5-dev]

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53846 )


 (

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: stdlib,configs: Set SPEC examples partition param to  
optional

..

stdlib,configs: Set SPEC examples partition param to optional

The SPEC2006 and SPEC2017 example configs require the passing of SPEC
disk image to function correctly. Prior to this commit a root partition
parameter was required. However, disk images don't necessarily have
partitions. In this case an empty string needed passed.

This patch makes the root partition parameter optional. If a disk image
does not have a root partition, it does not need specified.

Change-Id: Ic0093c70c72ab83ffaca54c8ad24245d84a5e5ba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53846
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
M configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
2 files changed, 25 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py  
b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py

index 5624eaf..c1b7a3b 100644
--- a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
+++ b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
@@ -117,7 +117,8 @@
 parser.add_argument(
 "--partition",
 type = str,
-required = True,
+required = False,
+default=None,
 help = "Input the root partition of the SPEC disk-image. If the disk  
is \

 not partitioned, then pass \"\"."
 )
diff --git a/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py  
b/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py

index 25bbbea..2a03389 100644
--- a/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
+++ b/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
@@ -123,7 +123,8 @@
 parser.add_argument(
 "--partition",
 type = str,
-required = True,
+required = False,
+default=None,
 help = "Input the root partition of the SPEC disk-image. If the disk  
is \

 not partitioned, then pass \"\"."
 )

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic0093c70c72ab83ffaca54c8ad24245d84a5e5ba
Gerrit-Change-Number: 53846
Gerrit-PatchSet: 4
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Re: Broken SST due to python changes

[Gabe Black via gem5-dev]

Dumb question: I'm trying to run gdb inside this container on the sst
thing. How do I do that? It's not installed in the container now, and I
can't (easily) figure out how to get it installed. I can tell docker to
install it, but then it seems to throw that away as soon as the command
ends.

Gabe

On Fri, Dec 10, 2021 at 5:09 PM Bobby Bruce  wrote:

> Thanks Gabe,
>
> This is very much appreciated. I'm going to create the release staging
> once a couple more things get in. Feel free to push any patches related to
> these bugs to the release staging branch.
>
> If there is an order of priority I'd say the bug affecting SST is of
> higher importance than that affecting the Weeklies (as far as I can see the
> latter is hard to trigger). That being said, we'll apply both to the new
> release one way or another.
>
> --
> Dr. Bobby R. Bruce
> Room 3050,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
> On Fri, Dec 10, 2021 at 5:02 PM Gabe Black  wrote:
>
>> Hi Bobby, not yet, I meant to look into this for the last couple days but
>> kept running out of time. I'm sitting down to work on it right now.
>>
>> Gabe
>>
>> On Fri, Dec 10, 2021 at 1:21 PM Bobby Bruce  wrote:
>>
>>> Hey Gabe,
>>>
>>> Is there any update on this?
>>>
>>> Kind regards,
>>> Bobby
>>> --
>>> Dr. Bobby R. Bruce
>>> Room 3050,
>>> Kemper Hall, UC Davis
>>> Davis,
>>> CA, 95616
>>>
>>> web: https://www.bobbybruce.net
>>>
>>>
>>> On Wed, Dec 8, 2021 at 5:51 PM Hoa Nguyen via gem5-dev <
>>> gem5-dev@gem5.org> wrote:
>>>
 Hi Gabe,

 I have more details about this. In this use case, SST initialized the
 Python environment before adding the "gem5 object". This gem5 object
 will add more Python stuff from gem5 to the environment.

 The function that does that is initPython()

 https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/ext/sst/gem5.cc#415

 The following commands will pull the docker image for SST testing
 purposes (note that host_gem5_root and guest_gem5_root must be
 specified),

 ```
 docker run -u $UID:$GID --volume
 "${host_gem5_root}":"${guest_gem5_root}" -w \
  "${guest_gem5_root}" --rm gcr.io/gem5-test/sst-env \
  bash -c "\
 scons build/RISCV/libgem5_opt.so -j${nproc} --without-tcmalloc; \
 cd ext/sst; \
 make clean; make; \
 sst --add-lib-path=./ sst/example.py;
 ```

 We appreciate your help!

 Regards,
 Hoa Nguyen

 On 12/8/21, Jason Lowe-Power  wrote:
 > Hey Gabe,
 >
 > This change breaks the SST integration. In the SST integration python
 is
 > initialized from the SST module, not from init.cc (this is because
 SST has
 > their own python interpreter).
 >
 > We would appreciate some help in fixing this. Hoa and Giacomo can
 give you
 > an example that's breaking to help you fix it, I believe.
 >
 > https://gem5-review.googlesource.com/c/public/gem5/+/49413
 >
 > There's strong interest in having the SST integration working in this
 > current release. We've spent a lot of time figuring out all of the
 > intricacies and would appreciate any help you can provide in these
 last few
 > days before the release!
 >
 > Thanks!
 >
 > Jason
 >
 ___
 gem5-dev mailing list -- gem5-dev@gem5.org
 To unsubscribe send an email to gem5-dev-le...@gem5.org
 %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

>>>
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[gem5-dev] Re: Broken SST due to python changes

[Bobby Bruce via gem5-dev]

Thanks Gabe,

This is very much appreciated. I'm going to create the release staging once
a couple more things get in. Feel free to push any patches related to these
bugs to the release staging branch.

If there is an order of priority I'd say the bug affecting SST is of higher
importance than that affecting the Weeklies (as far as I can see the latter
is hard to trigger). That being said, we'll apply both to the new release
one way or another.

--
Dr. Bobby R. Bruce
Room 3050,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Fri, Dec 10, 2021 at 5:02 PM Gabe Black  wrote:

> Hi Bobby, not yet, I meant to look into this for the last couple days but
> kept running out of time. I'm sitting down to work on it right now.
>
> Gabe
>
> On Fri, Dec 10, 2021 at 1:21 PM Bobby Bruce  wrote:
>
>> Hey Gabe,
>>
>> Is there any update on this?
>>
>> Kind regards,
>> Bobby
>> --
>> Dr. Bobby R. Bruce
>> Room 3050,
>> Kemper Hall, UC Davis
>> Davis,
>> CA, 95616
>>
>> web: https://www.bobbybruce.net
>>
>>
>> On Wed, Dec 8, 2021 at 5:51 PM Hoa Nguyen via gem5-dev 
>> wrote:
>>
>>> Hi Gabe,
>>>
>>> I have more details about this. In this use case, SST initialized the
>>> Python environment before adding the "gem5 object". This gem5 object
>>> will add more Python stuff from gem5 to the environment.
>>>
>>> The function that does that is initPython()
>>>
>>> https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/ext/sst/gem5.cc#415
>>>
>>> The following commands will pull the docker image for SST testing
>>> purposes (note that host_gem5_root and guest_gem5_root must be
>>> specified),
>>>
>>> ```
>>> docker run -u $UID:$GID --volume
>>> "${host_gem5_root}":"${guest_gem5_root}" -w \
>>>  "${guest_gem5_root}" --rm gcr.io/gem5-test/sst-env \
>>>  bash -c "\
>>> scons build/RISCV/libgem5_opt.so -j${nproc} --without-tcmalloc; \
>>> cd ext/sst; \
>>> make clean; make; \
>>> sst --add-lib-path=./ sst/example.py;
>>> ```
>>>
>>> We appreciate your help!
>>>
>>> Regards,
>>> Hoa Nguyen
>>>
>>> On 12/8/21, Jason Lowe-Power  wrote:
>>> > Hey Gabe,
>>> >
>>> > This change breaks the SST integration. In the SST integration python
>>> is
>>> > initialized from the SST module, not from init.cc (this is because SST
>>> has
>>> > their own python interpreter).
>>> >
>>> > We would appreciate some help in fixing this. Hoa and Giacomo can give
>>> you
>>> > an example that's breaking to help you fix it, I believe.
>>> >
>>> > https://gem5-review.googlesource.com/c/public/gem5/+/49413
>>> >
>>> > There's strong interest in having the SST integration working in this
>>> > current release. We've spent a lot of time figuring out all of the
>>> > intricacies and would appreciate any help you can provide in these
>>> last few
>>> > days before the release!
>>> >
>>> > Thanks!
>>> >
>>> > Jason
>>> >
>>> ___
>>> gem5-dev mailing list -- gem5-dev@gem5.org
>>> To unsubscribe send an email to gem5-dev-le...@gem5.org
>>> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>>>
>>
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[gem5-dev] Re: Broken SST due to python changes

[Gabe Black via gem5-dev]

Hi Bobby, not yet, I meant to look into this for the last couple days but
kept running out of time. I'm sitting down to work on it right now.

Gabe

On Fri, Dec 10, 2021 at 1:21 PM Bobby Bruce  wrote:

> Hey Gabe,
>
> Is there any update on this?
>
> Kind regards,
> Bobby
> --
> Dr. Bobby R. Bruce
> Room 3050,
> Kemper Hall, UC Davis
> Davis,
> CA, 95616
>
> web: https://www.bobbybruce.net
>
>
> On Wed, Dec 8, 2021 at 5:51 PM Hoa Nguyen via gem5-dev 
> wrote:
>
>> Hi Gabe,
>>
>> I have more details about this. In this use case, SST initialized the
>> Python environment before adding the "gem5 object". This gem5 object
>> will add more Python stuff from gem5 to the environment.
>>
>> The function that does that is initPython()
>>
>> https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/ext/sst/gem5.cc#415
>>
>> The following commands will pull the docker image for SST testing
>> purposes (note that host_gem5_root and guest_gem5_root must be
>> specified),
>>
>> ```
>> docker run -u $UID:$GID --volume "${host_gem5_root}":"${guest_gem5_root}"
>> -w \
>>  "${guest_gem5_root}" --rm gcr.io/gem5-test/sst-env \
>>  bash -c "\
>> scons build/RISCV/libgem5_opt.so -j${nproc} --without-tcmalloc; \
>> cd ext/sst; \
>> make clean; make; \
>> sst --add-lib-path=./ sst/example.py;
>> ```
>>
>> We appreciate your help!
>>
>> Regards,
>> Hoa Nguyen
>>
>> On 12/8/21, Jason Lowe-Power  wrote:
>> > Hey Gabe,
>> >
>> > This change breaks the SST integration. In the SST integration python is
>> > initialized from the SST module, not from init.cc (this is because SST
>> has
>> > their own python interpreter).
>> >
>> > We would appreciate some help in fixing this. Hoa and Giacomo can give
>> you
>> > an example that's breaking to help you fix it, I believe.
>> >
>> > https://gem5-review.googlesource.com/c/public/gem5/+/49413
>> >
>> > There's strong interest in having the SST integration working in this
>> > current release. We've spent a lot of time figuring out all of the
>> > intricacies and would appreciate any help you can provide in these last
>> few
>> > days before the release!
>> >
>> > Thanks!
>> >
>> > Jason
>> >
>> ___
>> gem5-dev mailing list -- gem5-dev@gem5.org
>> To unsubscribe send an email to gem5-dev-le...@gem5.org
>> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>>
>
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[gem5-dev] Build failed in Jenkins: weekly #16

[jenkins-no-reply--- via gem5-dev]

See 

Changes:

[Bobby R. Bruce] scons,misc: Update default X86 protocol to MESI_Two_Level

[Bobby R. Bruce] stdlib: Add X86DemoBoard

[Bobby R. Bruce] tests: Add a nightly test for SST integration.

[msamani] stdlib: Updated MuliChannelMemory constructor

[msamani] tests: Adding new test for traffic_gen

[msamani] stdlib: Adding clock_domain to GUPSGenerators

[msamani] test: Updating simple_traffic_run and adding tests

[msamani] tests: Adding MultiChannelMemory to x86-boot-tests

[msamani] tests: Adding MultiChannelMemory to riscv-boot

[giacomo.travaglini] ext: Make gem5-SST Memory Size configurable from script

[Jason Lowe-Power] arch-arm,arch-sparc: Remove legacy stat for faults

[chenzou] base-stats: HDF5 calls with better compatibility

[matthew.poremba] dev-amdgpu: Hotfix variable initialization

[giacomo.travaglini] arch-arm, dev-arm: Move inSecureState helper to ISA class

[giacomo.travaglini] arch-arm: Remove currOpMode utility function

[giacomo.travaglini] arch-arm, dev-arm: Add currEL function to the ISA class

[msamani] stdlib: Removing SingleChannelMemory

[matthew.poremba] configs,mem-ruby: Remove reference to old GPU ptls

[matthew.poremba] dev-hsa,gpu-compute: Properly assign DmaVirtDevices in py

[Bobby R. Bruce] scons,misc: Fix broken X86_MI_example build_opts

[melissakjost] dev: Added new LupIO-RTC device

[melissakjost] dev: Introduced new LupV Platform

[melissakjost] stdlib: Introduced new LupV Board

[melissakjost] dev: Added new LupIO-RNG device

[melissakjost] stdlib: Added LupioRNG to LupVBoard

[melissakjost] dev: Added new LupIO-TTY device

[melissakjost] stdlib: Added LupioTTY to LupVBoard

[melissakjost] dev: Added new Lupio-BLK Device

[melissakjost] stdlib: Added LupioBLK Device to LupVBoard

[melissakjost] dev: Added new LupIO-TMR device

[melissakjost] dev: Added new LupIO-PIC device

[melissakjost] stdlib: Modified LupV Platform + Board to use LupioPIC + TMR

[melissakjost] dev: Modified LupioBLK and LupioTTY to use LupioPIC

[melissakjost] dev: Modify LupIO-TMR for SMP support

[melissakjost] dev: Added new Lupio-IPI device

[melissakjost] stdlib: Added LupIO-IPI to the LupV Board

[melissakjost] dev: Added new Lupio-SYS device

[melissakjost] stdlib: Added Lupio-SYS device to LupV Board

[melissakjost] stdlib: Moved LupV Board to an experimental folder

[melissakjost] stdlib: Update the LupvBoard to account for stdlib changes

[melissakjost] stdlib: Update the LupvBoard to use 'requires'

[melissakjost] stdlib: Update the LupvBoard to use KernelDiskWorkload

[melissakjost] configs: Added LupV script to configs

[gabe.black] sim-se: Handle empty paths when resolving an "at" path.

[gabe.black] sim-se: Implement the newfstatat system call.

[gabe.black] arch-x86: Hook up system calls for 64 bit processes.

[gabe.black] arch-x86: Hook up the newfstatat system call for 64 bit Linux.

[yuhsingw] fastmodel: add setResetAddr interface

[yuhsingw] fastmodel: CortexA76 implements setResetAddr interface

[yuhsingw] fastmodel: CortexR52 implements setResetAddr interface

[gabe.black] scons: Add sim_object and enums arguments to SimObject().

[gabe.black] scons: When importing SimObjects, use a copy of globals().

[gabe.black] python,scons: Add a dummy m5/objects/SimObject.py.

[gabe.black] python,sim: Change how the m5.* importer code is integrated.

[gabe.black] sim: Eliminate m5MainCommands and simplify calling m5.main.

[gabe.black] sim: Use pybind11 consistently in sim/init.(hh|cc).

[gabe.black] python: Insert gem5's m5 importer at the front of sys.meta_path.

[gabe.black] sim: Clean up and simplify main().

[gabe.black] sim,misc: Move protobuf housekeeping out of gem5Main.

[gabe.black] sim: Collapse gem5Main into main.

[gabe.black] python,sim,util: Move EmbeddedPython into it's own file.

[gabe.black] scons: Remove a workaround for a very old SCons bug.

[gabe.black] python: Remove python/embedded.cc's dependence on the rest of gem5.

[gabe.black] python,scons: Add a gem5py_m5 program which supports the m5 module.

[gabe.black] scons: Ensure the gem5py_env always has embedded python.

[gabe.black] scons: Record the sim_objects and enums passed into SimObject().

[gabe.black] scons: Use an external script to generate param struct headers.

[gabe.black] scons: Also build param struct .cc files using a helper script.

[garbage2collector] python: Define deprecated and callOnce decorators

[matthew.poremba] arch-gcn3: Delete extraneous registers header

[kggoswami] stdlib,configs: Adding a config to run PARSEC using stdlib.

[kggoswami] stdlib,configs: Adding a config to run NPB using stdlib.

[kggoswami] stdlib,configs: Adding a config to run GAPBS using stdlib.

[kggoswami] stdlib,configs: Config added for RISCV boot-test using stdlib.

[kggoswami] stdlib,configs: Config added for SPEC CPU2006 using stdlib.

[kggoswami] stdlib,configs: Config added for SPEC CPU2017 using stdlib.

[Bobby R. Bruce] dev: 

[gem5-dev] Re: Broken SST due to python changes

[Bobby Bruce via gem5-dev]

Hey Gabe,

Is there any update on this?

Kind regards,
Bobby
--
Dr. Bobby R. Bruce
Room 3050,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Wed, Dec 8, 2021 at 5:51 PM Hoa Nguyen via gem5-dev 
wrote:

> Hi Gabe,
>
> I have more details about this. In this use case, SST initialized the
> Python environment before adding the "gem5 object". This gem5 object
> will add more Python stuff from gem5 to the environment.
>
> The function that does that is initPython()
>
> https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/ext/sst/gem5.cc#415
>
> The following commands will pull the docker image for SST testing
> purposes (note that host_gem5_root and guest_gem5_root must be
> specified),
>
> ```
> docker run -u $UID:$GID --volume "${host_gem5_root}":"${guest_gem5_root}"
> -w \
>  "${guest_gem5_root}" --rm gcr.io/gem5-test/sst-env \
>  bash -c "\
> scons build/RISCV/libgem5_opt.so -j${nproc} --without-tcmalloc; \
> cd ext/sst; \
> make clean; make; \
> sst --add-lib-path=./ sst/example.py;
> ```
>
> We appreciate your help!
>
> Regards,
> Hoa Nguyen
>
> On 12/8/21, Jason Lowe-Power  wrote:
> > Hey Gabe,
> >
> > This change breaks the SST integration. In the SST integration python is
> > initialized from the SST module, not from init.cc (this is because SST
> has
> > their own python interpreter).
> >
> > We would appreciate some help in fixing this. Hoa and Giacomo can give
> you
> > an example that's breaking to help you fix it, I believe.
> >
> > https://gem5-review.googlesource.com/c/public/gem5/+/49413
> >
> > There's strong interest in having the SST integration working in this
> > current release. We've spent a lot of time figuring out all of the
> > intricacies and would appreciate any help you can provide in these last
> few
> > days before the release!
> >
> > Thanks!
> >
> > Jason
> >
> ___
> gem5-dev mailing list -- gem5-dev@gem5.org
> To unsubscribe send an email to gem5-dev-le...@gem5.org
> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>
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[gem5-dev] Build failed in Jenkins: nightly #69

[jenkins-no-reply--- via gem5-dev]

See 

Changes:

[giacomo.travaglini] ext: Fix segfault in simulate_limit_event shortcut

[giacomo.travaglini] ext: Make gem5-SST support CMOs

[giacomo.travaglini] ext, configs: Add example Arm gem5 SST platform

[giacomo.travaglini] ext: Add an Arm section for gem5-SST README.md

[giacomo.travaglini] ext: Avoid content duplication in gem5-SST docs

[matthew.poremba] arch-gcn3,gpu-compute: Move TLB to common folder in amdgpu

[Bobby R. Bruce] arch-arm: Use ArmRelease in MMU and TableWalker


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[gem5-dev] Change in gem5/gem5[develop]: stdlib: Add CustomDiskImageResource

[Bobby Bruce (Gerrit) via gem5-dev]

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53844 )


Change subject: stdlib: Add CustomDiskImageResource
..

stdlib: Add CustomDiskImageResource

This CustomResource can be used to specify a custom, local disk image.
It allows the user to specify the disk root partition parameter
considerably easier than when setting a disk image through a
CustomResource.

Change-Id: I8189ad065124d028aea9fab1c7f07108aa4ce6d5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53844
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
M src/python/gem5/resources/resource.py
M configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
3 files changed, 55 insertions(+), 22 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py  
b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py

index 0bd5320..5624eaf 100644
--- a/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
+++ b/configs/example/gem5_library/x86-spec-cpu2006-benchmarks.py
@@ -65,7 +65,7 @@
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
 from gem5.coherence_protocol import CoherenceProtocol
-from gem5.resources.resource import Resource, CustomResource
+from gem5.resources.resource import Resource, CustomDiskImageResource

 from m5.stats.gem5stats import get_simstat
 from m5.util import warn
@@ -227,15 +227,6 @@

 command = "{} {} {}".format(args.benchmark, args.size, output_dir)

-# For enabling CustomResource, we pass an additional parameter to mount the
-# correct partition.
-
-metadata = {
-"additional_metadata" : {
-"root_partition" : args.partition,
-},
-}
-
 board.set_kernel_disk_workload(
 # The x86 linux kernel will be automatically downloaded to the
 # `~/.cache/gem5` directory if not already present.
@@ -245,9 +236,9 @@
 "x86-linux-kernel-4.19.83",
 ),
 # The location of the x86 SPEC CPU 2017 image
-disk_image=CustomResource(
+disk_image=CustomDiskImageResource(
 args.image,
-metadata=metadata
+disk_root_partition=args.partition,
 ),
 readfile_contents=command,
 )
diff --git a/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py  
b/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py

index b4bb9ac..25bbbea 100644
--- a/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
+++ b/configs/example/gem5_library/x86-spec-cpu2017-benchmarks.py
@@ -63,7 +63,7 @@
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
 from gem5.coherence_protocol import CoherenceProtocol
-from gem5.resources.resource import Resource, CustomResource
+from gem5.resources.resource import Resource, CustomDiskImageResource

 from m5.stats.gem5stats import get_simstat
 from m5.util import warn
@@ -236,12 +236,6 @@
 # For enabling CustomResource, we pass an additional parameter to mount the
 # correct partition.

-metadata = {
-"additional_metadata" : {
-"root_partition" : args.partition,
-},
-}
-
 board.set_kernel_disk_workload(
 # The x86 linux kernel will be automatically downloaded to the
 # `~/.cache/gem5` directory if not already present.
@@ -250,10 +244,10 @@
 "x86-linux-kernel-4.19.83",
 ),
 # The location of the x86 SPEC CPU 2017 image
-disk_image=CustomResource(
+disk_image=CustomDiskImageResource(
 args.image,
-metadata=metadata
-),
+disk_root_partition=args.partition,
+),
 readfile_contents=command,
 )

diff --git a/src/python/gem5/resources/resource.py  
b/src/python/gem5/resources/resource.py

index b316f7d..f03490b 100644
--- a/src/python/gem5/resources/resource.py
+++ b/src/python/gem5/resources/resource.py
@@ -80,6 +80,36 @@
 """
 super().__init__(local_path=local_path, metadata=metadata)

+class CustomDiskImageResource(CustomResource):
+"""
+A custom disk image gem5 resource. It can be used to specify a custom,
+local disk image.
+"""
+
+def __init__(
+self,
+local_path: str,
+disk_root_partition: Optional[str] = None,
+metadata: Dict = {},
+):
+"""
+:param local_path: The path of the disk image on the host system.
+:param disk_root_partition: The root disk partition to use.
+:param metadata: Metadata for the resource.
+"""
+
+# Behind the scenes, we set the the root partition via the  
metadata.
+# For a traditional, non-custom, resource it is the metadata that  
is
+# used to specify the disk image partition root. Therefore, when  
the
+# root disk partition specified during the 

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Fix CustomResource metadata

[Bobby Bruce (Gerrit) via gem5-dev]

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53843 )


Change subject: stdlib: Fix CustomResource metadata
..

stdlib: Fix CustomResource metadata

CustomResource's base class, AbstractResource, must be constructed with
a dictionary for the 'metadata' field. However, if the user did not
specify any metadata for the CustomResource, None is passed. This is
not permitted and can cause error. This patch ensures the metadata is
set to an empty dictionary by default

Change-Id: I358725ee6982dc9c6410eac3ad8194fa676dd326
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53843
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/python/gem5/resources/resource.py
1 file changed, 20 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/resources/resource.py  
b/src/python/gem5/resources/resource.py

index 0b9b128..b316f7d 100644
--- a/src/python/gem5/resources/resource.py
+++ b/src/python/gem5/resources/resource.py
@@ -73,7 +73,7 @@
 repository.
 """

-def __init__(self, local_path: str, metadata: Optional[Dict] = None):
+def __init__(self, local_path: str, metadata: Dict = {}):
 """
 :param local_path: The path of the resource on the host system.
 :param metadata: Add metadata for the custom resource.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I358725ee6982dc9c6410eac3ad8194fa676dd326
Gerrit-Change-Number: 53843
Gerrit-PatchSet: 3
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add partial param to TlbEntry

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52123 )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Add partial param to TlbEntry
..

arch-arm: Add partial param to TlbEntry

The boolean will flag a partial translation

JIRA: https://gem5.atlassian.net/browse/GEM5-1108

Change-Id: Ia27e321cd5c4b062cafcfd0dc39a208a4d5e3247
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52123
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Jason Lowe-Power 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/arm/pagetable.hh
1 file changed, 24 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/pagetable.hh b/src/arch/arm/pagetable.hh
index 4cfdf2a..8300175 100644
--- a/src/arch/arm/pagetable.hh
+++ b/src/arch/arm/pagetable.hh
@@ -244,6 +244,8 @@
 // This is used to distinguish between instruction and data entries
 // in unified TLBs
 TypeTLB type;
+// True if the entry is caching a partial translation (a table walk)
+bool partial;

 // Type of memory
 bool nonCacheable; // Can we wrap this in mtype?
@@ -266,6 +268,7 @@
  domain(DomainType::Client),  mtype(MemoryType::StronglyOrdered),
  longDescFormat(false), isHyp(false), global(false), valid(true),
  ns(true), nstid(true), el(EL0), type(TypeTLB::unified),
+ partial(false),
  nonCacheable(uncacheable),
  shareable(false), outerShareable(false), xn(0), pxn(0)
 {
@@ -283,7 +286,7 @@
  domain(DomainType::Client), mtype(MemoryType::StronglyOrdered),
  longDescFormat(false), isHyp(false), global(false), valid(false),
  ns(true), nstid(true), el(EL0), type(TypeTLB::unified),
- nonCacheable(false),
+ partial(false), nonCacheable(false),
  shareable(false), outerShareable(false), xn(0), pxn(0)
 {
 // no restrictions by default, hap = 0x3

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia27e321cd5c4b062cafcfd0dc39a208a4d5e3247
Gerrit-Change-Number: 52123
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python: Add simulator instantiation checks

[Andreas Sandberg (Gerrit) via gem5-dev]

Andreas Sandberg has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53923 )



Change subject: python: Add simulator instantiation checks
..

python: Add simulator instantiation checks

Check that m5.instantiate() has been called before m5.simulate() and
that m5.instantiate() is only called once.

Change-Id: Iced129cfd3d09564e2ef619eba829fd294c8a6ac
Signed-off-by: Andreas Sandberg 
---
M src/python/m5/simulate.py
1 file changed, 27 insertions(+), 2 deletions(-)



diff --git a/src/python/m5/simulate.py b/src/python/m5/simulate.py
index b5b8c78..0e222cf 100644
--- a/src/python/m5/simulate.py
+++ b/src/python/m5/simulate.py
@@ -62,11 +62,19 @@

 _drain_manager = _m5.drain.DrainManager.instance()

-# The final hook to generate .ini files.  Called from the user script
-# once the config is built.
+_instantiated = False # Has m5.instantiate() been called?
+
+# The final call to instantiate the SimObject graph and initialize the
+# system.
 def instantiate(ckpt_dir=None):
+global _instantiated
 from m5 import options

+if _instantiated:
+fatal("m5.instantiate() called twice.")
+
+_instantiated = True
+
 root = objects.Root.getInstance()

 if not root:
@@ -148,6 +156,10 @@
 need_startup = True
 def simulate(*args, **kwargs):
 global need_startup
+global _instantiated
+
+if not _instantiated:
+fatal("m5.instantiate() must be called before m5.simulate().")

 if need_startup:
 root = objects.Root.getInstance()

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iced129cfd3d09564e2ef619eba829fd294c8a6ac
Gerrit-Change-Number: 53923
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg 
Gerrit-MessageType: newchange
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