[gem5-dev] Change in gem5/gem5[develop]: stdlib: Remove final decorator from abstract board
Hoa Nguyen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/55863 ) Change subject: stdlib: Remove final decorator from abstract board .. stdlib: Remove final decorator from abstract board @typing.final was not introduced until python3.8. Change-Id: I65a5f4b5655d2ad80f7b566f9cea8e2371b3be62 Signed-off-by: Hoa Nguyen --- M src/python/gem5/components/boards/abstract_board.py 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/src/python/gem5/components/boards/abstract_board.py b/src/python/gem5/components/boards/abstract_board.py index a27cecd..30fbfca 100644 --- a/src/python/gem5/components/boards/abstract_board.py +++ b/src/python/gem5/components/boards/abstract_board.py @@ -37,7 +37,7 @@ VoltageDomain, ) -from typing import List, final +from typing import List class AbstractBoard(System): @@ -236,7 +236,6 @@ """ raise NotImplementedError -@final def _connect_things(self) -> None: """Connects all the components to the board. -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/55863 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I65a5f4b5655d2ad80f7b566f9cea8e2371b3be62 Gerrit-Change-Number: 55863 Gerrit-PatchSet: 1 Gerrit-Owner: Hoa Nguyen Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Ensure moving to %cs faults even in real mode.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55825 )
Change subject: arch-x86: Ensure moving to %cs faults even in real mode.
..
arch-x86: Ensure moving to %cs faults even in real mode.
It's always illegal to try to use the "mov" instruction to move a
selector into %cs. That was implemented for normal mov-s, but not for
the real mode version.
Change-Id: Ida8ec323fd7428ece583ad01cd5095d5f9630c9d
---
M src/arch/x86/isa/decoder/one_byte_opcodes.isa
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index 878dab2..104d205 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -293,13 +293,18 @@
}
0x5: LEA(Gv,M);
0x6: decode MODE_SUBMODE {
-0x3, 0x4: MOV_REAL(Sv,Ev);
+0x3, 0x4: decode MODRM_REG {
+// Moving to the CS selector (0x1) is illegal, and 0x6
and
+// 0x7 are reserved.
+0x1, 0x6, 0x7: UD2();
+default: MOV_REAL(Sv,Ev);
+}
default: decode MODRM_REG {
-0x1: UD2(); // Moving to the CS selector is illegal.
+// Moving to the CS selector (0x1) is illegal, and 0x6
and
+// 0x7 are reserved.
+0x1, 0x6, 0x7: UD2();
0x2: MOVSS(Sv,Ev);
-0x0, 0x3,
-0x4, 0x5: MOV(Sv,Ev);
-default: UD2();
+default: MOV(Sv,Ev);
}
}
//0x7: group10_Ev();
--
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fix the SAHF and LAHF instructions.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55824 )
Change subject: arch-x86: Fix the SAHF and LAHF instructions.
..
arch-x86: Fix the SAHF and LAHF instructions.
These had been transposed with each other, and had other problems having
to do with data truncation and old bits leaking through into other
registers.
Change-Id: Ib46eaa201d4b8273a683ebcb0060e8d49c447d96
---
M src/arch/x86/isa/insts/general_purpose/flags/load_and_store.py
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/src/arch/x86/isa/insts/general_purpose/flags/load_and_store.py
b/src/arch/x86/isa/insts/general_purpose/flags/load_and_store.py
index 76f81c1..31723b3 100644
--- a/src/arch/x86/isa/insts/general_purpose/flags/load_and_store.py
+++ b/src/arch/x86/isa/insts/general_purpose/flags/load_and_store.py
@@ -35,10 +35,13 @@
microcode = '''
def macroop SAHF {
-ruflags ah, dataSize=1
+ruflags t1, dataSize=8
+mov t1, t1, ah, dataSize=1
+wruflags t1, t0, dataSize=8
};
def macroop LAHF {
-wruflags ah, t0, dataSize=1
+rflags t1, dataSize=8
+andi ah, t1, "CFBit | PFBit | AFBit | ZFBit | SFBit | (1 << 1)",
dataSize=1
};
'''
--
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Gerrit-Change-Id: Ib46eaa201d4b8273a683ebcb0060e8d49c447d96
Gerrit-Change-Number: 55824
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Make the flags microops handle reserved bits better.
Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/55823 ) Change subject: arch-x86: Make the flags microops handle reserved bits better. .. arch-x86: Make the flags microops handle reserved bits better. These microops should report bits which are RAZ as zero and RAO as one, and not let those bits get overwritten with anything else. Change-Id: I8e867b311b485234ac457bf58fad1673892dfa6a --- M src/arch/x86/isa/microops/regop.isa 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index d56e17c..556a02c 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -1177,18 +1177,21 @@ class Wrflags(WrRegOp): code = ''' -RegVal newFlags = PSrcReg1 ^ op2; -RegVal userFlagMask = 0xDD5; +const RegVal new_flags = PSrcReg1 ^ op2; // Get only the user flags -ccFlagBits = newFlags & ccFlagMask; -dfBit = newFlags & DFBit; -cfofBits = newFlags & cfofMask; +ccFlagBits = new_flags & ccFlagMask; +dfBit = new_flags & DFBit; +cfofBits = new_flags & cfofMask; ecfBit = 0; ezfBit = 0; // Get everything else -nccFlagBits = newFlags & ~userFlagMask; +const RegVal IOPLMask = mask(2) << 12; +const RegVal SysFlagMask = +TFBit | IFBit | IOPLMask | NTBit | RFBit | VMBit | +ACBit | VIFBit | VIPBit | IDBit; +nccFlagBits = new_flags & SysFlagMask; ''' class Rdip(RdRegOp): @@ -1200,7 +1203,7 @@ class Rflags(RdRegOp): code = ''' DestReg = ccFlagBits | cfofBits | dfBit | - ecfBit | ezfBit | nccFlagBits; + ecfBit | ezfBit | nccFlagBits | (1 << 1); ''' class Ruflag(RegOp): -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/55823 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I8e867b311b485234ac457bf58fad1673892dfa6a Gerrit-Change-Number: 55823 Gerrit-PatchSet: 1 Gerrit-Owner: Gabe Black Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Specialize some instructions for virtual 8086 mode.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55809 )
Change subject: arch-x86: Specialize some instructions for virtual 8086
mode.
..
arch-x86: Specialize some instructions for virtual 8086 mode.
Some instructions behave in special ways in virtual 8086 mode. In some
cases, that means that they behave like they do in real mode, even
though the CPU has protected mode enabled. In other cases, it means that
there are extra checks, or even very different behaviors, which help
virtualize the system for the 8086 programs.
Change-Id: I70723b38ea0a7625c4a557bf4dd8f044e5715172
---
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
M src/arch/x86/isa/decoder/one_byte_opcodes.isa
M src/arch/x86/isa/insts/general_purpose/flags/set_and_clear.py
M src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
M src/arch/x86/isa/insts/general_purpose/flags/push_and_pop.py
M src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
7 files changed, 156 insertions(+), 28 deletions(-)
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index 152f6e4..878dab2 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -47,7 +47,7 @@
}
0x7: decode MODE_SUBMODE {
0x0: UD2();
-0x4: POP_REAL(sEv);
+0x3, 0x4: POP_REAL(sEv);
default: WarnUnimpl::pop_ES();
}
default: MultiInst::ADD(OPCODE_OP_BOTTOM3,
@@ -75,7 +75,7 @@
}
0x7: decode MODE_SUBMODE {
0x0: UD2();
-0x4: POP_REAL(sSv);
+0x3, 0x4: POP_REAL(sSv);
default: WarnUnimpl::pop_SS();
}
default: MultiInst::ADC(OPCODE_OP_BOTTOM3,
@@ -90,7 +90,7 @@
}
0x7: decode MODE_SUBMODE {
0x0: UD2();
-0x4: POP_REAL(sDv);
+0x3, 0x4: POP_REAL(sDv);
default: WarnUnimpl::pop_DS();
}
default: MultiInst::SBB(OPCODE_OP_BOTTOM3,
@@ -192,10 +192,22 @@
0x1: IMUL(Gv,Ev,Iz);
0x2: PUSH(Ib);
0x3: IMUL(Gv,Ev,Ib);
-0x4: StringInst::INS(Yb,rD);
-0x5: StringInst::INS(Yz,rD);
-0x6: StringInst::OUTS(rD,Xb);
-0x7: StringInst::OUTS(rD,Xz);
+0x4: decode MODE_SUBMODE {
+0x3: StringInst::INS_VIRT(Yb,rD);
+default: StringInst::INS(Yb,rD);
+}
+0x5: decode MODE_SUBMODE {
+0x3: StringInst::INS(Yz,rD);
+default: StringInst::INS(Yz,rD);
+}
+0x6: decode MODE_SUBMODE {
+0x3: StringInst::OUTS(rD,Xb);
+default: StringInst::OUTS(rD,Xb);
+}
+0x7: decode MODE_SUBMODE {
+0x3: StringInst::OUTS(rD,Xz);
+default: StringInst::OUTS(rD,Xz);
+}
}
0x0E: decode OPCODE_OP_BOTTOM3 {
0x0: JO(Jb);
@@ -305,12 +317,18 @@
0x1: CQO(rAv,rDv);
0x2: decode MODE_SUBMODE {
0x0: UD2();
-0x4: CALL_FAR_REAL(Iz);
+0x3, 0x4: CALL_FAR_REAL(Iz);
default: WarnUnimpl::call_far_Ap();
}
0x3: WarnUnimpl::fwait(); //aka wait
-0x4: PUSHF();
-0x5: POPF();
+0x4: decode MODE_SUBMODE {
+0x3: PUSHF_VIRT();
+default: PUSHF();
+}
+0x5: decode MODE_SUBMODE {
+0x3: POPF_VIRT();
+default: POPF();
+}
//The 64 bit versions of both of these should be illegal only
//if CPUID says it isn't supported. For now, we'll just assume
//that it's supported.
@@ -366,12 +384,12 @@
0x3: RET_NEAR();
0x4: decode MODE_SUBMODE {
0x0: UD2();
-0x4: LES_REAL(Gz,Mz);
+0x3, 0x4: LES_REAL(Gz,Mz);
default: WarnUnimpl::les_Gz_Mp();
}
0x5: decode MODE_SUBMODE {
0x0: UD2();
-0x4: LDS_REAL(Gz,Mz);
+0x3, 0x4: LDS_REAL(Gz,Mz);
default: WarnUnimpl::lds_Gz_Mp();
}
//0x6: group12_Eb_Ib();
@@ -400,7 +418,11 @@
0x3, 0x4: Inst::RET_FAR_REAL();
default: Inst::RET_FAR();
}
-0x4: Inst::INT3();
+0x4: decode MODE_SUBMODE {
+0x4: Inst::INT3_REAL();
+0x3: Inst::INT3_VIRT();
+
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Use the right bits in the page table walker.
Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/55812 ) Change subject: arch-x86: Use the right bits in the page table walker. .. arch-x86: Use the right bits in the page table walker. In the section of the page table walker which processes a non-PAE, non-PSE page directory entry, use the right bits of the virtual address to figure out what to load next. Change-Id: I7be3339c24253aa5594f564087eb9a234c370325 --- M src/arch/x86/pagetable_walker.cc 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/pagetable_walker.cc b/src/arch/x86/pagetable_walker.cc index 6c22858..0aa9e75 100644 --- a/src/arch/x86/pagetable_walker.cc +++ b/src/arch/x86/pagetable_walker.cc @@ -476,7 +476,7 @@ } // 4 KB page entry.logBytes = 12; -nextRead = mbits(pte, 31, 12) + vaddr.norml2 * dataSize; +nextRead = mbits(pte, 31, 12) + vaddr.norml1 * dataSize; nextState = PTE; break; case PTE: -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/55812 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I7be3339c24253aa5594f564087eb9a234c370325 Gerrit-Change-Number: 55812 Gerrit-PatchSet: 1 Gerrit-Owner: Gabe Black Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Tidy up the page table walker stepWalk method.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55811 )
Change subject: arch-x86: Tidy up the page table walker stepWalk method.
..
arch-x86: Tidy up the page table walker stepWalk method.
Use the mbits function to avoid ugly manual masking and shifting. Also
remove some unnecessary casts when DPRINTF-ing PTEs.
Change-Id: I1cf7307760b2534e90bea1276110ecb005ec6471
---
M src/arch/x86/pagetable_walker.cc
1 file changed, 41 insertions(+), 39 deletions(-)
diff --git a/src/arch/x86/pagetable_walker.cc
b/src/arch/x86/pagetable_walker.cc
index 12a6c5e..6c22858 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -298,9 +298,8 @@
bool badNX = pte.nx && mode == BaseMMU::Execute && enableNX;
switch(state) {
case LongPML4:
-DPRINTF(PageTableWalker,
-"Got long mode PML4 entry %#016x.\n", (uint64_t)pte);
-nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl3 *
dataSize;
+DPRINTF(PageTableWalker, "Got long mode PML4 entry %#016x.\n",
pte);
+nextRead = mbits(pte, 51, 12) + vaddr.longl3 * dataSize;
doWrite = !pte.a;
pte.a = 1;
entry.writable = pte.w;
@@ -314,9 +313,8 @@
nextState = LongPDP;
break;
case LongPDP:
-DPRINTF(PageTableWalker,
-"Got long mode PDP entry %#016x.\n", (uint64_t)pte);
-nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl2 *
dataSize;
+DPRINTF(PageTableWalker, "Got long mode PDP entry %#016x.\n", pte);
+nextRead = mbits(pte, 51, 12) + vaddr.longl2 * dataSize;
doWrite = !pte.a;
pte.a = 1;
entry.writable = entry.writable && pte.w;
@@ -329,8 +327,7 @@
nextState = LongPD;
break;
case LongPD:
-DPRINTF(PageTableWalker,
-"Got long mode PD entry %#016x.\n", (uint64_t)pte);
+DPRINTF(PageTableWalker, "Got long mode PD entry %#016x.\n", pte);
doWrite = !pte.a;
pte.a = 1;
entry.writable = entry.writable && pte.w;
@@ -343,25 +340,23 @@
if (!pte.ps) {
// 4 KB page
entry.logBytes = 12;
-nextRead =
-((uint64_t)pte & (mask(40) << 12)) + vaddr.longl1 *
dataSize;
+nextRead = mbits(pte, 51, 12) + vaddr.longl1 * dataSize;
nextState = LongPTE;
break;
} else {
// 2 MB page
entry.logBytes = 21;
-entry.paddr = (uint64_t)pte & (mask(31) << 21);
+entry.paddr = mbits(pte, 51, 21);
entry.uncacheable = uncacheable;
entry.global = pte.g;
entry.patBit = bits(pte, 12);
-entry.vaddr = entry.vaddr & ~((2 * (1 << 20)) - 1);
+entry.vaddr = mbits(entry.vaddr, 63, 21);
doTLBInsert = true;
doEndWalk = true;
break;
}
case LongPTE:
-DPRINTF(PageTableWalker,
-"Got long mode PTE entry %#016x.\n", (uint64_t)pte);
+DPRINTF(PageTableWalker, "Got long mode PTE entry %#016x.\n", pte);
doWrite = !pte.a;
pte.a = 1;
entry.writable = entry.writable && pte.w;
@@ -371,18 +366,18 @@
fault = pageFault(pte.p);
break;
}
-entry.paddr = (uint64_t)pte & (mask(40) << 12);
+entry.paddr = mbits(pte, 51, 12);
entry.uncacheable = uncacheable;
entry.global = pte.g;
entry.patBit = bits(pte, 12);
-entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1);
+entry.vaddr = mbits(entry.vaddr, 63, 12);
doTLBInsert = true;
doEndWalk = true;
break;
case PAEPDP:
DPRINTF(PageTableWalker,
-"Got legacy mode PAE PDP entry %#08x.\n", (uint32_t)pte);
-nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.pael2 *
dataSize;
+"Got legacy mode PAE PDP entry %#08x.\n", pte);
+nextRead = mbits(pte, 51, 12) + vaddr.pael2 * dataSize;
if (!pte.p) {
doEndWalk = true;
fault = pageFault(pte.p);
@@ -391,8 +386,7 @@
nextState = PAEPD;
break;
case PAEPD:
-DPRINTF(PageTableWalker,
-"Got legacy mode PAE PD entry %#08x.\n", (uint32_t)pte);
+DPRINTF(PageTableWalker, "Got legacy mode PAE PD entry %#08x.\n",
pte);
doWrite = !pte.a;
pte.a = 1;
entry.writable = pte.w;
@@ -405,24 +399,24 @@
if (!pte.ps) {
// 4 KB page
entry.logBytes = 12;
-nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.pael1 *
dataSize;
+nextRead = mbits(pte, 51, 12) + vaddr.pael1 * dataSize;
nextState = PAEPTE;
break;
} else {
// 2 MB
[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fix writing back 32 bit PTEs in the walker.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55808 )
Change subject: arch-x86: Fix writing back 32 bit PTEs in the walker.
..
arch-x86: Fix writing back 32 bit PTEs in the walker.
The page table walker might need to write back page table entries to set
their accessed bits. It was already checking whether the access was 32
or 64 bit when the PTE was retrieved from the incoming packet, but was
not checking the size when it was written back out, causing an assert to
fail when working with 32 bit legacy PTEs.
Change-Id: I7d02241cad20681e6cac0111edf2454335c466fa
---
M src/arch/x86/pagetable_walker.cc
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/src/arch/x86/pagetable_walker.cc
b/src/arch/x86/pagetable_walker.cc
index cf84d17..12a6c5e 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -529,7 +529,10 @@
// value back to memory.
if (doWrite) {
write = oldRead;
-write->setLE(pte);
+if (dataSize == 8)
+write->setLE(pte);
+else
+write->setLE(pte);
write->cmd = MemCmd::WriteReq;
} else {
write = NULL;
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I7d02241cad20681e6cac0111edf2454335c466fa
Gerrit-Change-Number: 55808
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: dev,arch-x86: Fix a panic in the i8042 device.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55803 )
Change subject: dev,arch-x86: Fix a panic in the i8042 device.
..
dev,arch-x86: Fix a panic in the i8042 device.
The write case was copied and pasted from the read case but not fully
updated.
Change-Id: I07c281a2dfab8ef957729ae2ca897e0eb91b555c
---
M src/dev/x86/i8042.cc
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/src/dev/x86/i8042.cc b/src/dev/x86/i8042.cc
index 723affe..8bfbaec 100644
--- a/src/dev/x86/i8042.cc
+++ b/src/dev/x86/i8042.cc
@@ -200,8 +200,8 @@
"get byte %d.\n", data - ReadControllerRamBase);
} else if (data > WriteControllerRamBase &&
data < WriteControllerRamBase + RamSize) {
-panic("Attempted to use i8042 read controller RAM command to "
-"get byte %d.\n", data - ReadControllerRamBase);
+panic("Attempted to use i8042 write controller RAM command to "
+"get byte %d.\n", data - WriteControllerRamBase);
} else if (data >= PulseOutputBitBase &&
data < PulseOutputBitBase + NumOutputBits) {
panic("Attempted to use i8042 pulse output bit command to "
--
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[gem5-dev] Change in gem5/gem5[develop]: dev,arch-x86: Make the I8042 reset settings more realistic.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55805 )
Change subject: dev,arch-x86: Make the I8042 reset settings more realistic.
..
dev,arch-x86: Make the I8042 reset settings more realistic.
When powered on, the "passed self test" bit should not be set. It should
only be set once the I8042 has actually been told to do a self test.
Also the mouse and keyboard should be disabled. With them disabled their
interrupts won't matter, but we might as well leave those disabled as
well.
Change-Id: Ief1ab30365a0a8ea0a116e52c16dcccf441515ec
---
M src/dev/x86/i8042.cc
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/src/dev/x86/i8042.cc b/src/dev/x86/i8042.cc
index 7aed0ee..268d090 100644
--- a/src/dev/x86/i8042.cc
+++ b/src/dev/x86/i8042.cc
@@ -55,13 +55,11 @@
fatal_if(!mouse, "The i8042 model requires a mouse instance");
fatal_if(!keyboard, "The i8042 model requires a keyboard instance");
-statusReg.passedSelfTest = 1;
-statusReg.commandLast = 1;
statusReg.keyboardUnlocked = 1;
commandByte.convertScanCodes = 1;
-commandByte.passedSelfTest = 1;
-commandByte.keyboardFullInt = 1;
+commandByte.disableMouse = 1;
+commandByte.disableKeyboard = 1;
for (int i = 0; i < p.port_keyboard_int_pin_connection_count; i++) {
keyboardIntPin.push_back(new IntSourcePin(
--
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Detect when entering virtual 8086 mode.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55810 )
Change subject: arch-x86: Detect when entering virtual 8086 mode.
..
arch-x86: Detect when entering virtual 8086 mode.
If we're entering virtual 8086 mode, panic. Some aspects of that mode
may actually work, but since it's essentially untested, lets be extra
cautious.
Change-Id: I78bbfcb75db8370f4271c75caabc0ec53f75a884
---
M src/arch/x86/isa.cc
1 file changed, 19 insertions(+), 0 deletions(-)
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 89e0d29..2d7c4df 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -314,6 +314,12 @@
break;
case MISCREG_CR8:
break;
+ case MISCREG_RFLAGS:
+{
+RFLAGS rflags = val;
+panic_if(rflags.vm, "Virtual 8086 mode is not supported.");
+break;
+}
case MISCREG_CS_ATTR:
{
SegAttr toggled = regVal[miscReg] ^ val;
--
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Gerrit-Change-Number: 55810
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[gem5-dev] Change in gem5/gem5[develop]: dev,arch-x86: Change the i8042 to a normal PioDevice.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55804 )
Change subject: dev,arch-x86: Change the i8042 to a normal PioDevice.
..
dev,arch-x86: Change the i8042 to a normal PioDevice.
It was already acting like a normal PioDevice, but was inheriting from
BasicPioDevice and then disabling the additions that came with it.
Change-Id: I95791c200251c555ace6fe0c4297899877a94471
---
M src/dev/x86/I8042.py
M src/dev/x86/i8042.cc
M src/dev/x86/i8042.hh
3 files changed, 29 insertions(+), 21 deletions(-)
diff --git a/src/dev/x86/I8042.py b/src/dev/x86/I8042.py
index d2d9a17..956a1bf 100644
--- a/src/dev/x86/I8042.py
+++ b/src/dev/x86/I8042.py
@@ -26,17 +26,16 @@
from m5.params import *
from m5.proxy import *
-from m5.objects.Device import BasicPioDevice
+from m5.objects.Device import PioDevice
from m5.objects.IntPin import IntSourcePin
from m5.objects.PS2 import *
-class I8042(BasicPioDevice):
+class I8042(PioDevice):
type = 'I8042'
cxx_class = 'gem5::X86ISA::I8042'
cxx_header = "dev/x86/i8042.hh"
-# This isn't actually used for anything here.
-pio_addr = 0x0
+pio_latency = Param.Latency('100ns', "Programmed IO latency")
data_port = Param.Addr('Data port address')
command_port = Param.Addr('Command/status port address')
mouse_int_pin = IntSourcePin('Pin to signal the mouse has data')
diff --git a/src/dev/x86/i8042.cc b/src/dev/x86/i8042.cc
index 8bfbaec..7aed0ee 100644
--- a/src/dev/x86/i8042.cc
+++ b/src/dev/x86/i8042.cc
@@ -48,10 +48,8 @@
X86ISA::I8042::I8042(const Params &p)
-: BasicPioDevice(p, 0), // pioSize arg is dummy value... not used
- latency(p.pio_latency),
+: PioDevice(p), latency(p.pio_latency),
dataPort(p.data_port), commandPort(p.command_port),
- statusReg(0), commandByte(0), dataReg(0), lastCommand(NoCommand),
mouse(p.mouse), keyboard(p.keyboard)
{
fatal_if(!mouse, "The i8042 model requires a mouse instance");
@@ -80,7 +78,6 @@
X86ISA::I8042::getAddrRanges() const
{
AddrRangeList ranges;
-// TODO: Are these really supposed to be a single byte and not 4?
ranges.push_back(RangeSize(dataPort, 1));
ranges.push_back(RangeSize(commandPort, 1));
return ranges;
diff --git a/src/dev/x86/i8042.hh b/src/dev/x86/i8042.hh
index 4ab86ac..d6e464b 100644
--- a/src/dev/x86/i8042.hh
+++ b/src/dev/x86/i8042.hh
@@ -43,7 +43,7 @@
namespace X86ISA
{
-class I8042 : public BasicPioDevice
+class I8042 : public PioDevice
{
protected:
enum Command
@@ -98,25 +98,25 @@
Bitfield<0> keyboardFullInt;
EndBitUnion(CommandByte)
-Tick latency;
-Addr dataPort;
-Addr commandPort;
+Tick latency = 0;
+Addr dataPort = 0;
+Addr commandPort = 0;
-StatusReg statusReg;
-CommandByte commandByte;
+StatusReg statusReg = 0;
+CommandByte commandByte = 0;
-uint8_t dataReg;
+uint8_t dataReg = 0;
-static const uint16_t NoCommand = (uint16_t)(-1);
-uint16_t lastCommand;
+static inline const uint16_t NoCommand = (uint16_t)(-1);
+uint16_t lastCommand = NoCommand;
std::vector *> mouseIntPin;
std::vector *> keyboardIntPin;
-ps2::Device *mouse;
-ps2::Device *keyboard;
+ps2::Device *mouse = nullptr;
+ps2::Device *keyboard = nullptr;
-void writeData(uint8_t newData, bool mouse = false);
+void writeData(uint8_t newData, bool mouse=false);
uint8_t readDataOut();
public:
@@ -132,7 +132,7 @@
else if (if_name == "keyboard_int_pin")
return *keyboardIntPin.at(idx);
else
-return BasicPioDevice::getPort(if_name, idx);
+return PioDevice::getPort(if_name, idx);
}
AddrRangeList getAddrRanges() const override;
--
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[gem5-dev] Change in gem5/gem5[develop]: dev,arch-x86: Implement some self test 8042 commands.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55806 )
Change subject: dev,arch-x86: Implement some self test 8042 commands.
..
dev,arch-x86: Implement some self test 8042 commands.
The self test in particular is used by bare metal software to ensure
that the keyboard controller is reset and ready to use.
Change-Id: I53c2a80c181b9d19617c75657637e06951c94433
---
M src/dev/x86/i8042.cc
1 file changed, 30 insertions(+), 3 deletions(-)
diff --git a/src/dev/x86/i8042.cc b/src/dev/x86/i8042.cc
index 268d090..9fab694 100644
--- a/src/dev/x86/i8042.cc
+++ b/src/dev/x86/i8042.cc
@@ -226,11 +226,26 @@
commandByte.disableMouse = 0;
break;
case TestMouse:
-panic("i8042 \"Test mouse\" command not implemented.\n");
+// The response to this is from the 8042, not the mouse.
+// Hard code no errors detected.
+writeData(0x00);
+break;
case SelfTest:
-panic("i8042 \"Self test\" command not implemented.\n");
+// Exactly what this does is essentially undocumented, but
this:
+// https://www.os2museum.com/wp/
+// ibm-pcat-8042-keyboard-controller-commands/
+// says that this should essentially reset some values.
+commandByte.convertScanCodes = 1;
+commandByte.disableMouse = 1;
+commandByte.disableKeyboard = 1;
+commandByte.passedSelfTest = 1;
+statusReg.passedSelfTest = 1;
+writeData(0x55); // Self test passed.
+break;
case InterfaceTest:
-panic("i8042 \"Interface test\" command not implemented.\n");
+// Hard code no errors detected.
+writeData(0x00);
+break;
case DiagnosticDump:
panic("i8042 \"Diagnostic dump\" command not implemented.\n");
case DisableKeyboard:
--
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[gem5-dev] Change in gem5/gem5[develop]: dev: Implement PS/2 keyboard echo and set scan code commands.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55807 )
Change subject: dev: Implement PS/2 keyboard echo and set scan code
commands.
..
dev: Implement PS/2 keyboard echo and set scan code commands.
Don't actually let anyone set a scan code set other than 2, since that's
all our converter knows about. It's probably all anyone will want
anyway.
Change-Id: Ief2f35448adc80e30e8fdf13ef9d64d6f19447eb
---
M src/dev/ps2/keyboard.cc
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/src/dev/ps2/keyboard.cc b/src/dev/ps2/keyboard.cc
index fb63d48..e3b13ac 100644
--- a/src/dev/ps2/keyboard.cc
+++ b/src/dev/ps2/keyboard.cc
@@ -128,9 +128,26 @@
return true;
}
case keyboard::DiagnosticEcho:
-panic("Keyboard diagnostic echo unimplemented.\n");
+send(keyboard::DiagnosticEcho);
+return true;
case keyboard::AlternateScanCodes:
-panic("Accessing alternate scan codes unimplemented.\n");
+if (data.size() == 1) {
+DPRINTF(PS2, "Got scan code set command.\n");
+sendAck();
+return false;
+} else {
+sendAck();
+uint8_t scan_code = data[1];
+if (scan_code == 0) {
+DPRINTF(PS2, "Sending hard coded current scan code set
2.\n");
+send(0x2);
+} else {
+DPRINTF(PS2, "Setting scan code set to %d.\n", scan_code);
+panic_if(scan_code != 0x2,
+"PS/2 scan code set %d not supported.", scan_code);
+}
+}
+return true;
case keyboard::TypematicInfo:
if (data.size() == 1) {
DPRINTF(PS2, "Setting typematic info.\n");
--
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