[gem5-dev] Change in gem5/gem5[develop]: configs: Modify createAddrRanges to support NUMA configuration

[Daecheol You (Gerrit) via gem5-dev]

Daecheol You has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56610 )


Change subject: configs: Modify createAddrRanges to support NUMA  
configuration

..

configs: Modify createAddrRanges to support NUMA configuration

When system is configured for NUMA, it has multiple memory ranges,
and each memory range is mapped to a corresponding NUMA node.
For this, the change enables createAddrRanges to map address ranges to
only a given HNFs.

JIRA: https://gem5.atlassian.net/browse/GEM5-1187

Change-Id: If4a8f3ba9aac9f74125970f63410883d2ad32f01
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56610
Reviewed-by: Tiago Muck 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/ruby/CHI.py
M configs/ruby/CHI_config.py
2 files changed, 28 insertions(+), 9 deletions(-)

Approvals:
  Tiago Muck: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/ruby/CHI.py b/configs/ruby/CHI.py
index e4a2477..3fe8b26 100644
--- a/configs/ruby/CHI.py
+++ b/configs/ruby/CHI.py
@@ -156,8 +156,9 @@
 for m in other_memories:
 sysranges.append(m.range)

+hnf_list = [i for i in range(options.num_l3caches)]
 CHI_HNF.createAddrRanges(sysranges, system.cache_line_size.value,
- options.num_l3caches)
+ hnf_list)
 ruby_system.hnf = [ CHI_HNF(i, ruby_system, HNFCache, None)
 for i in range(options.num_l3caches) ]

diff --git a/configs/ruby/CHI_config.py b/configs/ruby/CHI_config.py
index 097f367..b596efa 100644
--- a/configs/ruby/CHI_config.py
+++ b/configs/ruby/CHI_config.py
@@ -486,15 +486,14 @@
 '''HNFs may also define the 'pairing' parameter to allow pairing'''
 pairing = None

-_addr_ranges = []
+_addr_ranges = {}
 @classmethod
-def createAddrRanges(cls, sys_mem_ranges, cache_line_size, num_hnfs):
+def createAddrRanges(cls, sys_mem_ranges, cache_line_size, hnfs):
 # Create the HNFs interleaved addr ranges
 block_size_bits = int(math.log(cache_line_size, 2))
-cls._addr_ranges = []
-llc_bits = int(math.log(num_hnfs, 2))
+llc_bits = int(math.log(len(hnfs), 2))
 numa_bit = block_size_bits + llc_bits - 1
-for i in range(num_hnfs):
+for i, hnf in enumerate(hnfs):
 ranges = []
 for r in sys_mem_ranges:
 addr_range = AddrRange(r.start, size = r.size(),
@@ -502,7 +501,7 @@
 intlvBits = llc_bits,
 intlvMatch = i)
 ranges.append(addr_range)
-cls._addr_ranges.append((ranges, numa_bit, i))
+cls._addr_ranges[hnf] = (ranges, numa_bit)

 @classmethod
 def getAddrRanges(cls, hnf_idx):
@@ -514,10 +513,9 @@
 def __init__(self, hnf_idx, ruby_system, llcache_type, parent):
 super(CHI_HNF, self).__init__(ruby_system)

-addr_ranges,intlvHighBit,intlvMatch = self.getAddrRanges(hnf_idx)
+addr_ranges,intlvHighBit = self.getAddrRanges(hnf_idx)
 # All ranges should have the same interleaving
 assert(len(addr_ranges) >= 1)
-assert(intlvMatch == hnf_idx)

 ll_cache = llcache_type(start_index_bit = intlvHighBit + 1)
 self._cntrl = CHI_HNFController(ruby_system, ll_cache, NULL,

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If4a8f3ba9aac9f74125970f63410883d2ad32f01
Gerrit-Change-Number: 56610
Gerrit-PatchSet: 6
Gerrit-Owner: Daecheol You 
Gerrit-Reviewer: Daecheol You 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Tiago Muck 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-cache: Fix unit inconsistencies in base cache stats

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56989 )


Change subject: mem-cache: Fix unit inconsistencies in base cache stats
..

mem-cache: Fix unit inconsistencies in base cache stats

Most latency stats are described to have Cycle unit in the comments.
However, most of them are calculated from Tick.

Also, the unit of `demandAvgMissLatency` is incorrect.

Change-Id: Ib1b9b7c6fa4404cecb3982b3799753df19774623
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56989
Reviewed-by: Daniel Carvalho 
Maintainer: Daniel Carvalho 
Tested-by: kokoro 
---
M src/mem/cache/base.cc
M src/mem/cache/base.hh
2 files changed, 36 insertions(+), 17 deletions(-)

Approvals:
  Daniel Carvalho: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 435684a..cf6c9fe 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -,10 +,10 @@
 ADD_STAT(overallMissRate, statistics::units::Ratio::get(),
  "miss rate for overall accesses"),
 ADD_STAT(demandAvgMissLatency, statistics::units::Rate<
-statistics::units::Cycle, statistics::units::Count>::get(),
- "average overall miss latency"),
+statistics::units::Tick, statistics::units::Count>::get(),
+ "average overall miss latency in ticks"),
 ADD_STAT(overallAvgMissLatency, statistics::units::Rate<
-statistics::units::Cycle, statistics::units::Count>::get(),
+statistics::units::Tick, statistics::units::Count>::get(),
  "average overall miss latency"),
 ADD_STAT(blockedCycles, statistics::units::Cycle::get(),
 "number of cycles access was blocked"),
@@ -2257,13 +2257,13 @@
 ADD_STAT(overallMshrMissRate, statistics::units::Ratio::get(),
  "mshr miss ratio for overall accesses"),
 ADD_STAT(demandAvgMshrMissLatency, statistics::units::Rate<
-statistics::units::Cycle, statistics::units::Count>::get(),
+statistics::units::Tick, statistics::units::Count>::get(),
  "average overall mshr miss latency"),
 ADD_STAT(overallAvgMshrMissLatency, statistics::units::Rate<
-statistics::units::Cycle, statistics::units::Count>::get(),
+statistics::units::Tick, statistics::units::Count>::get(),
  "average overall mshr miss latency"),
 ADD_STAT(overallAvgMshrUncacheableLatency, statistics::units::Rate<
-statistics::units::Cycle, statistics::units::Count>::get(),
+statistics::units::Tick, statistics::units::Count>::get(),
  "average overall mshr uncacheable latency"),
 ADD_STAT(replacements, statistics::units::Count::get(),
  "number of replacements"),
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 0dc64e1..6fc7628 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -1006,12 +1006,12 @@
 @sa Packet::Command */
 statistics::Vector misses;
 /**
- * Total number of cycles per thread/command spent waiting for a  
hit.
+ * Total number of ticks per thread/command spent waiting for a  
hit.

  * Used to calculate the average hit latency.
  */
 statistics::Vector hitLatency;
 /**
- * Total number of cycles per thread/command spent waiting for a  
miss.
+ * Total number of ticks per thread/command spent waiting for a  
miss.

  * Used to calculate the average miss latency.
  */
 statistics::Vector missLatency;
@@ -1027,9 +1027,9 @@
 statistics::Vector mshrMisses;
 /** Number of misses that miss in the MSHRs, per command and  
thread. */

 statistics::Vector mshrUncacheable;
-/** Total cycle latency of each MSHR miss, per command and thread.  
*/
+/** Total tick latency of each MSHR miss, per command and thread.  
*/

 statistics::Vector mshrMissLatency;
-/** Total cycle latency of each MSHR miss, per command and thread.  
*/
+/** Total tick latency of each MSHR miss, per command and thread.  
*/

 statistics::Vector mshrUncacheableLatency;
 /** The miss rate in the MSHRs pre command and thread. */
 statistics::Formula mshrMissRate;
@@ -1055,9 +1055,9 @@
 statistics::Formula demandHits;
 /** Number of hit for all accesses. */
 statistics::Formula overallHits;
-/** Total number of cycles spent waiting for demand hits. */
+/** Total number of ticks spent waiting for demand hits. */
 statistics::Formula demandHitLatency;
-/** Total number of cycles spent waiting for all hits. */
+/** Total number of ticks spent waiting for all hits. */