date:20220314

[gem5-dev] Change in gem5/gem5[develop]: mem: Add setter for RequestorID in request

2022-03-14 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57650 )



Change subject: mem: Add setter for RequestorID in request
..

mem: Add setter for RequestorID in request

This is more convenient than setVirt for changing the requestor ID. This
field is modified frequently in disjoint Ruby network topologies to
specify which Ruby network a request should be routed through.

Change-Id: If37d13207e3b2b5c62362bab9a0e1250c392be63
---
M src/mem/request.hh
1 file changed, 19 insertions(+), 0 deletions(-)



diff --git a/src/mem/request.hh b/src/mem/request.hh
index 2bd0adc..27d2f26 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -803,6 +803,12 @@
 return _requestorId;
 }

+void
+requestorId(RequestorID rid)
+{
+_requestorId = rid;
+}
+
 uint32_t
 taskId() const
 {

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If37d13207e3b2b5c62362bab9a0e1250c392be63
Gerrit-Change-Number: 57650
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Add methods to read GPU memory requestor ID

2022-03-14 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57651 )



Change subject: gpu-compute: Add methods to read GPU memory requestor ID
..

gpu-compute: Add methods to read GPU memory requestor ID

These methods are called from various places to override the requestor
ID of a request in order to determine which Ruby network a request
should be routed on.

Change-Id: Ic0270ddd7123f0457a13144e69ef9132204d4334
---
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/compute_unit.hh
M src/gpu-compute/gpu_command_processor.cc
M src/gpu-compute/gpu_command_processor.hh
M src/gpu-compute/shader.cc
M src/gpu-compute/shader.hh
6 files changed, 44 insertions(+), 0 deletions(-)



diff --git a/src/gpu-compute/compute_unit.cc  
b/src/gpu-compute/compute_unit.cc

index f3db81c..11802d2 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -2010,6 +2010,15 @@
 }

 /**
+ * Forward the VRAM requestor ID needed for device memory from shader.
+ */
+RequestorID
+ComputeUnit::vramRequestorId()
+{
+return shader->vramRequestorId();
+}
+
+/**
  * get the result of packets sent to the LDS when they return
  */
 bool
diff --git a/src/gpu-compute/compute_unit.hh  
b/src/gpu-compute/compute_unit.hh

index 10fd2f9..87ed541 100644
--- a/src/gpu-compute/compute_unit.hh
+++ b/src/gpu-compute/compute_unit.hh
@@ -458,6 +458,7 @@
 void updatePageDivergenceDist(Addr addr);

 RequestorID requestorId() { return _requestorId; }
+RequestorID vramRequestorId();

 bool isDone() const;
 bool isVectorAluIdle(uint32_t simdId) const;
diff --git a/src/gpu-compute/gpu_command_processor.cc  
b/src/gpu-compute/gpu_command_processor.cc

index 9499d47..0f74cb1 100644
--- a/src/gpu-compute/gpu_command_processor.cc
+++ b/src/gpu-compute/gpu_command_processor.cc
@@ -65,6 +65,15 @@
 return *hsaPP;
 }

+/**
+ * Forward the VRAM requestor ID needed for device memory from GPU device.
+ */
+RequestorID
+GPUCommandProcessor::vramRequestorId()
+{
+return gpuDevice->vramRequestorId();
+}
+
 TranslationGenPtr
 GPUCommandProcessor::translate(Addr vaddr, Addr size)
 {
diff --git a/src/gpu-compute/gpu_command_processor.hh  
b/src/gpu-compute/gpu_command_processor.hh

index 1bc19c7..ec163ed 100644
--- a/src/gpu-compute/gpu_command_processor.hh
+++ b/src/gpu-compute/gpu_command_processor.hh
@@ -76,6 +76,7 @@
 GPUCommandProcessor(const Params );

 HSAPacketProcessor& hsaPacketProc();
+RequestorID vramRequestorId();

 void setGPUDevice(AMDGPUDevice *gpu_device);
 void setShader(Shader *shader);
diff --git a/src/gpu-compute/shader.cc b/src/gpu-compute/shader.cc
index a4e72b3..ebacbb5 100644
--- a/src/gpu-compute/shader.cc
+++ b/src/gpu-compute/shader.cc
@@ -523,6 +523,15 @@
 stats.shaderActiveTicks += curTick() - _lastInactiveTick;
 }

+/**
+ * Forward the VRAM requestor ID needed for device memory from CP.
+ */
+RequestorID
+Shader::vramRequestorId()
+{
+return gpuCmdProc.vramRequestorId();
+}
+
 Shader::ShaderStats::ShaderStats(statistics::Group *parent, int wf_size)
 : statistics::Group(parent),
   ADD_STAT(allLatencyDist, "delay distribution for all"),
diff --git a/src/gpu-compute/shader.hh b/src/gpu-compute/shader.hh
index 0ea8741..96ad15d 100644
--- a/src/gpu-compute/shader.hh
+++ b/src/gpu-compute/shader.hh
@@ -183,6 +183,8 @@
 shHiddenPrivateBaseVmid = sh_hidden_base_new;
 }

+RequestorID vramRequestorId();
+
 EventFunctionWrapper tickEvent;

 // is this simulation going to be timing mode in the memory?

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic0270ddd7123f0457a13144e69ef9132204d4334
Gerrit-Change-Number: 57651
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: configs: Add GPU TLBs for GPU full system

2022-03-14 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57649 )



Change subject: configs: Add GPU TLBs for GPU full system
..

configs: Add GPU TLBs for GPU full system

Add the constructors for the Vega TLB and TLB coalescers in the python
config. These need a pointer to the gpu device which is added as a
parameter. The last level TLB's page table walker is added as a dma
device to the system so that the port is connected to the GPU device
memory in the disjoint VIPER configuration file.

A portion of the the GPUFS system configuration file needs to be
shuffled around so that the shader CPU is created before the TLBs are
created so they can be connected to the shader's ports. This means the
real CPU init code needs to break once reaching the shader. The vendor
string must also be set after createThreads is called on real CPUs.

Change-Id: I36ed93db262b21427f3eaf4904a1c897a2894835
---
M configs/common/GPUTLBConfig.py
M configs/example/gpufs/system/system.py
2 files changed, 96 insertions(+), 32 deletions(-)



diff --git a/configs/common/GPUTLBConfig.py b/configs/common/GPUTLBConfig.py
index f6aaccf..0f67de0 100644
--- a/configs/common/GPUTLBConfig.py
+++ b/configs/common/GPUTLBConfig.py
@@ -34,41 +34,66 @@
 import m5
 from m5.objects import *

-def TLB_constructor(level):
+def TLB_constructor(options, level, gpu_ctrl=None):

-constructor_call = "X86GPUTLB(size = options.L%(level)dTLBentries, \
-assoc = options.L%(level)dTLBassoc, \
-hitLatency = options.L%(level)dAccessLatency,\
-missLatency2 = options.L%(level)dMissLatency,\
-maxOutstandingReqs = options.L%(level)dMaxOutstandingReqs,\
-accessDistance = options.L%(level)dAccessDistanceStat,\
-clk_domain = SrcClockDomain(\
-clock = options.gpu_clock,\
-voltage_domain = VoltageDomain(\
-voltage = options.gpu_voltage)))" % locals()
-return constructor_call
-
-def Coalescer_constructor(level):
-
-constructor_call = "TLBCoalescer(probesPerCycle = \
-options.L%(level)dProbesPerCycle, \
-coalescingWindow = options.L%(level)dCoalescingWindow,\
-disableCoalescing = options.L%(level)dDisableCoalescing,\
+if options.full_system:
+constructor_call = "VegaGPUTLB(\
+gpu_device = gpu_ctrl, \
+size = options.L%(level)dTLBentries, \
+assoc = options.L%(level)dTLBassoc, \
+hitLatency = options.L%(level)dAccessLatency,\
+missLatency1 = options.L%(level)dMissLatency,\
+missLatency2 = options.L%(level)dMissLatency,\
+maxOutstandingReqs = options.L%(level)dMaxOutstandingReqs,\
+clk_domain = SrcClockDomain(\
+clock = options.gpu_clock,\
+voltage_domain = VoltageDomain(\
+voltage = options.gpu_voltage)))" % locals()
+else:
+constructor_call = "X86GPUTLB(size = options.L%(level)dTLBentries,  
\

+assoc = options.L%(level)dTLBassoc, \
+hitLatency = options.L%(level)dAccessLatency,\
+missLatency2 = options.L%(level)dMissLatency,\
+maxOutstandingReqs = options.L%(level)dMaxOutstandingReqs,\
+accessDistance = options.L%(level)dAccessDistanceStat,\
 clk_domain = SrcClockDomain(\
 clock = options.gpu_clock,\
 voltage_domain = VoltageDomain(\
 voltage = options.gpu_voltage)))" % locals()
 return constructor_call

+def Coalescer_constructor(options, level):
+
+if options.full_system:
+constructor_call = "VegaTLBCoalescer(probesPerCycle = \
+options.L%(level)dProbesPerCycle, \
+tlb_level  = %(level)d ,\
+coalescingWindow = options.L%(level)dCoalescingWindow,\
+disableCoalescing = options.L%(level)dDisableCoalescing,\
+clk_domain = SrcClockDomain(\
+clock = options.gpu_clock,\
+voltage_domain = VoltageDomain(\
+voltage = options.gpu_voltage)))" % locals()
+else:
+constructor_call = "TLBCoalescer(probesPerCycle = \
+options.L%(level)dProbesPerCycle, \
+coalescingWindow = options.L%(level)dCoalescingWindow,\
+disableCoalescing = options.L%(level)dDisableCoalescing,\
+clk_domain = SrcClockDomain(\
+clock = options.gpu_clock,\
+voltage_domain = VoltageDomain(\
+voltage = options.gpu_voltage)))" % locals()
+return constructor_call
+
 def create_TLB_Coalescer(options, my_level, my_index, tlb_name,
-coalescer_name):
+coalescer_name, gpu_ctrl=None):
 # arguments: options,

[gem5-dev] Change in gem5/gem5[develop]: configs,gpu-compute: Support fetch from system pages

2022-03-14 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57652 )



Change subject: configs,gpu-compute: Support fetch from system pages
..

configs,gpu-compute: Support fetch from system pages

The amdgpu driver supports fetching instructions from pages which reside
in system memory rather than device memory. This changeset adds support
to do this by adding the system hub object added in a prior changeset to
the fetch unit and issues requests to the system hub if the system bit
in the memory page's PTE is set. Otherwise, the requestor ID is set to
be device memory and the request is routed through the Ruby network /
GPU caches to fetch the instructions.

Change-Id: Ib2fb47c589fdd5e544ab6493d7dbd8f2d9d7b0e8
---
M configs/example/gpufs/system/system.py
M src/gpu-compute/GPU.py
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/compute_unit.hh
M src/gpu-compute/fetch_unit.cc
M src/gpu-compute/fetch_unit.hh
M src/gpu-compute/shader.cc
M src/gpu-compute/shader.hh
8 files changed, 83 insertions(+), 3 deletions(-)



diff --git a/configs/example/gpufs/system/system.py  
b/configs/example/gpufs/system/system.py

index 81dbd2d..6bd9023 100644
--- a/configs/example/gpufs/system/system.py
+++ b/configs/example/gpufs/system/system.py
@@ -133,6 +133,10 @@
 gpu_mem_mgr = AMDGPUMemoryManager()
 system.pc.south_bridge.gpu.memory_manager = gpu_mem_mgr

+# CPU data path (SystemHub)
+system_hub = AMDGPUSystemHub()
+shader.system_hub = system_hub
+
 # GPU, HSAPP, and GPUCommandProc are DMA devices
 system._dma_ports.append(gpu_hsapp)
 system._dma_ports.append(gpu_cmd_proc)
@@ -141,6 +145,7 @@
 system._dma_ports.append(sdma1)
 system._dma_ports.append(device_ih)
 system._dma_ports.append(pm4_pkt_proc)
+system._dma_ports.append(system_hub)
 system._dma_ports.append(gpu_mem_mgr)
 system._dma_ports.append(hsapp_pt_walker)
 system._dma_ports.append(cp_pt_walker)
@@ -154,6 +159,7 @@
 sdma1.pio = system.iobus.mem_side_ports
 device_ih.pio = system.iobus.mem_side_ports
 pm4_pkt_proc.pio = system.iobus.mem_side_ports
+system_hub.pio = system.iobus.mem_side_ports

 # Full system needs special TLBs for SQC, Scalar, and vector data ports
 args.full_system = True
diff --git a/src/gpu-compute/GPU.py b/src/gpu-compute/GPU.py
index 3e5fba6..a0154a7 100644
--- a/src/gpu-compute/GPU.py
+++ b/src/gpu-compute/GPU.py
@@ -224,6 +224,7 @@
 CUs = VectorParam.ComputeUnit('Number of compute units')
 gpu_cmd_proc = Param.GPUCommandProcessor('Command processor for GPU')
 dispatcher = Param.GPUDispatcher('GPU workgroup dispatcher')
+system_hub = Param.AMDGPUSystemHub(NULL, 'GPU System Hub (FS Mode  
only)')

 n_wf = Param.Int(10, 'Number of wavefront slots per SIMD')
 impl_kern_launch_acq = Param.Bool(True, """Insert acq packet into
  ruby at kernel launch""")
diff --git a/src/gpu-compute/compute_unit.cc  
b/src/gpu-compute/compute_unit.cc

index 11802d2..b40b464 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -979,11 +979,18 @@
 bool
 ComputeUnit::SQCPort::recvTimingResp(PacketPtr pkt)
 {
-computeUnit->fetchStage.processFetchReturn(pkt);
+computeUnit->handleSQCReturn(pkt);
+
 return true;
 }

 void
+ComputeUnit::handleSQCReturn(PacketPtr pkt)
+{
+fetchStage.processFetchReturn(pkt);
+}
+
+void
 ComputeUnit::SQCPort::recvReqRetry()
 {
 int len = retries.size();
diff --git a/src/gpu-compute/compute_unit.hh  
b/src/gpu-compute/compute_unit.hh

index 87ed541..1c211d9 100644
--- a/src/gpu-compute/compute_unit.hh
+++ b/src/gpu-compute/compute_unit.hh
@@ -463,6 +463,8 @@
 bool isDone() const;
 bool isVectorAluIdle(uint32_t simdId) const;

+void handleSQCReturn(PacketPtr pkt);
+
   protected:
 RequestorID _requestorId;

diff --git a/src/gpu-compute/fetch_unit.cc b/src/gpu-compute/fetch_unit.cc
index 6e35818..640e29b 100644
--- a/src/gpu-compute/fetch_unit.cc
+++ b/src/gpu-compute/fetch_unit.cc
@@ -206,6 +206,15 @@

 computeUnit.sqcTLBPort.sendFunctional(pkt);

+/**
+ * For full system, if this is a device request we need to set the
+ * requestor ID of the packet to the GPU memory manager so it is  
routed

+ * through Ruby as a memory request and not a PIO request.
+ */
+if (!pkt->req->systemReq()) {
+pkt->req->requestorId(computeUnit.vramRequestorId());
+}
+
 GpuTranslationState *sender_state =
  safe_cast(pkt->senderState);

@@ -250,6 +259,15 @@
 }

 /**
+ * For full system, if this is a device request we need to set the
+ * requestor ID of the packet to the GPU memory manager so it is routed
+ * through Ruby as a memory request and not a PIO request.
+ */
+if (!pkt->req->systemReq()) {
+

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: CortexA76 fix missing registers for FastModel 11.17

2022-03-14 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57629 )



Change subject: fastmodel: CortexA76 fix missing registers for FastModel  
11.17

..

fastmodel: CortexA76 fix missing registers for FastModel 11.17

Change-Id: I1f6e2e92b91d0fe361a5ea88542a1e095a9f357b
---
M src/arch/arm/fastmodel/CortexA76/thread_context.cc
1 file changed, 60 insertions(+), 51 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc  
b/src/arch/arm/fastmodel/CortexA76/thread_context.cc

index ff82bbe..36c6458 100644
--- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
@@ -267,7 +267,7 @@
 { ArmISA::MISCREG_DBGOSLAR, "DBGOSLAR" },
 // ArmISA::MISCREG_DBGOSLSR?
 // ArmISA::MISCREG_DBGOSDLR?
-{ ArmISA::MISCREG_DBGPRCR, "DBGPRCR_EL1" }, //XXX verify
+// ArmISA::MISCREG_DBGPRCR?
 // ArmISA::MISCREG_DBGDSAR?
 { ArmISA::MISCREG_DBGCLAIMSET, "DBGCLAIMSET" },
 { ArmISA::MISCREG_DBGCLAIMCLR, "DBGCLAIMCLR" },
@@ -283,31 +283,31 @@

 // AArch32 CP15 registers (system control)
 { ArmISA::MISCREG_MIDR, "MIDR" },
-{ ArmISA::MISCREG_CTR, "CTR" },
-{ ArmISA::MISCREG_TCMTR, "TCMTR" },
-{ ArmISA::MISCREG_TLBTR, "TLBTR" },
-{ ArmISA::MISCREG_MPIDR, "MPIDR" },
-{ ArmISA::MISCREG_REVIDR, "REVIDR" },
-{ ArmISA::MISCREG_ID_PFR0, "ID_PFR0" },
-{ ArmISA::MISCREG_ID_PFR1, "ID_PFR1" },
-{ ArmISA::MISCREG_ID_DFR0, "ID_DFR0" },
-{ ArmISA::MISCREG_ID_AFR0, "ID_AFR0" },
-{ ArmISA::MISCREG_ID_MMFR0, "ID_MMFR0" },
-{ ArmISA::MISCREG_ID_MMFR1, "ID_MMFR1" },
-{ ArmISA::MISCREG_ID_MMFR2, "ID_MMFR2" },
-{ ArmISA::MISCREG_ID_MMFR3, "ID_MMFR3" },
-{ ArmISA::MISCREG_ID_MMFR4, "ID_MMFR4" },
-{ ArmISA::MISCREG_ID_ISAR0, "ID_ISAR0" },
-{ ArmISA::MISCREG_ID_ISAR1, "ID_ISAR1" },
-{ ArmISA::MISCREG_ID_ISAR2, "ID_ISAR2" },
-{ ArmISA::MISCREG_ID_ISAR3, "ID_ISAR3" },
-{ ArmISA::MISCREG_ID_ISAR4, "ID_ISAR4" },
-{ ArmISA::MISCREG_ID_ISAR5, "ID_ISAR5" },
-{ ArmISA::MISCREG_ID_ISAR6, "ID_ISAR6" },
-{ ArmISA::MISCREG_CCSIDR, "CCSIDR" },
-{ ArmISA::MISCREG_CLIDR, "CLIDR" },
-{ ArmISA::MISCREG_AIDR, "AIDR" },
-{ ArmISA::MISCREG_CSSELR, "CSSELR_EL1" }, //XXX verify
+// ArmISA::MISCREG_CTR?
+// ArmISA::MISCREG_TCMTR?
+// ArmISA::MISCREG_TLBTR?
+// ArmISA::MISCREG_MPIDR?
+// ArmISA::MISCREG_REVIDR?
+// ArmISA::MISCREG_ID_PFR0?
+// ArmISA::MISCREG_ID_PFR1?
+// ArmISA::MISCREG_ID_DFR0?
+// ArmISA::MISCREG_ID_AFR0?
+// ArmISA::MISCREG_ID_MMFR0?
+// ArmISA::MISCREG_ID_MMFR1?
+// ArmISA::MISCREG_ID_MMFR2?
+// ArmISA::MISCREG_ID_MMFR3?
+// ArmISA::MISCREG_ID_MMFR4?
+// ArmISA::MISCREG_ID_ISAR0?
+// ArmISA::MISCREG_ID_ISAR1?
+// ArmISA::MISCREG_ID_ISAR2?
+// ArmISA::MISCREG_ID_ISAR3?
+// ArmISA::MISCREG_ID_ISAR4?
+// ArmISA::MISCREG_ID_ISAR5?
+// ArmISA::MISCREG_ID_ISAR6?
+// ArmISA::MISCREG_CCSIDR?
+// ArmISA::MISCREG_CLIDR?
+// ArmISA::MISCREG_AIDR?
+// ArmISA::MISCREG_CSSELR?
 // ArmISA::MISCREG_CSSELR_NS?
 // ArmISA::MISCREG_CSSELR_S?
 // ArmISA::MISCREG_VPIDR?
@@ -327,7 +327,7 @@
 // ArmISA::MISCREG_HCR?
 // ArmISA::MISCREG_HDCR?
 // ArmISA::MISCREG_HCPTR?
-{ ArmISA::MISCREG_HSTR, "HSTR_EL2" }, //XXX verify
+// ArmISA::MISCREG_HSTR?
 // ArmISA::MISCREG_HACR?
 // ArmISA::MISCREG_TTBR0?
 // ArmISA::MISCREG_TTBR0_NS?
@@ -349,7 +349,7 @@
 // ArmISA::MISCREG_IFSR?
 // ArmISA::MISCREG_IFSR_NS?
 // ArmISA::MISCREG_IFSR_S?
-// { ArmISA::MISCREG_ADFSR, "ADFSR" },
+// ArmISA::MISCREG_ADFSR?
 // ArmISA::MISCREG_ADFSR_NS?
 // ArmISA::MISCREG_ADFSR_S?
 // ArmISA::MISCREG_AIFSR?
@@ -367,35 +367,35 @@
 // ArmISA::MISCREG_HDFAR?
 // ArmISA::MISCREG_HIFAR?
 // ArmISA::MISCREG_HPFAR?
-{ ArmISA::MISCREG_ICIALLUIS, "ICIALLUIS" },
+// ArmISA::MISCREG_ICIALLUIS?
 // ArmISA::MISCREG_BPIALLIS?
 // ArmISA::MISCREG_PAR?
 // ArmISA::MISCREG_PAR_NS?
 // ArmISA::MISCREG_PAR_S?
-{ ArmISA::MISCREG_ICIALLU, "ICIALLU" },
-{ ArmISA::MISCREG_ICIMVAU, "ICIMVAU" },
+// ArmISA::MISCREG_ICIALLU?
+// ArmISA::MISCREG_ICIMVAU?
 // ArmISA::MISCREG_CP15ISB?
 // ArmISA::MISCREG_BPIALL?
 // ArmISA::MISCREG_BPIMVA?
-{ ArmISA::MISCREG_DCIMVAC, "DCIMVAC" },
-{ ArmISA::MISCREG_DCISW, "DCISW" },
-{ ArmISA::MISCREG_ATS1CPR, "ATS1CPR" },
-{

[gem5-dev] Change in gem5/gem5[develop]: scons: Make all sticky variables automatically exported.

2022-03-14 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56891 )


 (

6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: scons: Make all sticky variables automatically exported.
..

scons: Make all sticky variables automatically exported.

All sticky vars are exported, but not all exported vars are sticky. The
vars which are exported but not sticky are (at least in general) found
with Configure() style measurement.

Change-Id: Idebf17e44c2eeca745cdfdd9f42eddcfdb0cf9ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56891
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Andreas Sandberg 
---
M src/SConscript
M src/arch/SConsopts
M src/arch/arm/fastmodel/SConsopts
M src/base/SConsopts
M src/cpu/kvm/SConsopts
M src/gpu-compute/SConsopts
M src/mem/ruby/SConsopts
M src/systemc/SConsopts
8 files changed, 25 insertions(+), 19 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/SConscript b/src/SConscript
index d3c5a5c..f905b1f 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -60,7 +60,11 @@
 # Children need to see the environment
 Export('env')

-build_env = [(opt, env[opt]) for opt in export_vars]
+all_export_vars = set()
+all_export_vars.update(export_vars)
+all_export_vars.update(sticky_vars.keys())
+
+build_env = [(opt, env[opt]) for opt in all_export_vars]

 from code_formatter import code_formatter

@@ -533,7 +537,7 @@
 build_dir = os.path.join(env['BUILDDIR'], root[prefix_len:])
 SConscript(os.path.join(root, 'SConscript'),  
variant_dir=build_dir)


-for opt in export_vars:
+for opt in all_export_vars:
 env.ConfigFile(opt)

 def makeTheISA(source, target, env):
diff --git a/src/arch/SConsopts b/src/arch/SConsopts
index 38b02f5..048814e 100644
--- a/src/arch/SConsopts
+++ b/src/arch/SConsopts
@@ -33,5 +33,3 @@
 sorted(set(main.Split('${ALL_GPU_ISAS}',
 )
 AfterSConsopts(add_isa_lists)
-
-export_vars.extend(['TARGET_ISA', 'TARGET_GPU_ISA'])
diff --git a/src/arch/arm/fastmodel/SConsopts  
b/src/arch/arm/fastmodel/SConsopts

index 74165fe..c7bfd84 100644
--- a/src/arch/arm/fastmodel/SConsopts
+++ b/src/arch/arm/fastmodel/SConsopts
@@ -45,9 +45,3 @@
  'The maximum number of ARM licenses to use concurrently', 1),
 ('SIMGEN', 'simgen executable', os.environ.get('SIMGEN',  
default_simgen)),

 )
-
-export_vars.extend([
-'ARMLMD_LICENSE_FILE',
-'PVLIB_HOME',
-'PVLIB_FLAVOR',
-])
diff --git a/src/base/SConsopts b/src/base/SConsopts
index 9fafd64..5c8d5f7 100644
--- a/src/base/SConsopts
+++ b/src/base/SConsopts
@@ -80,5 +80,4 @@


 export_vars.extend([
-'HAVE_FENV', 'HAVE_PNG', 'USE_POSIX_CLOCK', 'HAVE_VALGRIND',
-'HAVE_DEPRECATED_NAMESPACE'])
+'HAVE_FENV', 'HAVE_PNG', 'HAVE_VALGRIND', 'HAVE_DEPRECATED_NAMESPACE'])
diff --git a/src/cpu/kvm/SConsopts b/src/cpu/kvm/SConsopts
index be413e1..72f2a2e 100644
--- a/src/cpu/kvm/SConsopts
+++ b/src/cpu/kvm/SConsopts
@@ -76,7 +76,7 @@
 'Enable hardware virtualized (KVM) CPU models', True))
 else:
 main['USE_KVM'] = False
+export_vars.append('USE_KVM')
 warning("Can not enable KVM, host seems to lack KVM support")

-export_vars.append('USE_KVM')
 export_vars.append('KVM_ISA')
diff --git a/src/gpu-compute/SConsopts b/src/gpu-compute/SConsopts
index 1737c13..251ac5d 100644
--- a/src/gpu-compute/SConsopts
+++ b/src/gpu-compute/SConsopts
@@ -27,5 +27,3 @@

 sticky_vars.Add(BoolVariable('BUILD_GPU', 'Build the compute-GPU model',
  False))
-
-export_vars.append('BUILD_GPU')
diff --git a/src/mem/ruby/SConsopts b/src/mem/ruby/SConsopts
index 80713c4..f26b6d0 100644
--- a/src/mem/ruby/SConsopts
+++ b/src/mem/ruby/SConsopts
@@ -34,5 +34,3 @@

 sticky_vars.Add(('NUMBER_BITS_PER_SET', 'Max elements in set (default 64)',
  64))
-
-export_vars.extend(['PROTOCOL', 'NUMBER_BITS_PER_SET'])
diff --git a/src/systemc/SConsopts b/src/systemc/SConsopts
index 891431c..7f59955 100644
--- a/src/systemc/SConsopts
+++ b/src/systemc/SConsopts
@@ -46,5 +46,3 @@

 sticky_vars.Add(BoolVariable('USE_SYSTEMC', 'Enable SystemC API support',
  main.UseSystemcCheck()))
-
-export_vars.append('USE_SYSTEMC')

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idebf17e44c2eeca745cdfdd9f42eddcfdb0cf9ed
Gerrit-Change-Number: 56891
Gerrit-PatchSet: 8
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer:

[gem5-dev] Change in gem5/gem5[develop]: ext,scons: Make kconfiglib available for use in SCons.

2022-03-14 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56755 )


 (

8 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: ext,scons: Make kconfiglib available for use in SCons.
..

ext,scons: Make kconfiglib available for use in SCons.

Change-Id: Ie9c902819ed0750a04f8318911fa914701c2a0fe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56755
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Bobby Bruce 
---
A ext/Kconfiglib/.gitignore
A ext/Kconfiglib/LICENSE.txt
A ext/Kconfiglib/MANIFEST.in
A ext/Kconfiglib/README.rst
A ext/Kconfiglib/alldefconfig.py
A ext/Kconfiglib/allmodconfig.py
A ext/Kconfiglib/allnoconfig.py
A ext/Kconfiglib/allyesconfig.py
A ext/Kconfiglib/defconfig.py
A ext/Kconfiglib/examples/Kmenuconfig
A ext/Kconfiglib/examples/allnoconfig_walk.py
A ext/Kconfiglib/examples/defconfig_oldconfig.py
A ext/Kconfiglib/examples/dumpvars.py
A ext/Kconfiglib/examples/eval_expr.py
A ext/Kconfiglib/examples/find_symbol.py
A ext/Kconfiglib/examples/help_grep.py
A ext/Kconfiglib/examples/list_undefined.py
A ext/Kconfiglib/examples/menuconfig_example.py
A ext/Kconfiglib/examples/merge_config.py
A ext/Kconfiglib/examples/print_config_tree.py
A ext/Kconfiglib/examples/print_sym_info.py
A ext/Kconfiglib/examples/print_tree.py
A ext/Kconfiglib/gem5notes.txt
A ext/Kconfiglib/genconfig.py
A ext/Kconfiglib/guiconfig.py
A ext/Kconfiglib/import/kconfiglib.py
A ext/Kconfiglib/listnewconfig.py
A ext/Kconfiglib/makefile.patch
A ext/Kconfiglib/menuconfig.py
A ext/Kconfiglib/oldconfig.py
A ext/Kconfiglib/olddefconfig.py
A ext/Kconfiglib/savedefconfig.py
A ext/Kconfiglib/setconfig.py
A ext/Kconfiglib/setup.cfg
A ext/Kconfiglib/setup.py
A ext/Kconfiglib/tests/Kappend
A ext/Kconfiglib/tests/Kassignable
A ext/Kconfiglib/tests/Kchoice
A ext/Kconfiglib/tests/Kdefconfig_existent
A ext/Kconfiglib/tests/Kdefconfig_existent_but_n
A ext/Kconfiglib/tests/Kdefconfig_nonexistent
A ext/Kconfiglib/tests/Kdefconfig_srctree
A ext/Kconfiglib/tests/Kdepcopy
A ext/Kconfiglib/tests/Kdeploop0
A ext/Kconfiglib/tests/Kdeploop1
A ext/Kconfiglib/tests/Kdeploop10
A ext/Kconfiglib/tests/Kdeploop2
A ext/Kconfiglib/tests/Kdeploop3
A ext/Kconfiglib/tests/Kdeploop4
A ext/Kconfiglib/tests/Kdeploop5
A ext/Kconfiglib/tests/Kdeploop6
A ext/Kconfiglib/tests/Kdeploop7
A ext/Kconfiglib/tests/Kdeploop8
A ext/Kconfiglib/tests/Kdeploop9
A ext/Kconfiglib/tests/Kdirdep
A ext/Kconfiglib/tests/Kescape
A ext/Kconfiglib/tests/Keval
A ext/Kconfiglib/tests/Kexpr_items
A ext/Kconfiglib/tests/Kheader
A ext/Kconfiglib/tests/Khelp
A ext/Kconfiglib/tests/Kifremoval
A ext/Kconfiglib/tests/Kimply
A ext/Kconfiglib/tests/Kinclude_path
A ext/Kconfiglib/tests/Kinclude_path_sourced_1
A ext/Kconfiglib/tests/Kinclude_path_sourced_2
A ext/Kconfiglib/tests/Kitemlists
A ext/Kconfiglib/tests/Klocation
A ext/Kconfiglib/tests/Klocation_sourced
A ext/Kconfiglib/tests/Kmainmenu
A ext/Kconfiglib/tests/Kmenuconfig
A ext/Kconfiglib/tests/Kmisc
A ext/Kconfiglib/tests/Kmissingrsource
A ext/Kconfiglib/tests/Kmissingsource
A ext/Kconfiglib/tests/Korder
A ext/Kconfiglib/tests/Kpreprocess
A ext/Kconfiglib/tests/Krange
A ext/Kconfiglib/tests/Krecursive1
A ext/Kconfiglib/tests/Krecursive2
A ext/Kconfiglib/tests/Kreferenced
A ext/Kconfiglib/tests/Krelation
A ext/Kconfiglib/tests/Krepr
A ext/Kconfiglib/tests/Kstr
A ext/Kconfiglib/tests/Kundef
A ext/Kconfiglib/tests/Kuserfunctions
A ext/Kconfiglib/tests/Kvisibility
A ext/Kconfiglib/tests/config_indented
A ext/Kconfiglib/tests/config_set_bool
A ext/Kconfiglib/tests/config_set_string
A ext/Kconfiglib/tests/defconfig_1
A ext/Kconfiglib/tests/defconfig_2
A ext/Kconfiglib/tests/empty
A ext/Kconfiglib/tests/kconfigfunctions.py
A ext/Kconfiglib/tests/reltest
A ext/Kconfiglib/tests/sub/Kconfig_symlink_2
A ext/Kconfiglib/tests/sub/Kconfig_symlink_3
A ext/Kconfiglib/tests/sub/Klocation_grsourced1
A ext/Kconfiglib/tests/sub/Klocation_grsourced2
A ext/Kconfiglib/tests/sub/Klocation_gsourced1
A ext/Kconfiglib/tests/sub/Klocation_gsourced2
A ext/Kconfiglib/tests/sub/Klocation_rsourced
A ext/Kconfiglib/tests/sub/defconfig_in_sub
A ext/Kconfiglib/tests/sub/sub/Kconfig_symlink_1
A ext/Kconfiglib/testsuite.py
M site_scons/gem5_python_paths.py
104 files changed, 21,897 insertions(+), 0 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass





--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie9c902819ed0750a04f8318911fa914701c2a0fe
Gerrit-Change-Number: 56755
Gerrit-PatchSet: 10
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer:

[gem5-dev] Change in gem5/gem5[develop]: util-docker: Add docker container for building riscv target

2022-03-14 Thread Hoa Nguyen (Gerrit) via gem5-dev

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57609 )



Change subject: util-docker: Add docker container for building riscv target
..

util-docker: Add docker container for building riscv target

This container comes with clang main branch and with
riscv-gnu-toolchain main branch as the back-end.

Signed-off-by: Hoa Nguyen 
Change-Id: I0bc310e1ae3ca9257fbde95a864c2b48009cd897
---
M util/dockerfiles/docker-compose.yaml
A util/dockerfiles/llvm-riscv-target/Dockerfile
2 files changed, 100 insertions(+), 1 deletion(-)



diff --git a/util/dockerfiles/docker-compose.yaml  
b/util/dockerfiles/docker-compose.yaml

index bcae58a..f25a021 100644
--- a/util/dockerfiles/docker-compose.yaml
+++ b/util/dockerfiles/docker-compose.yaml
@@ -110,4 +110,10 @@
 args:
 - version=12
 image: gcr.io/gem5-test/clang-version-12
-
+clang-dev-riscv-target:
+build:
+context: ubuntu-20.04_clang-version
+dockerfile: Dockerfile
+args:
+- version=dev-riscv-target
+image: gcr.io/gem5-test/clang-dev-riscv-target
diff --git a/util/dockerfiles/llvm-riscv-target/Dockerfile  
b/util/dockerfiles/llvm-riscv-target/Dockerfile

new file mode 100644
index 000..e403f5a
--- /dev/null
+++ b/util/dockerfiles/llvm-riscv-target/Dockerfile
@@ -0,0 +1,80 @@
+# Copyright (c) 2022 The Regents of the University of California
+# All Rights Reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+# stage 1: download the compilers and compile them
+FROM ubuntu:20.04 AS stage1
+
+ENV DEBIAN_FRONTEND=noninteractive
+RUN apt -y update
+RUN apt -y upgrade
+RUN apt -y install \
+  binutils build-essential libtool texinfo gzip zip unzip patchutils curl  
git \

+  make cmake ninja-build automake bison flex gperf grep sed gawk bc \
+  zlib1g-dev libexpat1-dev libmpc-dev libglib2.0-dev libfdt-dev  
libpixman-1-dev

+
+RUN mkdir -p /riscv/_install
+WORKDIR /riscv
+ENV PATH=`/riscv/_install/bin:$PATH`
+RUN git clone --recursive https://github.com/riscv/riscv-gnu-toolchain
+WORKDIR /riscv/riscv-gnu-toolchain
+RUN ./configure --prefix=/riscv/_install --enable-multilib
+RUN make linux -j`nproc`
+RUN make install
+
+WORKDIR /riscv
+RUN git clone https://github.com/llvm/llvm-project.git riscv-llvm
+WORKDIR /riscv/riscv-llvm
+RUN ln -s ../../clang llvm/tools || true
+RUN mkdir _build
+WORKDIR /riscv/riscv-llvm/_build
+RUN cmake -G Ninja -DCMAKE_BUILD_TYPE="Release" \
+  -DBUILD_SHARED_LIBS=True -DLLVM_USE_SPLIT_DWARF=True \
+  -DCMAKE_INSTALL_PREFIX="/riscv/_install" \
+  -DLLVM_OPTIMIZED_TABLEGEN=True -DLLVM_BUILD_TESTS=False \
+  -DDEFAULT_SYSROOT="/riscv/_install/sysroot" \
+  -DLLVM_DEFAULT_TARGET_TRIPLE="riscv64-unknown-linux-gnu" \
+  -DLLVM_TARGETS_TO_BUILD="RISCV" \
+  ../llvm
+RUN cmake --build . --target install -j`nproc`
+
+
+
+# stage 2: create a new container with the compiled cross-compilers only
+FROM ubuntu:20.04
+ENV DEBIAN_FRONTEND=noninteractive
+RUN apt -y update
+RUN apt -y upgrade
+RUN apt -y install \
+  binutils build-essential libtool texinfo gzip zip unzip patchutils curl  
git \

+  make cmake ninja-build automake bison flex gperf grep sed gawk bc \
+  zlib1g-dev libexpat1-dev libmpc-dev libglib2.0-dev libfdt-dev  
libpixman-1-dev

+
+RUN mkdir -p /riscv/
+COPY --from=stage1 /riscv/_install/ /riscv/_install
+ENV PATH=/riscv/_install/bin:$PATH
+
+RUN mkdir -p /workdir

--
To view, visit

[gem5-dev] Change in gem5/gem5[develop]: arch: Make the DummyVec... types the same size as RegVal.

2022-03-14 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56929 )


Change subject: arch: Make the DummyVec... types the same size as RegVal.
..

arch: Make the DummyVec... types the same size as RegVal.

This makes RegClass-es which don't specify a size work with the Dummy
types of VecRegContainer and VecPredRegContainer, and avoids having to
set up extra plumbing in ISAs that don't need it.

Change-Id: I059306a54b2a9cf7a22258a01e0821e370f0590a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56929
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Gabe Black 
---
M src/arch/generic/vec_pred_reg.hh
M src/arch/generic/vec_reg.hh
2 files changed, 61 insertions(+), 2 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/generic/vec_pred_reg.hh  
b/src/arch/generic/vec_pred_reg.hh

index ad6bcce..9495911 100644
--- a/src/arch/generic/vec_pred_reg.hh
+++ b/src/arch/generic/vec_pred_reg.hh
@@ -44,6 +44,7 @@
 #include 

 #include "base/cprintf.hh"
+#include "base/types.hh"
 #include "sim/serialize_handlers.hh"

 namespace gem5
@@ -394,7 +395,27 @@
 /// Dummy type aliases and constants for architectures that do not  
implement

 /// vector predicate registers.
 /// @{
-using DummyVecPredRegContainer = VecPredRegContainer<8, false>;
+struct DummyVecPredRegContainer
+{
+RegVal filler = 0;
+bool operator == (const DummyVecPredRegContainer ) const { return  
true; }
+bool operator != (const DummyVecPredRegContainer ) const { return  
true; }

+};
+template <>
+struct ParseParam
+{
+static bool
+parse(const std::string , DummyVecPredRegContainer )
+{
+return false;
+}
+};
+static_assert(sizeof(DummyVecPredRegContainer) == sizeof(RegVal));
+static inline std::ostream &
+operator<<(std::ostream , const DummyVecPredRegContainer )
+{
+return os;
+}
 /// @}

 } // namespace gem5
diff --git a/src/arch/generic/vec_reg.hh b/src/arch/generic/vec_reg.hh
index f32f581..c818b1c 100644
--- a/src/arch/generic/vec_reg.hh
+++ b/src/arch/generic/vec_reg.hh
@@ -104,6 +104,7 @@

 #include "base/cprintf.hh"
 #include "base/logging.hh"
+#include "base/types.hh"
 #include "sim/serialize_handlers.hh"

 namespace gem5
@@ -264,7 +265,27 @@
  * vector registers.
  */
 /** @{ */
-using DummyVecRegContainer = VecRegContainer<8>;
+struct DummyVecRegContainer
+{
+RegVal filler = 0;
+bool operator == (const DummyVecRegContainer ) const { return true; }
+bool operator != (const DummyVecRegContainer ) const { return true; }
+};
+template <>
+struct ParseParam
+{
+static bool
+parse(const std::string , DummyVecRegContainer )
+{
+return false;
+}
+};
+static_assert(sizeof(DummyVecRegContainer) == sizeof(RegVal));
+static inline std::ostream &
+operator<<(std::ostream , const DummyVecRegContainer )
+{
+return os;
+}
 /** @} */

 } // namespace gem5

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I059306a54b2a9cf7a22258a01e0821e370f0590a
Gerrit-Change-Number: 56929
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fix the SAHF and LAHF instructions.

2022-03-14 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55824 )


 (

10 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-x86: Fix the SAHF and LAHF instructions.
..

arch-x86: Fix the SAHF and LAHF instructions.

These had been transposed with each other, and had other problems having
to do with data truncation and old bits leaking through into other
registers.

Change-Id: Ib46eaa201d4b8273a683ebcb0060e8d49c447d96
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55824
Reviewed-by: Matthew Poremba 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/x86/isa/insts/general_purpose/flags/load_and_store.py
1 file changed, 22 insertions(+), 2 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/x86/isa/insts/general_purpose/flags/load_and_store.py  
b/src/arch/x86/isa/insts/general_purpose/flags/load_and_store.py

index 76f81c1..31723b3 100644
--- a/src/arch/x86/isa/insts/general_purpose/flags/load_and_store.py
+++ b/src/arch/x86/isa/insts/general_purpose/flags/load_and_store.py
@@ -35,10 +35,13 @@

 microcode = '''
 def macroop SAHF {
-ruflags ah, dataSize=1
+ruflags t1, dataSize=8
+mov t1, t1, ah, dataSize=1
+wruflags t1, t0, dataSize=8
 };

 def macroop LAHF {
-wruflags ah, t0, dataSize=1
+rflags t1, dataSize=8
+andi ah, t1, "CFBit | PFBit | AFBit | ZFBit | SFBit | (1 << 1)",  
dataSize=1

 };
 '''

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib46eaa201d4b8273a683ebcb0060e8d49c447d96
Gerrit-Change-Number: 55824
Gerrit-PatchSet: 12
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bradford Beckmann 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev-amdgpu: Handle framebuffer reads from device cache

2022-03-14 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57589 )



Change subject: dev-amdgpu: Handle framebuffer reads from device cache
..

dev-amdgpu: Handle framebuffer reads from device cache

Reads to the frame buffer are currently handled by either the MMIO trace
or from the GART table if the address is in the GART aperture. In some
cases the MMIO trace will not contain the address or the data may have
been written previously and be different from the MMIO trace. To handle
this, return the data that was written previously by the driver. The
priority order from lowest to highest is: MMIO trace, device cache,
special framebuffer registers.

Change-Id: Ia45ae1908fcd780926fedbd7a65c3d294727
---
M src/dev/amdgpu/amdgpu_device.cc
1 file changed, 25 insertions(+), 1 deletion(-)



diff --git a/src/dev/amdgpu/amdgpu_device.cc  
b/src/dev/amdgpu/amdgpu_device.cc

index 3f66570..ffa5bb8 100644
--- a/src/dev/amdgpu/amdgpu_device.cc
+++ b/src/dev/amdgpu/amdgpu_device.cc
@@ -179,8 +179,14 @@
 {
 DPRINTF(AMDGPUDevice, "Read framebuffer address %#lx\n", offset);

+/* Try MMIO trace for frame writes first. */
 mmioReader.readFromTrace(pkt, FRAMEBUFFER_BAR, offset);

+/* If the driver wrote something, use that value over the trace. */
+if (frame_regs.find(offset) != frame_regs.end()) {
+pkt->setUintX(frame_regs[offset], ByteOrder::little);
+}
+
 /* Handle special counter addresses in framebuffer. */
 if (offset == 0xa28000) {
 /* Counter addresses expect the read to return previous value + 1.  
*/

@@ -247,8 +253,9 @@
 Addr aperture_offset = offset - aperture;

 // Record the value
-frame_regs[aperture_offset] = pkt->getLE();
+frame_regs[offset] = pkt->getLE();
 if (aperture == gpuvm.gartBase()) {
+frame_regs[aperture_offset] = pkt->getLE();
 DPRINTF(AMDGPUDevice, "GART translation %p -> %p\n",  
aperture_offset,

 bits(frame_regs[aperture_offset], 48, 12));
 gpuvm.gartTable[aperture_offset] = pkt->getLE();

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia45ae1908fcd780926fedbd7a65c3d294727
Gerrit-Change-Number: 57589
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: scons: Process the SConsopts files for each variant.

2022-03-14 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56751 )


Change subject: scons: Process the SConsopts files for each variant.
..

scons: Process the SConsopts files for each variant.

The SConsopts files that need to be processed is affected by the EXTRAS
setting, and if all settings are going to be local to the variants, that
means each variant can have a different set of SConsopts files to use.

This does result in Configure type output showing up repeatedly when
building multiple variants, but that's uncommon for users, and will
hopefully become unnecessary for developers over time.

Change-Id: I7df287c37fc32e91576dced80d0a9e56806c4581
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56751
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Andreas Sandberg 
---
M SConstruct
1 file changed, 67 insertions(+), 46 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/SConstruct b/SConstruct
index fe7b3ab..ec36532 100755
--- a/SConstruct
+++ b/SConstruct
@@ -597,52 +597,6 @@

 
 #
-# Read and process SConsopts files. These can add new settings which
-# affect each variant directory independently.
-#
-
-
-# Register a callback which is called after all SConsopts files have been  
read.

-after_sconsopts_callbacks = []
-def AfterSConsopts(cb):
-after_sconsopts_callbacks.append(cb)
-Export('AfterSConsopts')
-
-# Sticky variables get saved in the variables file so they persist from
-# one invocation to the next (unless overridden, in which case the new
-# value becomes sticky).
-sticky_vars = Variables(args=ARGUMENTS)
-Export('sticky_vars')
-
-# Sticky variables that should be exported to #defines in config/*.hh
-# (see src/SConscript).
-export_vars = []
-Export('export_vars')
-
-# Walk the tree and execute all SConsopts scripts that wil add to the
-# above variables
-if GetOption('verbose'):
-print("Reading SConsopts")
-for bdir in [ base_dir ] + extras_dir_list:
-if not isdir(bdir):
-error("Directory '%s' does not exist." % bdir)
-for root, dirs, files in os.walk(bdir):
-if 'SConsopts' in files:
-if GetOption('verbose'):
-print("Reading", os.path.join(root, 'SConsopts'))
-SConscript(os.path.join(root, 'SConsopts'))
-
-# Call any callbacks which the SConsopts files registered.
-for cb in after_sconsopts_callbacks:
-cb()
-
-# Add any generic sticky variables here.
-sticky_vars.Add(BoolVariable('USE_EFENCE',
-'Link with Electric Fence malloc debugger', False))
-
-
-
-#
 # Define build environments for required variants.
 #
 
@@ -659,6 +613,52 @@
 # determine the build parameters (e.g., 'X86')
 (build_root, variant_dir) = os.path.split(variant_path)

+
+#
+# Read and process SConsopts files. These can add new settings which
+# affect each variant directory independently.
+#
+
+
+# Register a callback to call after all SConsopts files have been read.
+after_sconsopts_callbacks = []
+def AfterSConsopts(cb):
+after_sconsopts_callbacks.append(cb)
+Export('AfterSConsopts')
+
+# Sticky variables get saved in the variables file so they persist from
+# one invocation to the next (unless overridden, in which case the new
+# value becomes sticky).
+sticky_vars = Variables(args=ARGUMENTS)
+Export('sticky_vars')
+
+# Sticky variables that should be exported to #defines in config/*.hh
+# (see src/SConscript).
+export_vars = []
+Export('export_vars')
+
+# Walk the tree and execute all SConsopts scripts that wil add to the
+# above variables
+if GetOption('verbose'):
+print("Reading SConsopts")
+for bdir in [ base_dir ] + extras_dir_list:
+if not isdir(bdir):
+error("Directory '%s' does not exist." % bdir)
+for root, dirs, files in os.walk(bdir):
+if 'SConsopts' in files:
+if GetOption('verbose'):
+print("Reading", os.path.join(root, 'SConsopts'))
+SConscript(os.path.join(root, 'SConsopts'),
+exports={'main': env})
+
+# Call any callbacks which the SConsopts files registered.
+for cb in after_sconsopts_callbacks:
+cb()
+
+# Add any generic sticky variables here.
+sticky_vars.Add(BoolVariable('USE_EFENCE',
+'Link with Electric Fence malloc

[gem5-dev] Change in gem5/gem5[develop]: scons: Turn a lot of compiler flag vars into env vars.

2022-03-14 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56752 )


Change subject: scons: Turn a lot of compiler flag vars into env vars.
..

scons: Turn a lot of compiler flag vars into env vars.

These are used to adapt gem5 to the system it's being built on, and so
should be attached to the host via the environment rather than gem5's
configuration.

Change-Id: I2adfe1af484dcdeae32a48097d9aa87752a7ed2a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56752
Reviewed-by: Daniel Carvalho 
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Andreas Sandberg 
---
M SConstruct
M site_scons/gem5_scons/defaults.py
2 files changed, 27 insertions(+), 9 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Daniel Carvalho: Looks good to me, but someone else must approve
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/SConstruct b/SConstruct
index ec36532..000e526 100755
--- a/SConstruct
+++ b/SConstruct
@@ -253,13 +253,6 @@
 global_vars = Variables(global_vars_file, args=ARGUMENTS)

 global_vars.AddVariables(
-('CCFLAGS_EXTRA', 'Extra C and C++ compiler flags', ''),
-('GEM5PY_CCFLAGS_EXTRA', 'Extra C and C++ gem5py compiler flags', ''),
-('GEM5PY_LINKFLAGS_EXTRA', 'Extra marshal gem5py flags', ''),
-('LINKFLAGS_EXTRA', 'Extra linker flags', ''),
-('PYTHON_CONFIG', 'Python config binary to use',
- [ 'python3-config', 'python-config']
-),
 ('BATCH', 'Use batch pool for build and tests', False),
 ('BATCH_CMD', 'Batch pool submission command name', 'qdo'),
 ('M5_BUILD_CACHE', 'Cache built objects in this directory', False),
diff --git a/site_scons/gem5_scons/defaults.py  
b/site_scons/gem5_scons/defaults.py

index 4efaa26..4382937 100644
--- a/site_scons/gem5_scons/defaults.py
+++ b/site_scons/gem5_scons/defaults.py
@@ -46,7 +46,9 @@
 # export TERM so that clang reports errors in color
 use_vars = set([ 'AS', 'AR', 'CC', 'CXX', 'HOME', 'LD_LIBRARY_PATH',
  'LIBRARY_PATH', 'PATH', 'PKG_CONFIG_PATH', 'PROTOC',
- 'PYTHONPATH', 'RANLIB', 'TERM' ])
+ 'PYTHONPATH', 'RANLIB', 'TERM', 'PYTHON_CONFIG',
+ 'CCFLAGS_EXTRA', 'GEM5PY_CCFLAGS_EXTRA',
+ 'GEM5PY_LINKFLAGS_EXTRA', 'LINKFLAGS_EXTRA'])

 use_prefixes = [
 "ASAN_",   # address sanitizer symbolizer path and settings
@@ -68,7 +70,12 @@
 var_overrides = {
 'CC': env['CC'],
 'CXX': env['CXX'],
-'PROTOC': 'protoc'
+'PROTOC': 'protoc',
+'PYTHON_CONFIG': [ 'python3-config', 'python-config' ],
+'CCFLAGS_EXTRA': '',
+'GEM5PY_CCFLAGS_EXTRA': '',
+'GEM5PY_LINKFLAGS_EXTRA': '',
+'LINKFLAGS_EXTRA': '',
 }
 for key,default in var_overrides.items():
 env[key] = env['ENV'].get(key, default)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2adfe1af484dcdeae32a48097d9aa87752a7ed2a
Gerrit-Change-Number: 56752
Gerrit-PatchSet: 9
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev,arch-x86: Make the I8042 reset settings more realistic.

2022-03-14 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55805 )


 (

11 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: dev,arch-x86: Make the I8042 reset settings more  
realistic.

..

dev,arch-x86: Make the I8042 reset settings more realistic.

When powered on, the "passed self test" bit should not be set. It should
only be set once the I8042 has actually been told to do a self test.
Also the mouse and keyboard should be disabled. With them disabled their
interrupts won't matter, but we might as well leave those disabled as
well.

Change-Id: Ief1ab30365a0a8ea0a116e52c16dcccf441515ec
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55805
Reviewed-by: Matthew Poremba 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/dev/x86/i8042.cc
1 file changed, 21 insertions(+), 4 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/x86/i8042.cc b/src/dev/x86/i8042.cc
index 7aed0ee..268d090 100644
--- a/src/dev/x86/i8042.cc
+++ b/src/dev/x86/i8042.cc
@@ -55,13 +55,11 @@
 fatal_if(!mouse, "The i8042 model requires a mouse instance");
 fatal_if(!keyboard, "The i8042 model requires a keyboard instance");

-statusReg.passedSelfTest = 1;
-statusReg.commandLast = 1;
 statusReg.keyboardUnlocked = 1;

 commandByte.convertScanCodes = 1;
-commandByte.passedSelfTest = 1;
-commandByte.keyboardFullInt = 1;
+commandByte.disableMouse = 1;
+commandByte.disableKeyboard = 1;

 for (int i = 0; i < p.port_keyboard_int_pin_connection_count; i++) {
 keyboardIntPin.push_back(new IntSourcePin(

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ief1ab30365a0a8ea0a116e52c16dcccf441515ec
Gerrit-Change-Number: 55805
Gerrit-PatchSet: 13
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bradford Beckmann 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: dev,arch-x86: Implement some self test 8042 commands.

2022-03-14 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55806 )


 (

11 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: dev,arch-x86: Implement some self test 8042 commands.
..

dev,arch-x86: Implement some self test 8042 commands.

The self test in particular is used by bare metal software to ensure
that the keyboard controller is reset and ready to use.

Change-Id: I53c2a80c181b9d19617c75657637e06951c94433
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55806
Reviewed-by: Matthew Poremba 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/dev/x86/i8042.cc
1 file changed, 34 insertions(+), 3 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/x86/i8042.cc b/src/dev/x86/i8042.cc
index 268d090..9fab694 100644
--- a/src/dev/x86/i8042.cc
+++ b/src/dev/x86/i8042.cc
@@ -226,11 +226,26 @@
 commandByte.disableMouse = 0;
 break;
   case TestMouse:
-panic("i8042 \"Test mouse\" command not implemented.\n");
+// The response to this is from the 8042, not the mouse.
+// Hard code no errors detected.
+writeData(0x00);
+break;
   case SelfTest:
-panic("i8042 \"Self test\" command not implemented.\n");
+// Exactly what this does is essentially undocumented, but  
this:

+// https://www.os2museum.com/wp/
+//  ibm-pcat-8042-keyboard-controller-commands/
+// says that this should essentially reset some values.
+commandByte.convertScanCodes = 1;
+commandByte.disableMouse = 1;
+commandByte.disableKeyboard = 1;
+commandByte.passedSelfTest = 1;
+statusReg.passedSelfTest = 1;
+writeData(0x55); // Self test passed.
+break;
   case InterfaceTest:
-panic("i8042 \"Interface test\" command not implemented.\n");
+// Hard code no errors detected.
+writeData(0x00);
+break;
   case DiagnosticDump:
 panic("i8042 \"Diagnostic dump\" command not implemented.\n");
   case DisableKeyboard:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I53c2a80c181b9d19617c75657637e06951c94433
Gerrit-Change-Number: 55806
Gerrit-PatchSet: 13
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bradford Beckmann 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: util: Remove util/cloudbuild

2022-03-14 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57431 )


Change subject: util: Remove util/cloudbuild
..

util: Remove util/cloudbuild

The "util/cloudbuild" directory was used to build Docker images on
the Google Cloud Build infrastructure. The gem5 project no longer uses
this service to build Docker images and, as such, this directory (and
its contents) are no longer required.

Change-Id: I724c50ec6045ab95f6b94533f2fd54980230789c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57431
Reviewed-by: Gabe Black 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
D util/cloudbuild/cloudbuild_create_images.yaml
1 file changed, 19 insertions(+), 110 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/util/cloudbuild/cloudbuild_create_images.yaml  
b/util/cloudbuild/cloudbuild_create_images.yaml

deleted file mode 100644
index 7549012..000
--- a/util/cloudbuild/cloudbuild_create_images.yaml
+++ /dev/null
@@ -1,110 +0,0 @@
-steps:
-- name: 'gcr.io/cloud-builders/docker'
-  args: ['build',
-'-t',
-'gcr.io/$PROJECT_ID/ubuntu-20.04_all-dependencies:latest',
-'util/dockerfiles/ubuntu-20.04_all-dependencies']
-
-- name: 'gcr.io/cloud-builders/docker'
-  args: ['build',
-'-t',
-'gcr.io/$PROJECT_ID/ubuntu-20.04_min-dependencies:latest',
-'util/dockerfiles/ubuntu-20.04_min-dependencies']
-
-- name: 'gcr.io/cloud-builders/docker'
-  args: ['build',
-'-t',
-'gcr.io/$PROJECT_ID/ubuntu-18.04_all-dependencies:latest',
-'util/dockerfiles/ubuntu-18.04_all-dependencies']
-
-- name: 'gcr.io/cloud-builders/docker'
-  args: ['build',
-'-t',
-'gcr.io/$PROJECT_ID/gcc-version-7:latest',
-'--build-arg', 'version=7',
-'util/dockerfiles/ubuntu-18.04_gcc-version']
-
-- name: 'gcr.io/cloud-builders/docker'
-  args: ['build',
-'-t',
-'gcr.io/$PROJECT_ID/gcc-version-8:latest',
-'--build-arg', 'version=8',
-'util/dockerfiles/ubuntu-18.04_gcc-version']
-
-- name: 'gcr.io/cloud-builders/docker'
-  args: ['build',
-'-t',
-'gcr.io/$PROJECT_ID/gcc-version-9:latest',
-'--build-arg', 'version=9',
-'util/dockerfiles/ubuntu-20.04_gcc-version']
-
-- name: 'gcr.io/cloud-builders/docker'
-  args: ['build',
-'-t',
-'gcr.io/$PROJECT_ID/gcc-version-10:latest',
-'--build-arg', 'version=10',
-'util/dockerfiles/ubuntu-20.04_gcc-version']
-
-- name: 'gcr.io/cloud-builders/docker'
-  args: ['build',
-'-t',
-'gcr.io/$PROJECT_ID/clang-version-6.0:latest',
-'--build-arg', 'version=6.0',
-'util/dockerfiles/ubuntu-18.04_clang-version']
-
-- name: 'gcr.io/cloud-builders/docker'
-  args: ['build',
-'-t',
-'gcr.io/$PROJECT_ID/clang-version-7:latest',
-'--build-arg', 'version=7',
-'util/dockerfiles/ubuntu-18.04_clang-version']
-
-- name: 'gcr.io/cloud-builders/docker'
-  args: ['build',
-'-t',
-'gcr.io/$PROJECT_ID/clang-version-8:latest',
-'--build-arg', 'version=8',
-'util/dockerfiles/ubuntu-18.04_clang-version']
-
-- name: 'gcr.io/cloud-builders/docker'
-  args: ['build',
-'-t',
-'gcr.io/$PROJECT_ID/clang-version-9:latest',
-'--build-arg', 'version=9',
-'util/dockerfiles/ubuntu-18.04_clang-version']
-
-- name: 'gcr.io/cloud-builders/docker'
-  args: ['build',
-'-t',
-'gcr.io/$PROJECT_ID/clang-version-10:latest',
-'--build-arg', 'version=10',
-'util/dockerfiles/ubuntu-20.04_clang-version']
-
-- name: 'gcr.io/cloud-builders/docker'
-  args: ['build',
-'-t',
-'gcr.io/$PROJECT_ID/clang-version-11:latest',
-'--build-arg', 'version=11',
-'util/dockerfiles/ubuntu-20.04_clang-version']
-
-- name: 'gcr.io/cloud-builders/docker'
-  args: ['build',
-'-t',
-'gcr.io/$PROJECT_ID/gcn-gpu:latest',
-'util/dockerfiles/gcn-gpu']
-
-images: ['gcr.io/$PROJECT_ID/ubuntu-20.04_all-dependencies:latest',
- 'gcr.io/$PROJECT_ID/ubuntu-20.04_min-dependencies:latest',
- 'gcr.io/$PROJECT_ID/ubuntu-18.04_all-dependencies:latest',
- 'gcr.io/$PROJECT_ID/gcc-version-7:latest',
- 'gcr.io/$PROJECT_ID/gcc-version-8:latest',
- 'gcr.io/$PROJECT_ID/gcc-version-9:latest',
- 'gcr.io/$PROJECT_ID/gcc-version-10:latest',
-

[gem5-dev] Change in gem5/gem5[develop]: tests,util-docker: Add clang-12 to the compiler tests

2022-03-14 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57430 )


Change subject: tests,util-docker: Add clang-12 to the compiler tests
..

tests,util-docker: Add clang-12 to the compiler tests

Change-Id: I07f37df42b370677f4a5f4cd948b7680d551a5ab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57430
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M tests/compiler-tests.sh
M util/dockerfiles/docker-compose.yaml
M util/dockerfiles/ubuntu-20.04_clang-version/Dockerfile
3 files changed, 23 insertions(+), 1 deletion(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/compiler-tests.sh b/tests/compiler-tests.sh
index 15ffb16..292d661 100755
--- a/tests/compiler-tests.sh
+++ b/tests/compiler-tests.sh
@@ -15,6 +15,7 @@
 "gcc-version-9"
 "gcc-version-8"
 "gcc-version-7"
+"clang-version-12"
 "clang-version-11"
 "clang-version-10"
 "clang-version-9"
@@ -31,7 +32,7 @@
 # A subset of the above list: these images will build against every target,
 # ignoring builds_per_compiler.
 comprehensive=("gcc-version-11"
-   "clang-version-11")
+   "clang-version-12")

 # All build targets in build_opt/ which we want to build using each image.
 builds=("ARM"
diff --git a/util/dockerfiles/docker-compose.yaml  
b/util/dockerfiles/docker-compose.yaml

index 035fea4..bcae58a 100644
--- a/util/dockerfiles/docker-compose.yaml
+++ b/util/dockerfiles/docker-compose.yaml
@@ -103,4 +103,11 @@
 args:
 - version=11
 image: gcr.io/gem5-test/clang-version-11
+clang-12:
+build:
+context: ubuntu-20.04_clang-version
+dockerfile: Dockerfile
+args:
+- version=12
+image: gcr.io/gem5-test/clang-version-12

diff --git a/util/dockerfiles/ubuntu-20.04_clang-version/Dockerfile  
b/util/dockerfiles/ubuntu-20.04_clang-version/Dockerfile

index 447a4dd..534291b 100644
--- a/util/dockerfiles/ubuntu-20.04_clang-version/Dockerfile
+++ b/util/dockerfiles/ubuntu-20.04_clang-version/Dockerfile
@@ -32,6 +32,7 @@
 # 9
 # 10
 # 11
+# 12
 ARG version

 ENV DEBIAN_FRONTEND=noninteractive

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I07f37df42b370677f4a5f4cd948b7680d551a5ab
Gerrit-Change-Number: 57430
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Jason Lowe-Power 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: util-docker: Adding docker-compose.yaml

2022-03-14 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57429 )


Change subject: util-docker: Adding docker-compose.yaml
..

util-docker: Adding docker-compose.yaml

"docker-compose.yaml" is used by the docker-compose utility to define
Docker image builds. In the case the "docker-compose.yaml" file defines
the building of all Docker images used in the gem5 project. These can be
built locally using `docker-compose build`.

Change-Id: I2544ec43e3a1743884e5aa243905704cb263d7d9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57429
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
A util/dockerfiles/README.md
A util/dockerfiles/docker-compose.yaml
2 files changed, 127 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/util/dockerfiles/README.md b/util/dockerfiles/README.md
new file mode 100644
index 000..18686fe
--- /dev/null
+++ b/util/dockerfiles/README.md
@@ -0,0 +1,3 @@
+This directory contains Dockerfiles used to create images used in the gem5  
project.

+The `docker-compose.yaml` defines the building of each image.
+The images can be built locally using `docker-compose build`.
diff --git a/util/dockerfiles/docker-compose.yaml  
b/util/dockerfiles/docker-compose.yaml

new file mode 100644
index 000..035fea4
--- /dev/null
+++ b/util/dockerfiles/docker-compose.yaml
@@ -0,0 +1,106 @@
+version: '2'
+
+services:
+gcn-gpu:
+build:
+context: gcn-gpu
+dockerfile: Dockerfile
+image: gcr.io/gem5-test/gcn-gpu
+sst:
+build:
+context: sst-11.1.0
+dockerfile: Dockerfile
+image: gcr.io/gem5-test/sst-env
+ubuntu-18.04_all-dependencies:
+build:
+context: ubuntu-18.04_all-dependencies
+dockerfile: Dockerfile
+image: gcr.io/gem5-test/ubuntu-18.04_all-dependencies
+ubuntu-20.04_all-dependencies:
+build:
+context: ubuntu-20.04_all-dependencies
+dockerfile: Dockerfile
+image: gcr.io/gem5-test/ubuntu-20.04_all-dependencies
+ubuntu-20.04_min-dependencies:
+build:
+context: ubuntu-20.04_min-dependencies
+dockerfile: Dockerfile
+image: gcr.io/gem5-test/ubuntu-20.04_min-dependencies
+gcc-7:
+build:
+context: ubuntu-18.04_gcc-version
+dockerfile: Dockerfile
+args:
+- version=7
+image: gcr.io/gem5-test/gcc-version-7
+gcc-8:
+build:
+context: ubuntu-18.04_gcc-version
+dockerfile: Dockerfile
+args:
+- version=8
+image: gcr.io/gem5-test/gcc-version-8
+gcc-9:
+build:
+context: ubuntu-20.04_gcc-version
+dockerfile: Dockerfile
+args:
+- version=9
+image: gcr.io/gem5-test/gcc-version-9
+gcc-10:
+build:
+context: ubuntu-20.04_gcc-version
+dockerfile: Dockerfile
+args:
+- version=10
+image: gcr.io/gem5-test/gcc-version-10
+gcc-11:
+build:
+context: ubuntu-20.04_gcc-version-11
+dockerfile: Dockerfile
+args:
+- version=11
+image: gcr.io/gem5-test/gcc-version-11
+clang-6:
+build:
+context: ubuntu-18.04_clang-version
+dockerfile: Dockerfile
+args:
+- version=6.0
+image: gcr.io/gem5-test/clang-version-6.0
+clang-7:
+build:
+context: ubuntu-18.04_clang-version
+dockerfile: Dockerfile
+args:
+- version=7
+image: gcr.io/gem5-test/clang-version-7
+clang-8:
+build:
+context: ubuntu-18.04_clang-version
+dockerfile: Dockerfile
+args:
+- version=8
+image: gcr.io/gem5-test/clang-version-8
+clang-9:
+build:
+context: ubuntu-18.04_clang-version
+dockerfile: Dockerfile
+args:
+- version=9
+image: gcr.io/gem5-test/clang-version-9
+clang-10:
+build:
+context: ubuntu-20.04_clang-version
+dockerfile: Dockerfile
+args:
+- version=10
+image: gcr.io/gem5-test/clang-version-10
+clang-11:
+build:
+context: ubuntu-20.04_clang-version
+dockerfile: Dockerfile
+args:
+- version=11
+image: gcr.io/gem5-test/clang-version-11
+

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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix setup of ESR.IL field

2022-03-14 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57570 )



Change subject: arch-arm: Fix setup of ESR.IL field
..

arch-arm: Fix setup of ESR.IL field

The ESR.IL field (Instruction Lenght) is set to 0 if the exception
has been triggered by a 16-bit instruction (Thumb) and 1 otherwise.

Current implementation has been implemented more or less correctly
for AArch32 but not for AArch64; by doing:

if (to64) {
esr.il = 1;
} ... [AArch32]

We are directly setting ESR.IL to 1 in case the exception is taken in
AArch64 mode. This is not covering the case of a thumb instruction
faulting to AArch64.

We are fixing this by defining a virtual method returning the ESR.IL
bitfield depending on the exception cause/type. This is following
the Arm Architectural Reference Manual, which states ESR.IL bit should
be set to 1 for 32-bit instructions and for cases where the fault
doesn't really depend on the instruction:

* SError interrupt
* Instruction Abort exception
* PC alignment exception
* SP alignment exception
* Data Abort exception for which the value of the ISV bit is 0.
* Illegal Execution state exception.
* Debug exception except for Breakpoint instruction exceptions
* Exception reported using EC value 0b00.

Change-Id: I79c9ba8397248c526490e2ed83088fe968029b0e
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
2 files changed, 110 insertions(+), 27 deletions(-)



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 0efcd27..4ab45d4 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -404,18 +404,8 @@
 assert(!from64 || ArmSystem::highestELIs64(tc));

 esr.ec = exc_class;
+esr.il = il(tc);

-// HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts  
(0x24,

-// 0x25) for which the ISS information is not valid (ARMv7).
-// @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not
-// valid it is treated as RES1.
-if (to64) {
-esr.il = 1;
-} else if ((bits(exc_class, 5, 3) != 4) ||
-   (bits(exc_class, 2) && bits(iss_val, 24))) {
-if (!machInst.thumb || machInst.bigThumb)
-esr.il = 1;
-}
 // Condition code valid for EC[5:4] nonzero
 if (!from64 && ((bits(exc_class, 5, 4) == 0) &&
 (bits(exc_class, 3, 0) != 0))) {
@@ -1367,6 +1357,12 @@
 }

 bool
+DataAbort::il(ThreadContext *tc) const
+{
+return !isv? true : AbortFault::il(tc);
+}
+
+bool
 DataAbort::routeToMonitor(ThreadContext *tc) const
 {
 SCR scr = 0;
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 660a2b7..6c0cda6 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -249,8 +249,9 @@
 virtual bool abortDisable(ThreadContext *tc) = 0;
 virtual bool fiqDisable(ThreadContext *tc) = 0;
 virtual ExceptionClass ec(ThreadContext *tc) const = 0;
-virtual uint32_t vectorCatchFlag() const { return 0x0; }
+virtual bool il(ThreadContext *tc) const = 0;
 virtual uint32_t iss() const = 0;
+virtual uint32_t vectorCatchFlag() const { return 0x0; }
 virtual bool isStage2() const { return false; }
 virtual FSR getFsr(ThreadContext *tc) const { return 0; }
 virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg);
@@ -298,7 +299,15 @@
 uint8_t thumbPcElrOffset() override { return vals.thumbPcElrOffset; }
 bool abortDisable(ThreadContext* tc) override { return  
vals.abortDisable; }

 bool fiqDisable(ThreadContext* tc) override { return vals.fiqDisable; }
+
+/** Syndrome methods */
 ExceptionClass ec(ThreadContext *tc) const override { return vals.ec; }
+bool
+il(ThreadContext *tc) const override
+{
+// ESR.IL = 1 if exception cause is unknown (EC = 0)
+return ec(tc) == EC_UNKNOWN || !machInst.thumb ||  
machInst.bigThumb;

+}
 uint32_t iss() const override { return issRaw; }
 };

@@ -339,9 +348,11 @@
 void invoke(ThreadContext *tc, const StaticInstPtr  =
 nullStaticInstPtr) override;
 bool routeToHyp(ThreadContext *tc) const override;
+uint32_t vectorCatchFlag() const override { return 0x0202; }
+
+/** Syndrome methods */
 ExceptionClass ec(ThreadContext *tc) const override;
 uint32_t iss() const override;
-uint32_t vectorCatchFlag() const override { return 0x0202; }
 };

 class SupervisorCall : public ArmFaultVals
@@ -360,9 +371,11 @@
 void invoke(ThreadContext *tc, const StaticInstPtr  =
 nullStaticInstPtr) override;
 bool routeToHyp(ThreadContext *tc) const override;
+uint32_t vectorCatchFlag() const override { return 0x04000404; }
+
+/** Syndrome methods */
 ExceptionClass ec(ThreadContext *tc) const override;
 uint32_t iss() const override;
-uint32_t vectorCatchFlag() const override { return 0x04000404;

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix coding tyle of faults.{cc,hh}

2022-03-14 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57569 )



Change subject: arch-arm: Fix coding tyle of faults.{cc,hh}
..

arch-arm: Fix coding tyle of faults.{cc,hh}

Change-Id: Iaf7858ab08fc858b7c2f932240e24657dc48bbe4
Signed-off-by: Giacomo Travaglini 
---
M src/arch/arm/faults.cc
M src/arch/arm/faults.hh
2 files changed, 80 insertions(+), 59 deletions(-)



diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 4e3d10d..0efcd27 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -934,8 +934,8 @@
 }


-HypervisorCall::HypervisorCall(ExtMachInst _machInst, uint32_t _imm) :
-ArmFaultVals(_machInst, _imm)
+HypervisorCall::HypervisorCall(ExtMachInst mach_inst, uint32_t _imm) :
+ArmFaultVals(mach_inst, _imm)
 {
 bStep = true;
 }
@@ -1613,8 +1613,8 @@
 }


-SoftwareBreakpoint::SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t  
_iss)

-: ArmFaultVals(_mach_inst, _iss)
+SoftwareBreakpoint::SoftwareBreakpoint(ExtMachInst mach_inst, uint32_t  
_iss)

+: ArmFaultVals(mach_inst, _iss)
 {}

 bool
@@ -1633,8 +1633,8 @@
 return from64 ? EC_SOFTWARE_BREAKPOINT_64 : vals.ec;
 }

-HardwareBreakpoint::HardwareBreakpoint(Addr _vaddr,  uint32_t _iss)
-: ArmFaultVals(0x0, _iss), vAddr(_vaddr)
+HardwareBreakpoint::HardwareBreakpoint(Addr vaddr,  uint32_t _iss)
+: ArmFaultVals(0x0, _iss), vAddr(vaddr)
 {}

 bool
@@ -1683,9 +1683,9 @@

 }

-Watchpoint::Watchpoint(ExtMachInst _mach_inst, Addr _vaddr,
+Watchpoint::Watchpoint(ExtMachInst mach_inst, Addr _vaddr,
bool _write, bool _cm)
-: ArmFaultVals(_mach_inst), vAddr(_vaddr),
+: ArmFaultVals(mach_inst), vAddr(_vaddr),
   write(_write), cm(_cm)
 {}

@@ -1744,9 +1744,9 @@
 return EC_WATCHPOINT_LOWER_EL;
 }

-SoftwareStepFault::SoftwareStepFault(ExtMachInst _mach_inst, bool is_ldx,
+SoftwareStepFault::SoftwareStepFault(ExtMachInst mach_inst, bool is_ldx,
  bool _stepped)
-: ArmFaultVals(_mach_inst), isldx(is_ldx),
+: ArmFaultVals(mach_inst), isldx(is_ldx),
   stepped(_stepped)
 {
 bStep = true;
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 906f704..660a2b7 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -193,26 +193,27 @@
 // (exceptions taken in HYP mode or in AArch64 state)
 const ExceptionClass ec;

-FaultVals(const FaultName& name_, const FaultOffset& offset_,
-const uint16_t& currELTOffset_, const uint16_t&  
currELHOffset_,

-const uint16_t& lowerEL64Offset_,
-const uint16_t& lowerEL32Offset_,
-const OperatingMode& nextMode_, const uint8_t&  
armPcOffset_,
-const uint8_t& thumbPcOffset_, const uint8_t&  
armPcElrOffset_,
-const uint8_t& thumbPcElrOffset_, const bool&  
hypTrappable_,

-const bool& abortDisable_, const bool& fiqDisable_,
-const ExceptionClass& ec_)
-: name(name_), offset(offset_), currELTOffset(currELTOffset_),
-  currELHOffset(currELHOffset_), lowerEL64Offset(lowerEL64Offset_),
-  lowerEL32Offset(lowerEL32Offset_), nextMode(nextMode_),
-  armPcOffset(armPcOffset_), thumbPcOffset(thumbPcOffset_),
-  armPcElrOffset(armPcElrOffset_),  
thumbPcElrOffset(thumbPcElrOffset_),

-  hypTrappable(hypTrappable_), abortDisable(abortDisable_),
-  fiqDisable(fiqDisable_), ec(ec_) {}
+FaultVals(const FaultName& name_, FaultOffset offset_,
+  uint16_t curr_elt_offset, uint16_t curr_elh_offset,
+  uint16_t lower_el64_offset,
+  uint16_t lower_el32_offset,
+  OperatingMode next_mode, uint8_t arm_pc_offset,
+  uint8_t thumb_pc_offset, uint8_t arm_pc_elr_offset,
+  uint8_t thumb_pc_elr_offset, bool hyp_trappable,
+  bool abort_disable, bool fiq_disable,
+  ExceptionClass ec_)
+: name(name_), offset(offset_), currELTOffset(curr_elt_offset),
+  currELHOffset(curr_elh_offset),  
lowerEL64Offset(lower_el64_offset),

+  lowerEL32Offset(lower_el32_offset), nextMode(next_mode),
+  armPcOffset(arm_pc_offset), thumbPcOffset(thumb_pc_offset),
+  armPcElrOffset(arm_pc_elr_offset),
+  thumbPcElrOffset(thumb_pc_elr_offset),
+  hypTrappable(hyp_trappable), abortDisable(abort_disable),
+  fiqDisable(fiq_disable), ec(ec_) {}
 };

-ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) :
-machInst(_machInst), issRaw(_iss), bStep(false), from64(false),
+ArmFault(ExtMachInst mach_inst = 0, uint32_t _iss = 0) :
+machInst(mach_inst), issRaw(_iss), bStep(false), from64(false),
 to64(false),

[gem5-dev] Change in gem5/gem5[develop]: sim-se: Initialize shared page table base upon clone

2022-03-14 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56366 )


Change subject: sim-se: Initialize shared page table base upon clone
..

sim-se: Initialize shared page table base upon clone

When the clone syscall is called, a new process is created which
allocates a new page table. If clone was called with CLONE_THREAD, the
page table of that new process is then marked as shared. Next, initState
is called on the process which calls the page table's initState. For the
multi level page table, initState only sets the base pointer if shared
is false. This means that in this order the base pointer of the new page
table is not currently initialized causing spurious errors.

To fix this, the page table is explicitly initialized after the new
process and new page table are created but before the page table is
marked as shared. The process initState continues as normal and the new
page table's base pointer is not modified by further calls to initState
as it is already marked shared.

Change-Id: I4a533e13565fa572fb9153a926f70958bc7488b7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56366
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Reviewed-by: Matt Sinclair 
Tested-by: kokoro 
---
M src/sim/syscall_emul.hh
1 file changed, 29 insertions(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Matt Sinclair: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 546ae75..3fe1cf0 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -1672,6 +1672,7 @@
 }

 if (flags & OS::TGT_CLONE_THREAD) {
+cp->pTable->initState();
 cp->pTable->shared = true;
 cp->useForClone = true;
 }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4a533e13565fa572fb9153a926f70958bc7488b7
Gerrit-Change-Number: 56366
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Make the flags microops handle reserved bits better.

2022-03-14 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55823 )


 (

10 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: arch-x86: Make the flags microops handle reserved bits  
better.

..

arch-x86: Make the flags microops handle reserved bits better.

These microops should report bits which are RAZ as zero and RAO as one,
and not let those bits get overwritten with anything else.

Change-Id: I8e867b311b485234ac457bf58fad1673892dfa6a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55823
Reviewed-by: Matthew Poremba 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/x86/isa/microops/regop.isa
1 file changed, 26 insertions(+), 7 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/x86/isa/microops/regop.isa  
b/src/arch/x86/isa/microops/regop.isa

index d56e17c..556a02c 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -1177,18 +1177,21 @@

 class Wrflags(WrRegOp):
 code = '''
-RegVal newFlags = PSrcReg1 ^ op2;
-RegVal userFlagMask = 0xDD5;
+const RegVal new_flags = PSrcReg1 ^ op2;

 // Get only the user flags
-ccFlagBits = newFlags & ccFlagMask;
-dfBit = newFlags & DFBit;
-cfofBits = newFlags & cfofMask;
+ccFlagBits = new_flags & ccFlagMask;
+dfBit = new_flags & DFBit;
+cfofBits = new_flags & cfofMask;
 ecfBit = 0;
 ezfBit = 0;

 // Get everything else
-nccFlagBits = newFlags & ~userFlagMask;
+const RegVal IOPLMask = mask(2) << 12;
+const RegVal SysFlagMask =
+TFBit | IFBit | IOPLMask | NTBit | RFBit | VMBit |
+ACBit | VIFBit | VIPBit | IDBit;
+nccFlagBits = new_flags & SysFlagMask;
 '''

 class Rdip(RdRegOp):
@@ -1200,7 +1203,7 @@
 class Rflags(RdRegOp):
 code = '''
 DestReg = ccFlagBits | cfofBits | dfBit |
-  ecfBit | ezfBit | nccFlagBits;
+  ecfBit | ezfBit | nccFlagBits | (1 << 1);
 '''

 class Ruflag(RegOp):

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8e867b311b485234ac457bf58fad1673892dfa6a
Gerrit-Change-Number: 55823
Gerrit-PatchSet: 13
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bradford Beckmann 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Use the right bits in the page table walker.

2022-03-14 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55812 )


 (

11 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-x86: Use the right bits in the page table walker.
..

arch-x86: Use the right bits in the page table walker.

In the section of the page table walker which processes a non-PAE,
non-PSE page directory entry, use the right bits of the virtual address
to figure out what to load next.

Change-Id: I7be3339c24253aa5594f564087eb9a234c370325
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55812
Reviewed-by: Matthew Poremba 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/x86/pagetable_walker.cc
1 file changed, 18 insertions(+), 1 deletion(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/x86/pagetable_walker.cc  
b/src/arch/x86/pagetable_walker.cc

index 47be278..78d10d0 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -477,7 +477,7 @@
 }
 // 4 KB page
 entry.logBytes = 12;
-nextRead = mbits(pte, 31, 12) + vaddr.norml2 * dataSize;
+nextRead = mbits(pte, 31, 12) + vaddr.norml1 * dataSize;
 nextState = PTE;
 break;
   case PTE:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7be3339c24253aa5594f564087eb9a234c370325
Gerrit-Change-Number: 55812
Gerrit-PatchSet: 14
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bradford Beckmann 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Tidy up the page table walker stepWalk method.

2022-03-14 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55811 )


 (

11 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-x86: Tidy up the page table walker stepWalk method.
..

arch-x86: Tidy up the page table walker stepWalk method.

Use the mbits function to avoid ugly manual masking and shifting. Also
remove some unnecessary casts when DPRINTF-ing PTEs.

Change-Id: I1cf7307760b2534e90bea1276110ecb005ec6471
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55811
Reviewed-by: Matthew Poremba 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/x86/pagetable_walker.cc
1 file changed, 45 insertions(+), 39 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/x86/pagetable_walker.cc  
b/src/arch/x86/pagetable_walker.cc

index 15c3a1e..47be278 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -299,9 +299,8 @@
 bool badNX = pte.nx && mode == BaseMMU::Execute && enableNX;
 switch(state) {
   case LongPML4:
-DPRINTF(PageTableWalker,
-"Got long mode PML4 entry %#016x.\n", (uint64_t)pte);
-nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl3 *  
dataSize;
+DPRINTF(PageTableWalker, "Got long mode PML4 entry %#016x.\n",  
pte);

+nextRead = mbits(pte, 51, 12) + vaddr.longl3 * dataSize;
 doWrite = !pte.a;
 pte.a = 1;
 entry.writable = pte.w;
@@ -315,9 +314,8 @@
 nextState = LongPDP;
 break;
   case LongPDP:
-DPRINTF(PageTableWalker,
-"Got long mode PDP entry %#016x.\n", (uint64_t)pte);
-nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl2 *  
dataSize;

+DPRINTF(PageTableWalker, "Got long mode PDP entry %#016x.\n", pte);
+nextRead = mbits(pte, 51, 12) + vaddr.longl2 * dataSize;
 doWrite = !pte.a;
 pte.a = 1;
 entry.writable = entry.writable && pte.w;
@@ -330,8 +328,7 @@
 nextState = LongPD;
 break;
   case LongPD:
-DPRINTF(PageTableWalker,
-"Got long mode PD entry %#016x.\n", (uint64_t)pte);
+DPRINTF(PageTableWalker, "Got long mode PD entry %#016x.\n", pte);
 doWrite = !pte.a;
 pte.a = 1;
 entry.writable = entry.writable && pte.w;
@@ -344,25 +341,23 @@
 if (!pte.ps) {
 // 4 KB page
 entry.logBytes = 12;
-nextRead =
-((uint64_t)pte & (mask(40) << 12)) + vaddr.longl1 *  
dataSize;

+nextRead = mbits(pte, 51, 12) + vaddr.longl1 * dataSize;
 nextState = LongPTE;
 break;
 } else {
 // 2 MB page
 entry.logBytes = 21;
-entry.paddr = (uint64_t)pte & (mask(31) << 21);
+entry.paddr = mbits(pte, 51, 21);
 entry.uncacheable = uncacheable;
 entry.global = pte.g;
 entry.patBit = bits(pte, 12);
-entry.vaddr = entry.vaddr & ~((2 * (1 << 20)) - 1);
+entry.vaddr = mbits(entry.vaddr, 63, 21);
 doTLBInsert = true;
 doEndWalk = true;
 break;
 }
   case LongPTE:
-DPRINTF(PageTableWalker,
-"Got long mode PTE entry %#016x.\n", (uint64_t)pte);
+DPRINTF(PageTableWalker, "Got long mode PTE entry %#016x.\n", pte);
 doWrite = !pte.a;
 pte.a = 1;
 entry.writable = entry.writable && pte.w;
@@ -372,18 +367,18 @@
 fault = pageFault(pte.p);
 break;
 }
-entry.paddr = (uint64_t)pte & (mask(40) << 12);
+entry.paddr = mbits(pte, 51, 12);
 entry.uncacheable = uncacheable;
 entry.global = pte.g;
 entry.patBit = bits(pte, 12);
-entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1);
+entry.vaddr = mbits(entry.vaddr, 63, 12);
 doTLBInsert = true;
 doEndWalk = true;
 break;
   case PAEPDP:
 DPRINTF(PageTableWalker,
-"Got legacy mode PAE PDP entry %#08x.\n", (uint32_t)pte);
-nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.pael2 *  
dataSize;

+"Got legacy mode PAE PDP entry %#08x.\n", pte);
+nextRead = mbits(pte, 51, 12) + vaddr.pael2 * dataSize;
 if (!pte.p) {
 doEndWalk = true;
 fault = pageFault(pte.p);
@@ -392,8 +387,7 @@
 nextState = PAEPD;
 break;
   case PAEPD:
-DPRINTF(PageTableWalker,
-"Got legacy mode PAE PD entry %#08x.\n", (uint32_t)pte);
+DPRINTF(PageTableWalker, "Got legacy mode PAE PD entry %#08x.\n",  
pte);

 doWrite = !pte.a;
 pte.a =

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Detect when entering virtual 8086 mode.

2022-03-14 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55810 )


 (

11 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-x86: Detect when entering virtual 8086 mode.
..

arch-x86: Detect when entering virtual 8086 mode.

If we're entering virtual 8086 mode, panic. Some aspects of that mode
may actually work, but since it's essentially untested, lets be extra
cautious.

Change-Id: I78bbfcb75db8370f4271c75caabc0ec53f75a884
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55810
Reviewed-by: Matthew Poremba 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/x86/isa.cc
1 file changed, 23 insertions(+), 0 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 713346e..f426137 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -318,6 +318,12 @@
 break;
   case MISCREG_CR8:
 break;
+  case MISCREG_RFLAGS:
+{
+RFLAGS rflags = val;
+panic_if(rflags.vm, "Virtual 8086 mode is not supported.");
+break;
+}
   case MISCREG_CS_ATTR:
 {
 SegAttr toggled = regVal[miscReg] ^ val;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I78bbfcb75db8370f4271c75caabc0ec53f75a884
Gerrit-Change-Number: 55810
Gerrit-PatchSet: 14
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bradford Beckmann 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fix writing back 32 bit PTEs in the walker.

2022-03-14 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55808 )


 (

11 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-x86: Fix writing back 32 bit PTEs in the walker.
..

arch-x86: Fix writing back 32 bit PTEs in the walker.

The page table walker might need to write back page table entries to set
their accessed bits. It was already checking whether the access was 32
or 64 bit when the PTE was retrieved from the incoming packet, but was
not checking the size when it was written back out, causing an assert to
fail when working with 32 bit legacy PTEs.

Change-Id: I7d02241cad20681e6cac0111edf2454335c466fa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55808
Reviewed-by: Matthew Poremba 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/x86/pagetable_walker.cc
1 file changed, 23 insertions(+), 1 deletion(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/x86/pagetable_walker.cc  
b/src/arch/x86/pagetable_walker.cc

index 5635895..15c3a1e 100644
--- a/src/arch/x86/pagetable_walker.cc
+++ b/src/arch/x86/pagetable_walker.cc
@@ -530,7 +530,10 @@
 // value back to memory.
 if (doWrite) {
 write = oldRead;
-write->setLE(pte);
+if (dataSize == 8)
+write->setLE(pte);
+else
+write->setLE(pte);
 write->cmd = MemCmd::WriteReq;
 } else {
 write = NULL;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7d02241cad20681e6cac0111edf2454335c466fa
Gerrit-Change-Number: 55808
Gerrit-PatchSet: 14
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bradford Beckmann 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fix a bug in the protected mode IRET.

2022-03-14 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55887 )


 (

10 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-x86: Fix a bug in the protected mode IRET.
..

arch-x86: Fix a bug in the protected mode IRET.

Fix the direction of the comparison which makes sure the new RIP will
fit within the new CS limit.

Change-Id: I3f3e66c185d0e1fbc430b0ae594d63cdd62b9dfd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55887
Reviewed-by: Matt Sinclair 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M  
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py

1 file changed, 17 insertions(+), 1 deletion(-)

Approvals:
  Matt Sinclair: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git  
a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py  
b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py

index 525279c..60d0086 100644
---  
a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
+++  
b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py

@@ -156,7 +156,7 @@
 # appropriate/other RIP checks.
 # if temp_RIP > CS.limit throw #GP(0)
 rdlimit t6, cs, dataSize=8
-sub t0, t1, t6, flags=(ECF,)
+sub t0, t6, t1, flags=(ECF,)
 fault "std::make_shared(0)", flags=(CECF,)

 #(temp_CPL!=CPL)

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3f3e66c185d0e1fbc430b0ae594d63cdd62b9dfd
Gerrit-Change-Number: 55887
Gerrit-PatchSet: 12
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bradford Beckmann 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem: Add setter for RequestorID in request

[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Add methods to read GPU memory requestor ID

[gem5-dev] Change in gem5/gem5[develop]: configs: Add GPU TLBs for GPU full system

[gem5-dev] Change in gem5/gem5[develop]: configs,gpu-compute: Support fetch from system pages

[gem5-dev] Change in gem5/gem5[develop]: fastmodel: CortexA76 fix missing registers for FastModel 11.17

[gem5-dev] Change in gem5/gem5[develop]: scons: Make all sticky variables automatically exported.

[gem5-dev] Change in gem5/gem5[develop]: ext,scons: Make kconfiglib available for use in SCons.

[gem5-dev] Change in gem5/gem5[develop]: util-docker: Add docker container for building riscv target

[gem5-dev] Change in gem5/gem5[develop]: arch: Make the DummyVec... types the same size as RegVal.

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fix the SAHF and LAHF instructions.

[gem5-dev] Change in gem5/gem5[develop]: dev-amdgpu: Handle framebuffer reads from device cache

[gem5-dev] Change in gem5/gem5[develop]: scons: Process the SConsopts files for each variant.

[gem5-dev] Change in gem5/gem5[develop]: scons: Turn a lot of compiler flag vars into env vars.

[gem5-dev] Change in gem5/gem5[develop]: dev,arch-x86: Make the I8042 reset settings more realistic.

[gem5-dev] Change in gem5/gem5[develop]: dev,arch-x86: Implement some self test 8042 commands.

[gem5-dev] Change in gem5/gem5[develop]: util: Remove util/cloudbuild

[gem5-dev] Change in gem5/gem5[develop]: tests,util-docker: Add clang-12 to the compiler tests

[gem5-dev] Change in gem5/gem5[develop]: util-docker: Adding docker-compose.yaml

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix setup of ESR.IL field

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix coding tyle of faults.{cc,hh}

[gem5-dev] Change in gem5/gem5[develop]: sim-se: Initialize shared page table base upon clone

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Make the flags microops handle reserved bits better.

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Use the right bits in the page table walker.

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Tidy up the page table walker stepWalk method.

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Detect when entering virtual 8086 mode.

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fix writing back 32 bit PTEs in the walker.

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Fix a bug in the protected mode IRET.

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