date:20220315

[gem5-dev] Re: Build failed in Jenkins: nightly #161

2022-03-15 Thread Gabe Black via gem5-dev

https://gem5-review.googlesource.com/c/public/gem5/+/57749

On Tue, Mar 15, 2022 at 12:59 PM Gabe Black  wrote:

> It looks like the problem is that the aapcs test calls ThreadContext which
> returns a TheISA::VecRegContainer, where since that test is for ARM it
> *should* really be working with an ARM VecRegContainer. Because this is
> being built for NULL, that uses the dummy versions which are not complete
> enough to have "as" template methods like the real classes.
>
> I think the solution is either to restrict that test to when building with
> ARM, or to add as<>() to the dummy classes. In the short term the offending
> change can be reverted, or we can wait until this evening when I'll have a
> chance to find a proper fix. This is what is right now probably a unique
> corner case where we have a unit test which is ISA dependent, and while it
> will *become* possible to run reasonably under any build once the
> ThreadContext doesn't build in what data type vector registers should be,
> in the mean time it either won't work because of this problem, or even when
> it would work, it would be operating on an inappropriate data type.
>
> Gabe
>
> On Tue, Mar 15, 2022 at 8:13 AM Jason Lowe-Power 
> wrote:
>
>> Looks like the problem is  [gabe.black] arch: Make the DummyVec... types
>> the same size as RegVal.
>>
>> Can you take a look, Gabe?
>>
>> Thanks,
>> Jason
>>
>> On Tue, Mar 15, 2022 at 1:46 AM jenkins-no-reply--- via gem5-dev <
>> gem5-dev@gem5.org> wrote:
>>
>>> See <
>>> https://jenkins.gem5.org/job/nightly/161/display/redirect?page=changes>
>>>
>>> Changes:
>>>
>>> [gabe.black] arch-x86: Fix a bug in the protected mode IRET.
>>>
>>> [gabe.black] arch-x86: Fix writing back 32 bit PTEs in the walker.
>>>
>>> [gabe.black] arch-x86: Detect when entering virtual 8086 mode.
>>>
>>> [gabe.black] arch-x86: Tidy up the page table walker stepWalk method.
>>>
>>> [gabe.black] arch-x86: Use the right bits in the page table walker.
>>>
>>> [gabe.black] arch-x86: Make the flags microops handle reserved bits
>>> better.
>>>
>>> [matthew.poremba] sim-se: Initialize shared page table base upon clone
>>>
>>> [Bobby R. Bruce] util-docker: Adding docker-compose.yaml
>>>
>>> [Bobby R. Bruce] tests,util-docker: Add clang-12 to the compiler tests
>>>
>>> [Bobby R. Bruce] util: Remove util/cloudbuild
>>>
>>> [gabe.black] dev,arch-x86: Make the I8042 reset settings more realistic.
>>>
>>> [gabe.black] dev,arch-x86: Implement some self test 8042 commands.
>>>
>>> [gabe.black] scons: Process the SConsopts files for each variant.
>>>
>>> [gabe.black] scons: Turn a lot of compiler flag vars into env vars.
>>>
>>> [gabe.black] arch-x86: Fix the SAHF and LAHF instructions.
>>>
>>> [gabe.black] arch: Make the DummyVec... types the same size as RegVal.
>>>
>>> [gabe.black] ext,scons: Make kconfiglib available for use in SCons.
>>>
>>> [gabe.black] scons: Make all sticky variables automatically exported.
>>>
>>> [gabe.black] dev: Implement PS/2 keyboard echo and set scan code
>>> commands.
>>>
>>> [gabe.black] arch-x86: Specialize some instructions for virtual 8086
>>> mode.
>>>
>>>
>>> --
>>> [...truncated 1.17 MB...]
>>> [ RUN  ] LoggingFixture.Warn
>>> [   OK ] LoggingFixture.Warn (0 ms)
>>> [ RUN  ] LoggingFixture.Inform
>>> [   OK ] LoggingFixture.Inform (0 ms)
>>> [ RUN  ] LoggingFixture.Hack
>>> [   OK ] LoggingFixture.Hack (0 ms)
>>> [ RUN  ] LoggingFixture.WarnOnce
>>> [   OK ] LoggingFixture.WarnOnce (0 ms)
>>> [ RUN  ] LoggingFixture.InformOnce
>>> [   OK ] LoggingFixture.InformOnce (0 ms)
>>> [ RUN  ] LoggingFixture.HackOnce
>>> [   OK ] LoggingFixture.HackOnce (0 ms)
>>> [ RUN  ] LoggingFixture.WarnIf
>>> [   OK ] LoggingFixture.WarnIf (0 ms)
>>> [ RUN  ] LoggingFixture.WarnIfOnce
>>> [   OK ] LoggingFixture.WarnIfOnce (0 ms)
>>> [--] 21 tests from LoggingFixture (0 ms total)
>>>
>>> [--] Global test environment tear-down
>>> [==] 34 tests from 2 test suites ran. (1638 ms total)
>>> [  PASSED  ] 34 tests.
>>>  [LINK]  -> NULL/arch/generic/vec_pred_reg.test.opt
>>> build/NULL/arch/generic/vec_reg.test.opt
>>> --gtest_output=xml:build/NULL/unittests.opt/arch/generic/vec_reg.test.xml
>>> Running main() from
>>> build/NULL/ext/googletest/googletest/src/gtest_main.cc
>>> [==] Running 8 tests from 2 test suites.
>>> [--] Global test environment set-up.
>>> [--] 2 tests from VecReg
>>> [ RUN  ] VecReg.Size
>>> [   OK ] VecReg.Size (0 ms)
>>> [ RUN  ] VecReg.Zero
>>> [   OK ] VecReg.Zero (0 ms)
>>> [--] 2 tests from VecReg (0 ms total)
>>>
>>> [--] 6 tests from TwoDifferentVecRegs
>>> [ RUN  ] TwoDifferentVecRegs.Assignment
>>> [   OK ] TwoDifferentVecRegs.Assignment (0 ms)
>>> [ RUN  ] TwoDifferentVecRegs.Equality
>>> [   OK ] TwoDifferentVecRegs.Equality (0 ms)
>>> [ RUN  ] TwoDifferentVecRegs.Inequality
>>> [

[gem5-dev] Change in gem5/gem5[develop]: base: zero initialize the underlying storage of bitunion

2022-03-15 Thread Yu-hsin Wang (Gerrit) via gem5-dev

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57730 )



Change subject: base: zero initialize the underlying storage of bitunion
..

base: zero initialize the underlying storage of bitunion

To make the simulation result deterministic, we should make sure
everything is initiaized in a good state. In addition, this change
wouldn't break anything, since the original initial value is a random
value.

Change-Id: Icbed36b3fa6751cbda63e84443eaab6d865d9bd6
---
M src/base/bitunion.hh
1 file changed, 18 insertions(+), 1 deletion(-)



diff --git a/src/base/bitunion.hh b/src/base/bitunion.hh
index 92d747c..1fc0a94 100644
--- a/src/base/bitunion.hh
+++ b/src/base/bitunion.hh
@@ -261,7 +261,10 @@

 BitUnionOperators(const BitUnionOperators &) = default;

-BitUnionOperators() {}
+BitUnionOperators()
+{
+Base::__storage = {};
+}

 //Conversion operators.
 operator const typename Base::__StorageType () const

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icbed36b3fa6751cbda63e84443eaab6d865d9bd6
Gerrit-Change-Number: 57730
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem: Add SharedMemoryServer

2022-03-15 Thread Jui-min Lee (Gerrit) via gem5-dev

Jui-min Lee has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57729 )



Change subject: mem: Add SharedMemoryServer
..

mem: Add SharedMemoryServer

Add an utility class that provides a service for another process
query and get the fd of the corresponding region in gem5's physmem.

We also add a new option in System.py so people can specify the path of
the unix socket providing such service.

Basically, the service works in this way:
1. client connect to the unix socket created by a gem5 system
2. client send a request {start, end} to gem5
3. the system locates the corresponding shared memory
4. gem5 response {offset} and pass {fd} in ancillary data

mmap fd at offset will provide the client the view into the physical
memory of the request range.

Bug: 222145732
Test: None
Change-Id: I9d42fd8a41fc28dcfebb45dec10bc9ebb8e21d11
---
M src/base/socket.hh
M src/mem/SConscript
M src/mem/physical.cc
M src/mem/physical.hh
A src/mem/shared_memory_server.cc
A src/mem/shared_memory_server.hh
M src/sim/System.py
M src/sim/system.cc
M src/sim/system.hh
9 files changed, 356 insertions(+), 11 deletions(-)



diff --git a/src/base/socket.hh b/src/base/socket.hh
index 4ed6185..3375ccc 100644
--- a/src/base/socket.hh
+++ b/src/base/socket.hh
@@ -62,14 +62,6 @@
  */
 static void cleanup();

-  private:
-/* Create a socket, adding SOCK_CLOEXEC if available. */
-static int socketCloexec(int domain, int type, int protocol);
-/* Accept a connection, adding SOCK_CLOEXEC if available. */
-static int acceptCloexec(int sockfd, struct sockaddr *addr,
-  socklen_t *addrlen);
-
-
   public:
 /**
  * @ingroup api_socket
@@ -84,6 +76,12 @@

 int getfd() const { return fd; }
 bool islistening() const { return listening; }
+
+/* Create a socket, adding SOCK_CLOEXEC if available. */
+static int socketCloexec(int domain, int type, int protocol);
+/* Accept a connection, adding SOCK_CLOEXEC if available. */
+static int acceptCloexec(int sockfd, struct sockaddr *addr,
+  socklen_t *addrlen);
 /** @} */ // end of api_socket
 };

diff --git a/src/mem/SConscript b/src/mem/SConscript
index 7790e1d..c0cc4d7 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -80,6 +80,7 @@
 Source('packet_queue.cc')
 Source('port_proxy.cc')
 Source('physical.cc')
+Source('shared_memory_server.cc')
 Source('simple_mem.cc')
 Source('snoop_filter.cc')
 Source('stack_dist_calc.cc')
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index ebc9ca8..c012ef7 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -248,7 +248,8 @@
 // remember this backing store so we can checkpoint it and unmap
 // it appropriately
 backingStore.emplace_back(range, pmem,
-  conf_table_reported, in_addr_map, kvm_map);
+  conf_table_reported, in_addr_map, kvm_map,
+  shm_fd, map_offset);

 // point the memories to their backing store
 for (const auto& m : _memories) {
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index ff0dc61..37bcd46 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -70,9 +70,11 @@
  * pointers, because PhysicalMemory is responsible for that.
  */
 BackingStoreEntry(AddrRange range, uint8_t* pmem,
-  bool conf_table_reported, bool in_addr_map, bool  
kvm_map)
+  bool conf_table_reported, bool in_addr_map, bool  
kvm_map,

+  int shm_fd, off_t shm_offset)
 : range(range), pmem(pmem), confTableReported(conf_table_reported),
-  inAddrMap(in_addr_map), kvmMap(kvm_map)
+  inAddrMap(in_addr_map), kvmMap(kvm_map), shmFd(shm_fd),
+  shmOffset(shm_offset)
 {}

 /**
@@ -101,6 +103,19 @@
   * acceleration.
   */
  bool kvmMap;
+
+ /**
+  * If this backing store is based on a shared memory, this is the fd  
to

+  * the shared memory. Otherwise, it should be -1.
+  */
+ int shmFd;
+
+ /**
+  * If this backing store is based on a shared memory, this is the  
offset

+  * of this backing store in the share memory. Otherwise, the value is
+  * unspecified and should not be rely upon.
+  */
+ off_t shmOffset;
 };

 /**
diff --git a/src/mem/shared_memory_server.cc  
b/src/mem/shared_memory_server.cc

new file mode 100644
index 000..3b78527
--- /dev/null
+++ b/src/mem/shared_memory_server.cc
@@ -0,0 +1,206 @@
+/*
+ * Copyright 2022 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in

[gem5-dev] Change in gem5/gem5[develop]: util-docker: Add docker container for building riscv target

2022-03-15 Thread Hoa Nguyen (Gerrit) via gem5-dev

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57609 )


Change subject: util-docker: Add docker container for building riscv target
..

util-docker: Add docker container for building riscv target

This container comes with LLVM/Clang riscv cross-compiler
with linker, libraries, and libc headers from
riscv-gnu-toolchain[1].

Adapted from [2].

[1] https://github.com/lowRISC/riscv-llvm
[2] https://github.com/sifive/riscv-llvm/blob/dev/README.md

Signed-off-by: Hoa Nguyen 
Change-Id: I0bc310e1ae3ca9257fbde95a864c2b48009cd897
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57609
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M util/dockerfiles/docker-compose.yaml
A util/dockerfiles/llvm-gnu-cross-compiler-riscv64/Dockerfile
2 files changed, 102 insertions(+), 1 deletion(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/util/dockerfiles/docker-compose.yaml  
b/util/dockerfiles/docker-compose.yaml

index bcae58a..cbc8987 100644
--- a/util/dockerfiles/docker-compose.yaml
+++ b/util/dockerfiles/docker-compose.yaml
@@ -110,4 +110,8 @@
 args:
 - version=12
 image: gcr.io/gem5-test/clang-version-12
-
+llvm-gnu-cross-compiler-riscv64:
+build:
+context: llvm-gnu-cross-compiler-riscv64
+dockerfile: Dockerfile
+image: gcr.io/gem5-test/llvm-gnu-cross-compiler-riscv64
diff --git a/util/dockerfiles/llvm-gnu-cross-compiler-riscv64/Dockerfile  
b/util/dockerfiles/llvm-gnu-cross-compiler-riscv64/Dockerfile

new file mode 100644
index 000..ed06bf7
--- /dev/null
+++ b/util/dockerfiles/llvm-gnu-cross-compiler-riscv64/Dockerfile
@@ -0,0 +1,74 @@
+# Copyright (c) 2022 The Regents of the University of California
+# All Rights Reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+# stage 1: download the dependencies
+FROM ubuntu:20.04 AS stage1
+
+ENV DEBIAN_FRONTEND=noninteractive
+RUN apt -y update
+RUN apt -y upgrade
+RUN apt -y install \
+  binutils build-essential libtool texinfo gzip zip unzip patchutils curl  
git \

+  make cmake ninja-build automake bison flex gperf grep sed gawk bc \
+  zlib1g-dev libexpat1-dev libmpc-dev libglib2.0-dev libfdt-dev  
libpixman-1-dev

+
+# stage 2: download the compilers and compile them
+FROM stage1 AS stage2
+RUN mkdir -p /riscv/_install
+WORKDIR /riscv
+ENV PATH=`/riscv/_install/bin:$PATH`
+RUN git clone --recursive https://github.com/riscv/riscv-gnu-toolchain
+WORKDIR /riscv/riscv-gnu-toolchain
+RUN git checkout --recurse-submodules  
051b9f7ddb7d136777505ea19c70a41926842b96

+RUN ./configure --prefix=/riscv/_install --enable-multilib
+RUN make linux -j`nproc`
+RUN make install
+
+WORKDIR /riscv
+RUN git clone https://github.com/llvm/llvm-project.git riscv-llvm
+WORKDIR /riscv/riscv-llvm
+RUN git checkout 2ef95efb414e215490a222de05cafdffb8054758
+RUN ln -s ../../clang llvm/tools || true
+RUN mkdir _build
+WORKDIR /riscv/riscv-llvm/_build
+RUN cmake -G Ninja -DCMAKE_BUILD_TYPE="Release" \
+  -DBUILD_SHARED_LIBS=True -DLLVM_USE_SPLIT_DWARF=True \
+  -DCMAKE_INSTALL_PREFIX="/riscv/_install" \
+  -DLLVM_OPTIMIZED_TABLEGEN=True -DLLVM_BUILD_TESTS=False \
+  -DDEFAULT_SYSROOT="/riscv/_install/sysroot" \
+  -DLLVM_DEFAULT_TARGET_TRIPLE="riscv64-unknown-linux-gnu" \
+  -DLLVM_TARGETS_TO_BUILD="RISCV" \
+  ../llvm
+RUN cmake --build . --target install -j`nproc`

[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Don't use emulated driver in full system

2022-03-15 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57712 )



Change subject: gpu-compute: Don't use emulated driver in full system
..

gpu-compute: Don't use emulated driver in full system

The emulated driver is currently called in a few locations
unconditionally. This changeset adds checks that we are not in full
system before calling any emulated driver function. In full system the
amdgpu driver running on the disk image handles these functions.

Change-Id: Iea3546b574e29c649351c0fce9154530be89e9b1
---
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/gpu_compute_driver.cc
2 files changed, 23 insertions(+), 3 deletions(-)



diff --git a/src/gpu-compute/compute_unit.cc  
b/src/gpu-compute/compute_unit.cc

index b9c14f9..6186fef 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -1051,13 +1051,18 @@
 // only do some things if actually accessing data
 bool isDataAccess = pkt->isWrite() || pkt->isRead();

-// For dGPUs, real hardware will extract MTYPE from the PTE.  Our model
+// For dGPUs, real hardware will extract MTYPE from the PTE. SE mode
 // uses x86 pagetables which don't have fields to track GPU MTYPEs.
 // Rather than hacking up the pagetable to add these bits in, we just
 // keep a structure local to our GPUs that are populated in our
 // emulated driver whenever memory is allocated.  Consult that  
structure

 // here in case we need a memtype override.
-shader->gpuCmdProc.driver()->setMtype(pkt->req);
+//
+// In full system mode these can be extracted from the PTE and assigned
+// after address translation takes place.
+if (!FullSystem) {
+shader->gpuCmdProc.driver()->setMtype(pkt->req);
+}

 // Check write before read for atomic operations
 // since atomic operations should use BaseMMU::Write
@@ -1075,7 +1080,7 @@
 PortID tlbPort_index = perLaneTLB ? index : 0;

 if (shader->timingSim) {
-if (debugSegFault) {
+if (!FullSystem && debugSegFault) {
 Process *p = shader->gpuTc->getProcessPtr();
 Addr vaddr = pkt->req->getVaddr();
 unsigned size = pkt->getSize();
diff --git a/src/gpu-compute/gpu_compute_driver.cc  
b/src/gpu-compute/gpu_compute_driver.cc

index ca870aa..203d087 100644
--- a/src/gpu-compute/gpu_compute_driver.cc
+++ b/src/gpu-compute/gpu_compute_driver.cc
@@ -1023,6 +1023,7 @@
 {
 // If we are a dGPU then set the MTYPE from our VMAs.
 if (isdGPU) {
+assert(!FullSystem);
 AddrRange range = RangeSize(req->getVaddr(), req->getSize());
 auto vma = gpuVmas.contains(range);
 assert(vma != gpuVmas.end());

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iea3546b574e29c649351c0fce9154530be89e9b1
Gerrit-Change-Number: 57712
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Command processor read path from device

2022-03-15 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57710 )



Change subject: gpu-compute: Command processor read path from device
..

gpu-compute: Command processor read path from device

In full system mode, the AMDKernelCode object can reside in either the
system memory or in the dGPU device memory. Currently only reading from
the host/system memory is supported. This adds the necessary code to
read from the dGPU device memory.

Change-Id: I887fc706b3f9834db14e40f36fd29dd3d4602925
---
M src/gpu-compute/gpu_command_processor.cc
1 file changed, 65 insertions(+), 7 deletions(-)



diff --git a/src/gpu-compute/gpu_command_processor.cc  
b/src/gpu-compute/gpu_command_processor.cc

index 0e2ff50..1322130 100644
--- a/src/gpu-compute/gpu_command_processor.cc
+++ b/src/gpu-compute/gpu_command_processor.cc
@@ -39,6 +39,8 @@
 #include "debug/GPUKernelInfo.hh"
 #include "dev/amdgpu/amdgpu_device.hh"
 #include "gpu-compute/dispatcher.hh"
+#include "mem/abstract_mem.hh"
+#include "mem/packet_access.hh"
 #include "mem/se_translating_port_proxy.hh"
 #include "mem/translating_port_proxy.hh"
 #include "params/GPUCommandProcessor.hh"
@@ -77,12 +79,20 @@
 TranslationGenPtr
 GPUCommandProcessor::translate(Addr vaddr, Addr size)
 {
-// Grab the process and try to translate the virtual address with it;  
with
-// new extensions, it will likely be wrong to just arbitrarily grab  
context

-// zero.
-auto process = sys->threads[0]->getProcessPtr();
+if (!FullSystem) {
+// Grab the process and try to translate the virtual address with  
it;

+// with new extensions, it will likely be wrong to just arbitrarily
+// grab context zero.
+auto process = sys->threads[0]->getProcessPtr();

-return process->pTable->translateRange(vaddr, size);
+return process->pTable->translateRange(vaddr, size);
+}
+
+// In full system use the page tables setup by the kernel driver rather
+// than the CPU page tables.
+return TranslationGenPtr(
+new AMDGPUVM::UserTranslationGen(>getVM(), walker,
+ 1 /* vmid */, vaddr, size));
 }

 /**
@@ -120,6 +130,20 @@
 PortProxy _proxy = FullSystem ? fs_proxy : se_proxy;

 /**
+ * In full system mode, the page table entry may point to a system page
+ * or a device page. System pages use the proxy as normal, but a device
+ * page needs to be read from device memory. Check what type it is  
here.

+ */
+bool is_system_page = true;
+Addr phys_addr = disp_pkt->kernel_object;
+if (FullSystem) {
+unsigned tmp_bytes;
+walker->startFunctional(gpuDevice->getVM().getPageTableBase(1),
+phys_addr, tmp_bytes, BaseMMU::Mode::Read,
+is_system_page);
+}
+
+/**
  * The kernel_object is a pointer to the machine code, whose entry
  * point is an 'amd_kernel_code_t' type, which is included in the
  * kernel binary, and describes various aspects of the kernel. The
@@ -129,8 +153,28 @@
  * instructions.
  */
 AMDKernelCode akc;
-virt_proxy.readBlob(disp_pkt->kernel_object, (uint8_t*),
-sizeof(AMDKernelCode));
+if (is_system_page) {
+DPRINTF(GPUCommandProc, "kernel_object in system, using proxy\n");
+virt_proxy.readBlob(disp_pkt->kernel_object, (uint8_t*),
+sizeof(AMDKernelCode));
+} else {
+assert(FullSystem);
+DPRINTF(GPUCommandProc, "kernel_object in device, using device  
mem\n");

+// Read from GPU memory manager
+uint8_t raw_akc[sizeof(AMDKernelCode)];
+for (int i = 0; i < sizeof(AMDKernelCode) / sizeof(uint8_t); ++i) {
+Addr mmhubAddr = phys_addr + i*sizeof(uint8_t);
+Request::Flags flags = Request::PHYSICAL;
+RequestPtr request = std::make_shared(
+mmhubAddr, sizeof(uint8_t), flags,  
walker->getDevRequestor());

+Packet *readPkt = new Packet(request, MemCmd::ReadReq);
+readPkt->allocate();
+system()->getDeviceMemory(readPkt)->access(readPkt);
+raw_akc[i] = readPkt->getLE();
+delete readPkt;
+}
+memcpy(, _akc, sizeof(AMDKernelCode));
+}

 DPRINTF(GPUCommandProc, "GPU machine code is %lli bytes from start of  
the "

 "kernel object\n", akc.kernel_code_entry_byte_offset);

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[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Support Scalar and Vector access to system pages

2022-03-15 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57711 )



Change subject: gpu-compute: Support Scalar and Vector access to system  
pages

..

gpu-compute: Support Scalar and Vector access to system pages

The amdgpu driver supports reading and writing scalar and vector memory
addresses that reside in system memory. This is commonly used for things
like blit kernels that perform host-to-device or device-to-host copies
using GPU load/store instructions.

This is done by utilizing the system hub device added in a prior
changeset. Memory packets translated by the Scalar or VMEM TLBs will
have the correspoding system request field set from the PTE in the TLB
which can be used in the compute unit to determine if a request is for
system memory or not.

Another important change is to return global memory tokens for system
requests. Since these do not flow through the GPU coalescer where the
token is returned, the token can be returned once the request is known
to be a system request.

Change-Id: I35030e0b3698f10c63a397f96b81267271e3130e
---
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/compute_unit.hh
M src/gpu-compute/global_memory_pipeline.cc
M src/gpu-compute/gpu_dyn_inst.hh
4 files changed, 150 insertions(+), 9 deletions(-)



diff --git a/src/gpu-compute/compute_unit.cc  
b/src/gpu-compute/compute_unit.cc

index b40b464..b9c14f9 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -112,6 +112,12 @@
 scheduleToExecute(p),
 stats(this, p.n_wf)
 {
+// This is not currently supported and would require adding more  
handling

+// for system vs. device memory requests on the functional paths, so we
+// fatal immediately in the constructor if this configuration is seen.
+fatal_if(functionalTLB && FullSystem,
+ "Functional TLB not supported in full-system GPU simulation");
+
 /**
  * This check is necessary because std::bitset only provides conversion
  * to unsigned long or unsigned long long via to_ulong() or  
to_ullong().

@@ -801,6 +807,12 @@
 bool
 ComputeUnit::DataPort::recvTimingResp(PacketPtr pkt)
 {
+return handleResponse(pkt);
+}
+
+bool
+ComputeUnit::DataPort::handleResponse(PacketPtr pkt)
+{
 // Ruby has completed the memory op. Schedule the mem_resp_event at the
 // appropriate cycle to process the timing memory response
 // This delay represents the pipeline delay
@@ -902,6 +914,12 @@
 bool
 ComputeUnit::ScalarDataPort::recvTimingResp(PacketPtr pkt)
 {
+return handleResponse(pkt);
+}
+
+bool
+ComputeUnit::ScalarDataPort::handleResponse(PacketPtr pkt)
+{
 assert(!pkt->req->isKernel());

 // retrieve sender state
@@ -1241,9 +1259,13 @@
 assert(gpuDynInst->isGlobalSeg() ||
gpuDynInst->executedAs() == enums::SC_GLOBAL);

+// Fences will never be issued to system memory, so we can mark the
+// requestor as a device memory ID here.
 if (!req) {
 req = std::make_shared(
-0, 0, 0, requestorId(), 0, gpuDynInst->wfDynId);
+0, 0, 0, vramRequestorId(), 0, gpuDynInst->wfDynId);
+} else {
+req->requestorId(vramRequestorId());
 }

 // all mem sync requests have Paddr == 0
@@ -1544,6 +1566,24 @@
 new ComputeUnit::DataPort::SenderState(gpuDynInst, mp_index,
nullptr);

+// Set VRAM ID for device requests
+// For now, system vmem requests use functional reads. This is not that
+// critical to model as the region of interest should always be  
accessing

+// device memory. System vmem requests are used by blit kernels to do
+// memcpys and load code objects into device memory.
+if (new_pkt->req->systemReq()) {
+// There will be multiple packets returned for the same gpuDynInst,
+// so first check if systemReq is not already set and if so, return
+// the token acquired when the dispatch list is filled as system
+// requests do not require a GPU coalescer token.
+if (!gpuDynInst->isSystemReq()) {
+computeUnit->getTokenManager()->recvTokens(1);
+gpuDynInst->setSystemReq();
+}
+} else {
+new_pkt->req->requestorId(computeUnit->vramRequestorId());
+}
+
 // translation is done. Schedule the mem_req_event at the appropriate
 // cycle to send the timing memory request to ruby
 EventFunctionWrapper *mem_req_event =
@@ -1582,7 +1622,11 @@
 GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst;
 [[maybe_unused]] ComputeUnit *compute_unit = computeUnit;

-if (!(sendTimingReq(pkt))) {
+if (pkt->req->systemReq()) {
+assert(compute_unit->shader->systemHub);
+SystemHubEvent *resp_event = new SystemHubEvent(pkt, this);
+compute_unit->shader->systemHub->sendRequest(pkt, resp_event);
+} else

[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Handle mailbox/wakeup signals for GPUFS

2022-03-15 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57709 )



Change subject: gpu-compute: Handle mailbox/wakeup signals for GPUFS
..

gpu-compute: Handle mailbox/wakeup signals for GPUFS

The current mailbox/wakeup signal uses the SE mode proxy port to write
the event value. This is not available in full system mode so instead we
need to issue a DMA write to the address. The value of 0 seems to be
correct based on many tests.

Change-Id: I424469076e87e690ab0bb722bac4c3e7414fb150
---
M src/gpu-compute/gpu_command_processor.cc
1 file changed, 21 insertions(+), 1 deletion(-)



diff --git a/src/gpu-compute/gpu_command_processor.cc  
b/src/gpu-compute/gpu_command_processor.cc

index 0f74cb1..0e2ff50 100644
--- a/src/gpu-compute/gpu_command_processor.cc
+++ b/src/gpu-compute/gpu_command_processor.cc
@@ -224,7 +224,13 @@

 DPRINTF(GPUCommandProc, "Calling signal wakeup event on "
 "signal event value %d\n", *event_val);
-signalWakeupEvent(*event_val);
+
+if (FullSystem) {
+auto cb = new DmaVirtCallback(function, 0);
+dmaWriteVirt(mailbox_addr, sizeof(Addr), cb, >dmaBuffer,  
0);

+} else {
+signalWakeupEvent(*event_val);
+}
 }
 }


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[gem5-dev] Change in gem5/gem5[develop]: stdlib: Add the MinorCPU type to the stdlib

2022-03-15 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57689 )



Change subject: stdlib: Add the MinorCPU type to the stdlib
..

stdlib: Add the MinorCPU type to the stdlib

Issue-on: https://gem5.atlassian.net/browse/GEM5-1161
Change-Id: I849f164bb33bde9e5d29bbd1d8c74a9193d29daf
---
M src/python/gem5/components/processors/abstract_core.py
M src/python/gem5/components/processors/cpu_types.py
M src/python/gem5/components/processors/simple_processor.py
3 files changed, 14 insertions(+), 2 deletions(-)



diff --git a/src/python/gem5/components/processors/abstract_core.py  
b/src/python/gem5/components/processors/abstract_core.py

index 7d4fa77..4da26bf 100644
--- a/src/python/gem5/components/processors/abstract_core.py
+++ b/src/python/gem5/components/processors/abstract_core.py
@@ -136,7 +136,8 @@
 CPUTypes.ATOMIC : "AtomicSimpleCPU",
 CPUTypes.O3 : "O3CPU",
 CPUTypes.TIMING : "TimingSimpleCPU",
-CPUTypes.KVM : "KvmCPU"
+CPUTypes.KVM : "KvmCPU",
+CPUTypes.MINOR : "MinorCPU",
 }

 if isa not in _isa_string_map:
diff --git a/src/python/gem5/components/processors/cpu_types.py  
b/src/python/gem5/components/processors/cpu_types.py

index 6e71dcc..831fe1d 100644
--- a/src/python/gem5/components/processors/cpu_types.py
+++ b/src/python/gem5/components/processors/cpu_types.py
@@ -32,3 +32,4 @@
 KVM = 2
 O3 = 3
 TIMING = 4
+MINOR = 5
diff --git a/src/python/gem5/components/processors/simple_processor.py  
b/src/python/gem5/components/processors/simple_processor.py

index d4dd85d..3c9c5c8 100644
--- a/src/python/gem5/components/processors/simple_processor.py
+++ b/src/python/gem5/components/processors/simple_processor.py
@@ -92,7 +92,7 @@
 board.kvm_vm = self.kvm_vm

 # Set the memory mode.
-if self._cpu_type == CPUTypes.TIMING or self._cpu_type ==  
CPUTypes.O3:
+if self._cpu_type in (CPUTypes.TIMING, CPUTypes.O3,  
CPUTypes.MINOR):

 board.set_mem_mode(MemMode.TIMING)
 elif self._cpu_type == CPUTypes.KVM:
 board.set_mem_mode(MemMode.ATOMIC_NONCACHING)

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Gerrit-Owner: Bobby Bruce 
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[gem5-dev] Change in gem5/gem5[develop]: tests: Add MinorCPU tests to the RISCV Boot tests

2022-03-15 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57691 )



Change subject: tests: Add MinorCPU tests to the RISCV Boot tests
..

tests: Add MinorCPU tests to the RISCV Boot tests

Change-Id: I9bd6665af00ea8a348152b5f5f83ff1017da4c7a
---
M tests/gem5/configs/riscv_boot_exit_run.py
M tests/gem5/riscv-boot-tests/test_linux_boot.py
2 files changed, 50 insertions(+), 1 deletion(-)



diff --git a/tests/gem5/configs/riscv_boot_exit_run.py  
b/tests/gem5/configs/riscv_boot_exit_run.py

index a06a45b..fd57e45 100644
--- a/tests/gem5/configs/riscv_boot_exit_run.py
+++ b/tests/gem5/configs/riscv_boot_exit_run.py
@@ -60,7 +60,7 @@
 "-c",
 "--cpu",
 type=str,
-choices=("kvm", "atomic", "timing", "o3"),
+choices=("kvm", "atomic", "timing", "o3", "minor"),
 required=True,
 help="The CPU type.",
 )
@@ -139,6 +139,8 @@
 cpu_type = CPUTypes.TIMING
 elif args.cpu == "o3":
 cpu_type = CPUTypes.O3
+elif args.cpu == "minor":
+cpu_type = CPUTypes.MINOR
 else:
 raise NotImplementedError(
 "CPU type '{}' is not supported in the boot  
tests.".format(args.cpu)
diff --git a/tests/gem5/riscv-boot-tests/test_linux_boot.py  
b/tests/gem5/riscv-boot-tests/test_linux_boot.py

index 6d4e9f1..e39c409 100644
--- a/tests/gem5/riscv-boot-tests/test_linux_boot.py
+++ b/tests/gem5/riscv-boot-tests/test_linux_boot.py
@@ -112,6 +112,44 @@
 )

 test_boot(
+cpu="minor",
+num_cpus=1,
+cache_type="classic",
+memory_class="SingleChannelDDR3_2133",
+length=constants.quick_tag,
+to_tick=100,
+)
+
+test_boot(
+cpu="minor",
+num_cpus=4,
+cache_type="classic",
+memory_class="SingleChannelDDR3_2133",
+length=constants.quick_tag,
+to_tick=100,
+)
+
+test_boot(
+cpu="minor",
+num_cpus=1,
+cache_type="mi_example",
+memory_class="SingleChannelDDR3_2133",
+length=constants.quick_tag,
+to_tick=100,
+)
+
+test_boot(
+cpu="minor",
+num_cpus=8,
+cache_type="mi_example",
+memory_class="SingleChannelDDR3_2133",
+length=constants.quick_tag,
+to_tick=100,
+)
+
+
+
+test_boot(
 cpu="timing",
 num_cpus=1,
 cache_type="mi_example",

--
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[gem5-dev] Change in gem5/gem5[develop]: tests: Add MinorCPU tests to Hello World tests

2022-03-15 Thread Bobby Bruce (Gerrit) via gem5-dev

Bobby Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57690 )



Change subject: tests: Add MinorCPU tests to Hello World tests
..

tests: Add MinorCPU tests to Hello World tests

At present, only the ARM and RISCV gem5 binaries support the MinorCPU by
default. Therefore, that is all that is tested for now.

Change-Id: I7cbcd2ee8cae470a3de0d59af20dc2fd911fb2bd
---
M tests/gem5/configs/simple_binary_run.py
M tests/gem5/hello_se/test_hello_se.py
2 files changed, 17 insertions(+), 3 deletions(-)



diff --git a/tests/gem5/configs/simple_binary_run.py  
b/tests/gem5/configs/simple_binary_run.py

index 51553df..7336865 100644
--- a/tests/gem5/configs/simple_binary_run.py
+++ b/tests/gem5/configs/simple_binary_run.py
@@ -55,7 +55,7 @@
 parser.add_argument(
 "cpu",
 type=str,
-choices=("kvm", "timing", "atomic", "o3"),
+choices=("kvm", "timing", "atomic", "o3", "minor"),
 help="The CPU type used.",
 )

@@ -103,6 +103,8 @@
 return CPUTypes.ATOMIC
 elif input == "o3":
 return CPUTypes.O3
+elif input == "minor":
+return CPUTypes.MINOR
 else:
 raise NotADirectoryError("Unknown CPU type '{}'.".format(input))

diff --git a/tests/gem5/hello_se/test_hello_se.py  
b/tests/gem5/hello_se/test_hello_se.py

index 115b396..e1e6aaf 100644
--- a/tests/gem5/hello_se/test_hello_se.py
+++ b/tests/gem5/hello_se/test_hello_se.py
@@ -72,9 +72,9 @@

 cpu_types = {
 constants.gcn3_x86_tag: ("timing", "atomic", "o3"),
-constants.arm_tag: ("timing", "atomic", "o3"),
+constants.arm_tag: ("timing", "atomic", "o3", "minor"),
 constants.mips_tag: ("timing", "atomic", "o3"),
-constants.riscv_tag: ("timing", "atomic", "o3"),
+constants.riscv_tag: ("timing", "atomic", "o3", "minor"),
 constants.sparc_tag: ("timing", "atomic"),
 }


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[gem5-dev] Re: Build failed in Jenkins: nightly #161

2022-03-15 Thread Gabe Black via gem5-dev

It looks like the problem is that the aapcs test calls ThreadContext which
returns a TheISA::VecRegContainer, where since that test is for ARM it
*should* really be working with an ARM VecRegContainer. Because this is
being built for NULL, that uses the dummy versions which are not complete
enough to have "as" template methods like the real classes.

I think the solution is either to restrict that test to when building with
ARM, or to add as<>() to the dummy classes. In the short term the offending
change can be reverted, or we can wait until this evening when I'll have a
chance to find a proper fix. This is what is right now probably a unique
corner case where we have a unit test which is ISA dependent, and while it
will *become* possible to run reasonably under any build once the
ThreadContext doesn't build in what data type vector registers should be,
in the mean time it either won't work because of this problem, or even when
it would work, it would be operating on an inappropriate data type.

Gabe

On Tue, Mar 15, 2022 at 8:13 AM Jason Lowe-Power 
wrote:

> Looks like the problem is  [gabe.black] arch: Make the DummyVec... types
> the same size as RegVal.
>
> Can you take a look, Gabe?
>
> Thanks,
> Jason
>
> On Tue, Mar 15, 2022 at 1:46 AM jenkins-no-reply--- via gem5-dev <
> gem5-dev@gem5.org> wrote:
>
>> See <
>> https://jenkins.gem5.org/job/nightly/161/display/redirect?page=changes>
>>
>> Changes:
>>
>> [gabe.black] arch-x86: Fix a bug in the protected mode IRET.
>>
>> [gabe.black] arch-x86: Fix writing back 32 bit PTEs in the walker.
>>
>> [gabe.black] arch-x86: Detect when entering virtual 8086 mode.
>>
>> [gabe.black] arch-x86: Tidy up the page table walker stepWalk method.
>>
>> [gabe.black] arch-x86: Use the right bits in the page table walker.
>>
>> [gabe.black] arch-x86: Make the flags microops handle reserved bits
>> better.
>>
>> [matthew.poremba] sim-se: Initialize shared page table base upon clone
>>
>> [Bobby R. Bruce] util-docker: Adding docker-compose.yaml
>>
>> [Bobby R. Bruce] tests,util-docker: Add clang-12 to the compiler tests
>>
>> [Bobby R. Bruce] util: Remove util/cloudbuild
>>
>> [gabe.black] dev,arch-x86: Make the I8042 reset settings more realistic.
>>
>> [gabe.black] dev,arch-x86: Implement some self test 8042 commands.
>>
>> [gabe.black] scons: Process the SConsopts files for each variant.
>>
>> [gabe.black] scons: Turn a lot of compiler flag vars into env vars.
>>
>> [gabe.black] arch-x86: Fix the SAHF and LAHF instructions.
>>
>> [gabe.black] arch: Make the DummyVec... types the same size as RegVal.
>>
>> [gabe.black] ext,scons: Make kconfiglib available for use in SCons.
>>
>> [gabe.black] scons: Make all sticky variables automatically exported.
>>
>> [gabe.black] dev: Implement PS/2 keyboard echo and set scan code commands.
>>
>> [gabe.black] arch-x86: Specialize some instructions for virtual 8086 mode.
>>
>>
>> --
>> [...truncated 1.17 MB...]
>> [ RUN  ] LoggingFixture.Warn
>> [   OK ] LoggingFixture.Warn (0 ms)
>> [ RUN  ] LoggingFixture.Inform
>> [   OK ] LoggingFixture.Inform (0 ms)
>> [ RUN  ] LoggingFixture.Hack
>> [   OK ] LoggingFixture.Hack (0 ms)
>> [ RUN  ] LoggingFixture.WarnOnce
>> [   OK ] LoggingFixture.WarnOnce (0 ms)
>> [ RUN  ] LoggingFixture.InformOnce
>> [   OK ] LoggingFixture.InformOnce (0 ms)
>> [ RUN  ] LoggingFixture.HackOnce
>> [   OK ] LoggingFixture.HackOnce (0 ms)
>> [ RUN  ] LoggingFixture.WarnIf
>> [   OK ] LoggingFixture.WarnIf (0 ms)
>> [ RUN  ] LoggingFixture.WarnIfOnce
>> [   OK ] LoggingFixture.WarnIfOnce (0 ms)
>> [--] 21 tests from LoggingFixture (0 ms total)
>>
>> [--] Global test environment tear-down
>> [==] 34 tests from 2 test suites ran. (1638 ms total)
>> [  PASSED  ] 34 tests.
>>  [LINK]  -> NULL/arch/generic/vec_pred_reg.test.opt
>> build/NULL/arch/generic/vec_reg.test.opt
>> --gtest_output=xml:build/NULL/unittests.opt/arch/generic/vec_reg.test.xml
>> Running main() from build/NULL/ext/googletest/googletest/src/gtest_main.cc
>> [==] Running 8 tests from 2 test suites.
>> [--] Global test environment set-up.
>> [--] 2 tests from VecReg
>> [ RUN  ] VecReg.Size
>> [   OK ] VecReg.Size (0 ms)
>> [ RUN  ] VecReg.Zero
>> [   OK ] VecReg.Zero (0 ms)
>> [--] 2 tests from VecReg (0 ms total)
>>
>> [--] 6 tests from TwoDifferentVecRegs
>> [ RUN  ] TwoDifferentVecRegs.Assignment
>> [   OK ] TwoDifferentVecRegs.Assignment (0 ms)
>> [ RUN  ] TwoDifferentVecRegs.Equality
>> [   OK ] TwoDifferentVecRegs.Equality (0 ms)
>> [ RUN  ] TwoDifferentVecRegs.Inequality
>> [   OK ] TwoDifferentVecRegs.Inequality (0 ms)
>> [ RUN  ] TwoDifferentVecRegs.Printing
>> [   OK ] TwoDifferentVecRegs.Printing (0 ms)
>> [ RUN  ] TwoDifferentVecRegs.ParseParam
>> [   OK ] TwoDifferentVecRegs.ParseParam (0 ms)
>> [ RUN  ]

[gem5-dev] Change in gem5/gem5[develop]: dev-hsa: Properly mask HSA packet header bits

2022-03-15 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57669 )



Change subject: dev-hsa: Properly mask HSA packet header bits
..

dev-hsa: Properly mask HSA packet header bits

The HSA packet macros were not actually masking the header bits
properly. Add a mask call around the width (number of bits) of the field
being masked.

Change-Id: Ia5e5fb0451296e99a85fb12a5f73b27aea72fc2e
---
M src/dev/hsa/hsa_packet_processor.cc
1 file changed, 16 insertions(+), 2 deletions(-)



diff --git a/src/dev/hsa/hsa_packet_processor.cc  
b/src/dev/hsa/hsa_packet_processor.cc

index 89fc3c1..1236256 100644
--- a/src/dev/hsa/hsa_packet_processor.cc
+++ b/src/dev/hsa/hsa_packet_processor.cc
@@ -60,12 +60,13 @@
   }

 #define PKT_TYPE(PKT) ((hsa_packet_type_t)(((PKT->header) >> \
-HSA_PACKET_HEADER_TYPE) & (HSA_PACKET_HEADER_WIDTH_TYPE - 1)))
+HSA_PACKET_HEADER_TYPE) & mask(HSA_PACKET_HEADER_WIDTH_TYPE)))

 // checks if the barrier bit is set in the header -- shift the barrier bit
 // to LSB, then bitwise "and" to mask off all other bits
 #define IS_BARRIER(PKT) ((hsa_packet_header_t)(((PKT->header) >> \
-HSA_PACKET_HEADER_BARRIER) & HSA_PACKET_HEADER_WIDTH_BARRIER))
+HSA_PACKET_HEADER_BARRIER) & \
+mask(HSA_PACKET_HEADER_WIDTH_BARRIER)))

 namespace gem5
 {

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia5e5fb0451296e99a85fb12a5f73b27aea72fc2e
Gerrit-Change-Number: 57669
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: dev-hsa: Update QCntxt readIndex in HW scheduler write

2022-03-15 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57670 )



Change subject: dev-hsa: Update QCntxt readIndex in HW scheduler write
..

dev-hsa: Update QCntxt readIndex in HW scheduler write

The QCntxt is reused when a queue is unmapped and mapped again. This is
fairly common in GPU full system. If this is not done the readIndex on
the queue context is reset to 1, causing getCommandsFromHost to read
from the wrong slot which is typically an old dispatch packet or an
invalid packet. This causes simulation to stall as the incorrect
completion signal is eventually written.

Change-Id: I65541e559fe04f5eb44b936ca37e3f802262fe6a
---
M src/dev/hsa/hw_scheduler.cc
1 file changed, 21 insertions(+), 0 deletions(-)



diff --git a/src/dev/hsa/hw_scheduler.cc b/src/dev/hsa/hw_scheduler.cc
index 8798d42..d88e4f9 100644
--- a/src/dev/hsa/hw_scheduler.cc
+++ b/src/dev/hsa/hw_scheduler.cc
@@ -332,6 +332,11 @@
 uint32_t al_idx = dbMap[db_addr];
 // Modify the write pointer
 activeList[al_idx].qDesc->writeIndex = doorbell_reg;
+// If a queue is unmapped and remapped (common in full system) the  
qDesc
+// gets reused. Keep the readIndex up to date so that when the HSA  
packet

+// processor gets commands from host, the correct entry is read after
+// remapping.
+activeList[al_idx].qDesc->readIndex = doorbell_reg - 1;
 DPRINTF(HSAPacketProcessor, "queue %d qDesc->writeIndex %d\n",
 al_idx, activeList[al_idx].qDesc->writeIndex);
 // If this queue is mapped, then start DMA to fetch the

--
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Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba 
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[gem5-dev] Change in gem5/gem5[develop]: mem: Add TlbiExtSync packet type

2022-03-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57290 )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: mem: Add TlbiExtSync packet type
..

mem: Add TlbiExtSync packet type

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I45435326daca599ac973c74ecac52bf7fd33
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57290
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/packet.cc
M src/mem/packet.hh
2 files changed, 21 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index 24c3d9c..3cd1bb9 100644
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2019 ARM Limited
+ * Copyright (c) 2011-2019, 2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -232,6 +232,7 @@
 { {IsRead, IsRequest, NeedsResponse}, HTMReqResp, "HTMReq" },
 { {IsRead, IsResponse}, InvalidCmd, "HTMReqResp" },
 { {IsRead, IsRequest}, InvalidCmd, "HTMAbort" },
+{ {IsRequest}, InvalidCmd, "TlbiExtSync" },
 };

 AddrRange
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index d42ea27..7d32634 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2019 ARM Limited
+ * Copyright (c) 2012-2019, 2021 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -144,6 +144,8 @@
 HTMReq,
 HTMReqResp,
 HTMAbort,
+// Tlb shootdown
+TlbiExtSync,
 NUM_MEM_CMDS
 };


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I45435326daca599ac973c74ecac52bf7fd33
Gerrit-Change-Number: 57290
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem: Add external TLBI flags to the Request object

2022-03-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57289 )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: mem: Add external TLBI flags to the Request object
..

mem: Add external TLBI flags to the Request object

* TLBI_EXT_SYNC: This flag tells the CPU model that a
remote TLBI Sync has been requested

* TLBI_EXT_SYNC_COMP: This flag tells the interconnect that a
remote TLBI Sync request has completed

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I459d22f112038cc1427e2404ba74c1c08cfb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57289
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Andreas Sandberg 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/request.hh
1 file changed, 40 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/mem/request.hh b/src/mem/request.hh
index 867cbb0..85a9bed 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -243,6 +243,14 @@
 /** The Request is a TLB shootdown sync */
 TLBI_SYNC   = 0x2000,

+/** The Request tells the CPU model that a
+remote TLB Sync has been requested */
+TLBI_EXT_SYNC   = 0x4000,
+
+/** The Request tells the interconnect that a
+remote TLB Sync request has completed */
+TLBI_EXT_SYNC_COMP  = 0x8000,
+
 /**
  * These flags are *not* cleared when a Request object is
  * reused (assigned a new address).
@@ -255,7 +263,8 @@
 static const FlagsType HTM_CMD = HTM_START | HTM_COMMIT |
 HTM_CANCEL | HTM_ABORT;

-static const FlagsType TLBI_CMD = TLBI | TLBI_SYNC;
+static const FlagsType TLBI_CMD = TLBI | TLBI_SYNC |
+TLBI_EXT_SYNC | TLBI_EXT_SYNC_COMP;

 /** Requestor Ids that are statically allocated
  * @{*/
@@ -985,7 +994,14 @@

 bool isTlbi() const { return _flags.isSet(TLBI); }
 bool isTlbiSync() const { return _flags.isSet(TLBI_SYNC); }
-bool isTlbiCmd() const { return isTlbi() || isTlbiSync(); }
+bool isTlbiExtSync() const { return _flags.isSet(TLBI_EXT_SYNC); }
+bool isTlbiExtSyncComp() const { return  
_flags.isSet(TLBI_EXT_SYNC_COMP); }

+bool
+isTlbiCmd() const
+{
+return (isTlbi() || isTlbiSync() ||
+isTlbiExtSync() || isTlbiExtSyncComp());
+}

 bool
 isAtomic() const

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I459d22f112038cc1427e2404ba74c1c08cfb
Gerrit-Change-Number: 57289
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add DVM enabled flag in the Decoder class

2022-03-15 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56603 )


 (

5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Add DVM enabled flag in the Decoder class
..

arch-arm: Add DVM enabled flag in the Decoder class

This is needed as the decoder needs to choose whether to
instantiate a DVM (treated as IsLoad) instruction when
decoding a TLBI/DSB Shareable, or to issue a simple system
instruction in case DVM messages are not modelled in the
simulated system.

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I9f46304dee63851caec809a5c6b8e796d684cc05
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56603
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/arch/arm/ArmDecoder.py
M src/arch/arm/decoder.cc
M src/arch/arm/decoder.hh
3 files changed, 47 insertions(+), 3 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/ArmDecoder.py b/src/arch/arm/ArmDecoder.py
index 9f01af6..a5c16f5 100644
--- a/src/arch/arm/ArmDecoder.py
+++ b/src/arch/arm/ArmDecoder.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2021 Arm Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright 2021 Google, Inc.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -23,9 +35,13 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

+from m5.params import *
 from m5.objects.InstDecoder import InstDecoder

 class ArmDecoder(InstDecoder):
 type = 'ArmDecoder'
 cxx_class = 'gem5::ArmISA::Decoder'
 cxx_header = "arch/arm/decoder.hh"
+
+dvm_enabled = Param.Bool(False,
+"Does the decoder implement DVM operations")
diff --git a/src/arch/arm/decoder.cc b/src/arch/arm/decoder.cc
index 9d90537..18b8c04 100644
--- a/src/arch/arm/decoder.cc
+++ b/src/arch/arm/decoder.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2014,2018 ARM Limited
+ * Copyright (c) 2012-2014,2018, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -55,7 +55,9 @@
 GenericISA::BasicDecodeCache Decoder::defaultCache;

 Decoder::Decoder(const ArmDecoderParams )
-: InstDecoder(params, ), data(0), fpscrLen(0), fpscrStride(0),
+: InstDecoder(params, ),
+  dvmEnabled(params.dvm_enabled),
+  data(0), fpscrLen(0), fpscrStride(0),
   decoderFlavor(dynamic_cast(params.isa)->decoderFlavor())
 {
 reset();
diff --git a/src/arch/arm/decoder.hh b/src/arch/arm/decoder.hh
index 62d6f54..fdabe6c 100644
--- a/src/arch/arm/decoder.hh
+++ b/src/arch/arm/decoder.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014 ARM Limited
+ * Copyright (c) 2013-2014, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -62,6 +62,10 @@
 class ISA;
 class Decoder : public InstDecoder
 {
+  public: // Public decoder parameters
+/** True if the decoder should emit DVM Ops (treated as Loads) */
+const bool dvmEnabled;
+
   protected:
 //The extended machine instruction being generated
 ExtMachInst emi;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9f46304dee63851caec809a5c6b8e796d684cc05
Gerrit-Change-Number: 56603
Gerrit-PatchSet: 7
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Re: Build failed in Jenkins: nightly #161

2022-03-15 Thread Jason Lowe-Power via gem5-dev

Looks like the problem is  [gabe.black] arch: Make the DummyVec... types
the same size as RegVal.

Can you take a look, Gabe?

Thanks,
Jason

On Tue, Mar 15, 2022 at 1:46 AM jenkins-no-reply--- via gem5-dev <
gem5-dev@gem5.org> wrote:

> See <
> https://jenkins.gem5.org/job/nightly/161/display/redirect?page=changes>
>
> Changes:
>
> [gabe.black] arch-x86: Fix a bug in the protected mode IRET.
>
> [gabe.black] arch-x86: Fix writing back 32 bit PTEs in the walker.
>
> [gabe.black] arch-x86: Detect when entering virtual 8086 mode.
>
> [gabe.black] arch-x86: Tidy up the page table walker stepWalk method.
>
> [gabe.black] arch-x86: Use the right bits in the page table walker.
>
> [gabe.black] arch-x86: Make the flags microops handle reserved bits better.
>
> [matthew.poremba] sim-se: Initialize shared page table base upon clone
>
> [Bobby R. Bruce] util-docker: Adding docker-compose.yaml
>
> [Bobby R. Bruce] tests,util-docker: Add clang-12 to the compiler tests
>
> [Bobby R. Bruce] util: Remove util/cloudbuild
>
> [gabe.black] dev,arch-x86: Make the I8042 reset settings more realistic.
>
> [gabe.black] dev,arch-x86: Implement some self test 8042 commands.
>
> [gabe.black] scons: Process the SConsopts files for each variant.
>
> [gabe.black] scons: Turn a lot of compiler flag vars into env vars.
>
> [gabe.black] arch-x86: Fix the SAHF and LAHF instructions.
>
> [gabe.black] arch: Make the DummyVec... types the same size as RegVal.
>
> [gabe.black] ext,scons: Make kconfiglib available for use in SCons.
>
> [gabe.black] scons: Make all sticky variables automatically exported.
>
> [gabe.black] dev: Implement PS/2 keyboard echo and set scan code commands.
>
> [gabe.black] arch-x86: Specialize some instructions for virtual 8086 mode.
>
>
> --
> [...truncated 1.17 MB...]
> [ RUN  ] LoggingFixture.Warn
> [   OK ] LoggingFixture.Warn (0 ms)
> [ RUN  ] LoggingFixture.Inform
> [   OK ] LoggingFixture.Inform (0 ms)
> [ RUN  ] LoggingFixture.Hack
> [   OK ] LoggingFixture.Hack (0 ms)
> [ RUN  ] LoggingFixture.WarnOnce
> [   OK ] LoggingFixture.WarnOnce (0 ms)
> [ RUN  ] LoggingFixture.InformOnce
> [   OK ] LoggingFixture.InformOnce (0 ms)
> [ RUN  ] LoggingFixture.HackOnce
> [   OK ] LoggingFixture.HackOnce (0 ms)
> [ RUN  ] LoggingFixture.WarnIf
> [   OK ] LoggingFixture.WarnIf (0 ms)
> [ RUN  ] LoggingFixture.WarnIfOnce
> [   OK ] LoggingFixture.WarnIfOnce (0 ms)
> [--] 21 tests from LoggingFixture (0 ms total)
>
> [--] Global test environment tear-down
> [==] 34 tests from 2 test suites ran. (1638 ms total)
> [  PASSED  ] 34 tests.
>  [LINK]  -> NULL/arch/generic/vec_pred_reg.test.opt
> build/NULL/arch/generic/vec_reg.test.opt
> --gtest_output=xml:build/NULL/unittests.opt/arch/generic/vec_reg.test.xml
> Running main() from build/NULL/ext/googletest/googletest/src/gtest_main.cc
> [==] Running 8 tests from 2 test suites.
> [--] Global test environment set-up.
> [--] 2 tests from VecReg
> [ RUN  ] VecReg.Size
> [   OK ] VecReg.Size (0 ms)
> [ RUN  ] VecReg.Zero
> [   OK ] VecReg.Zero (0 ms)
> [--] 2 tests from VecReg (0 ms total)
>
> [--] 6 tests from TwoDifferentVecRegs
> [ RUN  ] TwoDifferentVecRegs.Assignment
> [   OK ] TwoDifferentVecRegs.Assignment (0 ms)
> [ RUN  ] TwoDifferentVecRegs.Equality
> [   OK ] TwoDifferentVecRegs.Equality (0 ms)
> [ RUN  ] TwoDifferentVecRegs.Inequality
> [   OK ] TwoDifferentVecRegs.Inequality (0 ms)
> [ RUN  ] TwoDifferentVecRegs.Printing
> [   OK ] TwoDifferentVecRegs.Printing (0 ms)
> [ RUN  ] TwoDifferentVecRegs.ParseParam
> [   OK ] TwoDifferentVecRegs.ParseParam (0 ms)
> [ RUN  ] TwoDifferentVecRegs.ShowParam
> [   OK ] TwoDifferentVecRegs.ShowParam (0 ms)
> [--] 6 tests from TwoDifferentVecRegs (0 ms total)
>
> [--] Global test environment tear-down
> [==] 8 tests from 2 test suites ran. (0 ms total)
> [  PASSED  ] 8 tests.
>  [SO Param] m5.objects.SimObject, SimObject -> NULL/params/SimObject.hh
>  [ENUMDECL] m5.objects.StaticInstFlags, StaticInstFlags ->
> NULL/enums/StaticInstFlags.hh
>  [ENUMDECL] m5.objects.FuncUnit, OpClass -> NULL/enums/OpClass.hh
>  [ENUMDECL] m5.objects.SimObject, ByteOrder -> NULL/enums/ByteOrder.hh
> build/NULL/arch/generic/vec_pred_reg.test.opt
> --gtest_output=xml:build/NULL/unittests.opt/arch/generic/vec_pred_reg.test.xml
> Running main() from build/NULL/ext/googletest/googletest/src/gtest_main.cc
> [==] Running 14 tests from 3 test suites.
> [--] Global test environment set-up.
> [--] 2 tests from VecPredReg
> [ RUN  ] VecPredReg.reset
> [   OK ] VecPredReg.reset (0 ms)
> [ RUN  ] VecPredReg.set
> [   OK ] VecPredReg.set (0 ms)
> [--] 2 tests from VecPredReg (0 ms total)
>
> [--] 9 tests from TwoDifferentVecPredRegs
> [ RUN  ]

[gem5-dev] Build failed in Jenkins: weekly #33

2022-03-15 Thread jenkins-no-reply--- via gem5-dev

See 

Changes:

[gabe.black] dev,arch-x86: Create an x86 QEMU fw cfg, and an E820 entry type.

[gabe.black] arch-x86: Get rid of the soft int Fault class.

[gabe.black] arch-x86: Subtract the base from the PC when entering faults.

[gabe.black] arch-x86: Use inline initializers for members of Interrupts.

[gabe.black] scons: Move the build of ext/ into the variant dirs.

[gabe.black] arch-x86,dev: Add an INTA like transaction for I8259.

[gabe.black] arch-x86,dev: Use INTA to get the vector for the IO APIC.

[gabe.black] arch-x86: Implement the LINT0 pin for the LAPIC.

[gabe.black] arch-x86,dev: Use default initializers in the I8259.

[gabe.black] arch-x86,dev: Make the I8259::getVector method protected.

[matthew.poremba] mem-ruby: Remove DataBlk from MOESI_AMD DirectoryEntry

[matthew.poremba] mem-ruby: Enhance MOESI_AMD DmaWrite

[matthew.poremba] configs: Make VIPER memory MessageBuffers ordered

[matthew.poremba] gpu-compute: Fix default MTYPE initialization

[gabe.black] dev: Add a qemu fw config item for a byte array.

[gabe.black] dev,arch-x86: Fix a panic in the i8042 device.

[gabe.black] dev,arch-x86: Change the i8042 to a normal PioDevice.

[gabe.black] arch-x86: Fix a bug in the protected mode IRET.

[gabe.black] arch-x86: Fix writing back 32 bit PTEs in the walker.

[gabe.black] arch-x86: Detect when entering virtual 8086 mode.

[gabe.black] arch-x86: Tidy up the page table walker stepWalk method.

[gabe.black] arch-x86: Use the right bits in the page table walker.

[gabe.black] arch-x86: Make the flags microops handle reserved bits better.

[matthew.poremba] sim-se: Initialize shared page table base upon clone

[Bobby R. Bruce] util-docker: Adding docker-compose.yaml

[Bobby R. Bruce] tests,util-docker: Add clang-12 to the compiler tests

[Bobby R. Bruce] util: Remove util/cloudbuild

[gabe.black] dev,arch-x86: Make the I8042 reset settings more realistic.

[gabe.black] dev,arch-x86: Implement some self test 8042 commands.

[gabe.black] scons: Process the SConsopts files for each variant.

[gabe.black] scons: Turn a lot of compiler flag vars into env vars.

[gabe.black] arch-x86: Fix the SAHF and LAHF instructions.

[gabe.black] arch: Make the DummyVec... types the same size as RegVal.


--
[...truncated 820.16 KB...]
 [SHCC] X86/ext/softfloat/s_shortShiftRight128.c -> .os
 [SHCC] X86/ext/softfloat/s_shortShiftRightExtendM.c -> .os
 [SHCC] X86/ext/softfloat/s_shortShiftRightJam128.c -> .os
 [SHCC] X86/ext/softfloat/s_shortShiftRightJam128Extra.c -> .os
 [SHCC] X86/ext/softfloat/s_shortShiftRightJam64.c -> .os
 [SHCC] X86/ext/softfloat/s_shortShiftRightJam64Extra.c -> .os
 [SHCC] X86/ext/softfloat/s_shortShiftRightM.c -> .os
 [SHCC] X86/ext/softfloat/s_sub128.c -> .os
 [SHCC] X86/ext/softfloat/s_sub1XM.c -> .os
 [SHCC] X86/ext/softfloat/s_sub256M.c -> .os
 [SHCC] X86/ext/softfloat/s_subMagsF128.c -> .os
 [SHCC] X86/ext/softfloat/s_subMagsF16.c -> .os
 [SHCC] X86/ext/softfloat/s_subMagsF32.c -> .os
 [SHCC] X86/ext/softfloat/s_subMagsF64.c -> .os
 [SHCC] X86/ext/softfloat/s_subM.c -> .os
 [SHCC] X86/ext/softfloat/ui32_to_f128.c -> .os
 [SHCC] X86/ext/softfloat/ui32_to_f16.c -> .os
 [SHCC] X86/ext/softfloat/ui32_to_f32.c -> .os
 [SHCC] X86/ext/softfloat/ui32_to_f64.c -> .os
 [SHCC] X86/ext/softfloat/ui64_to_f128.c -> .os
 [SHCC] X86/ext/softfloat/ui64_to_f16.c -> .os
 [SHCC] X86/ext/softfloat/ui64_to_f32.c -> .os
 [SHCC] X86/ext/softfloat/ui64_to_f64.c -> .os
build/X86/ext/libelf/native-elf-format > 
build/X86/ext/libelf/native-elf-format.h
 [  M4] X86/ext/libelf/elf_types.m4, libelf_convert.m4 -> libelf_convert.c
 [SHCC] X86/ext/libelf/elf_errno.c -> .os
 [SHCC] X86/ext/libelf/elf.c -> .os
 [SHCC] X86/ext/libelf/gelf_getclass.c -> .os
 [SHCC] X86/ext/libelf/elf_strptr.c -> .os
 [SHCC] X86/ext/libelf/libelf_convert.c -> .os
 [SHCC] X86/ext/libelf/libelf_checksum.c -> .os
 [SHCC] X86/ext/libelf/libelf_align.c -> .os
 [SHCC] X86/ext/libelf/elf_hash.c -> .os
 [SHCC] X86/ext/libelf/elf_getarhdr.c -> .os
 [SHCC] X86/ext/libelf/gelf_xlate.c -> .os
 [SHCC] X86/ext/libelf/elf_next.c -> .os
 [SHCC] X86/ext/libelf/elf_version.c -> .os
 [SHCC] X86/ext/libelf/gelf_sym.c -> .os
 [SHCC] X86/ext/libelf/gelf_rela.c -> .os
 [SHCC] X86/ext/libelf/elf_errmsg.c -> .os
 [SHCC] X86/ext/libelf/elf_getarsym.c -> .os
 [SHCC] X86/ext/libelf/elf_shstrndx.c -> .os
 [SHCC] X86/ext/libelf/libelf_xlate.c -> .os
 [SHCC] X86/ext/libelf/libelf_ehdr.c -> .os
 [SHCC] X86/ext/libelf/elf_getident.c -> .os
 [SHCC] X86/ext/libelf/libelf_open.c -> .os
 [SHCC] X86/ext/libelf/libelf.c -> .os
 [SHCC] X86/ext/libelf/elf_update.c -> .os
 [SHCC] X86/ext/libelf/libelf_ar_util.c -> .os
 [SHCC] X86/ext/libelf/elf_memory.c -> .os
 [SHCC]

[gem5-dev] Build failed in Jenkins: nightly #161

2022-03-15 Thread jenkins-no-reply--- via gem5-dev

See 

Changes:

[gabe.black] arch-x86: Fix a bug in the protected mode IRET.

[gabe.black] arch-x86: Fix writing back 32 bit PTEs in the walker.

[gabe.black] arch-x86: Detect when entering virtual 8086 mode.

[gabe.black] arch-x86: Tidy up the page table walker stepWalk method.

[gabe.black] arch-x86: Use the right bits in the page table walker.

[gabe.black] arch-x86: Make the flags microops handle reserved bits better.

[matthew.poremba] sim-se: Initialize shared page table base upon clone

[Bobby R. Bruce] util-docker: Adding docker-compose.yaml

[Bobby R. Bruce] tests,util-docker: Add clang-12 to the compiler tests

[Bobby R. Bruce] util: Remove util/cloudbuild

[gabe.black] dev,arch-x86: Make the I8042 reset settings more realistic.

[gabe.black] dev,arch-x86: Implement some self test 8042 commands.

[gabe.black] scons: Process the SConsopts files for each variant.

[gabe.black] scons: Turn a lot of compiler flag vars into env vars.

[gabe.black] arch-x86: Fix the SAHF and LAHF instructions.

[gabe.black] arch: Make the DummyVec... types the same size as RegVal.

[gabe.black] ext,scons: Make kconfiglib available for use in SCons.

[gabe.black] scons: Make all sticky variables automatically exported.

[gabe.black] dev: Implement PS/2 keyboard echo and set scan code commands.

[gabe.black] arch-x86: Specialize some instructions for virtual 8086 mode.


--
[...truncated 1.17 MB...]
[ RUN  ] LoggingFixture.Warn
[   OK ] LoggingFixture.Warn (0 ms)
[ RUN  ] LoggingFixture.Inform
[   OK ] LoggingFixture.Inform (0 ms)
[ RUN  ] LoggingFixture.Hack
[   OK ] LoggingFixture.Hack (0 ms)
[ RUN  ] LoggingFixture.WarnOnce
[   OK ] LoggingFixture.WarnOnce (0 ms)
[ RUN  ] LoggingFixture.InformOnce
[   OK ] LoggingFixture.InformOnce (0 ms)
[ RUN  ] LoggingFixture.HackOnce
[   OK ] LoggingFixture.HackOnce (0 ms)
[ RUN  ] LoggingFixture.WarnIf
[   OK ] LoggingFixture.WarnIf (0 ms)
[ RUN  ] LoggingFixture.WarnIfOnce
[   OK ] LoggingFixture.WarnIfOnce (0 ms)
[--] 21 tests from LoggingFixture (0 ms total)

[--] Global test environment tear-down
[==] 34 tests from 2 test suites ran. (1638 ms total)
[  PASSED  ] 34 tests.
 [LINK]  -> NULL/arch/generic/vec_pred_reg.test.opt
build/NULL/arch/generic/vec_reg.test.opt 
--gtest_output=xml:build/NULL/unittests.opt/arch/generic/vec_reg.test.xml
Running main() from build/NULL/ext/googletest/googletest/src/gtest_main.cc
[==] Running 8 tests from 2 test suites.
[--] Global test environment set-up.
[--] 2 tests from VecReg
[ RUN  ] VecReg.Size
[   OK ] VecReg.Size (0 ms)
[ RUN  ] VecReg.Zero
[   OK ] VecReg.Zero (0 ms)
[--] 2 tests from VecReg (0 ms total)

[--] 6 tests from TwoDifferentVecRegs
[ RUN  ] TwoDifferentVecRegs.Assignment
[   OK ] TwoDifferentVecRegs.Assignment (0 ms)
[ RUN  ] TwoDifferentVecRegs.Equality
[   OK ] TwoDifferentVecRegs.Equality (0 ms)
[ RUN  ] TwoDifferentVecRegs.Inequality
[   OK ] TwoDifferentVecRegs.Inequality (0 ms)
[ RUN  ] TwoDifferentVecRegs.Printing
[   OK ] TwoDifferentVecRegs.Printing (0 ms)
[ RUN  ] TwoDifferentVecRegs.ParseParam
[   OK ] TwoDifferentVecRegs.ParseParam (0 ms)
[ RUN  ] TwoDifferentVecRegs.ShowParam
[   OK ] TwoDifferentVecRegs.ShowParam (0 ms)
[--] 6 tests from TwoDifferentVecRegs (0 ms total)

[--] Global test environment tear-down
[==] 8 tests from 2 test suites ran. (0 ms total)
[  PASSED  ] 8 tests.
 [SO Param] m5.objects.SimObject, SimObject -> NULL/params/SimObject.hh
 [ENUMDECL] m5.objects.StaticInstFlags, StaticInstFlags -> 
NULL/enums/StaticInstFlags.hh
 [ENUMDECL] m5.objects.FuncUnit, OpClass -> NULL/enums/OpClass.hh
 [ENUMDECL] m5.objects.SimObject, ByteOrder -> NULL/enums/ByteOrder.hh
build/NULL/arch/generic/vec_pred_reg.test.opt 
--gtest_output=xml:build/NULL/unittests.opt/arch/generic/vec_pred_reg.test.xml
Running main() from build/NULL/ext/googletest/googletest/src/gtest_main.cc
[==] Running 14 tests from 3 test suites.
[--] Global test environment set-up.
[--] 2 tests from VecPredReg
[ RUN  ] VecPredReg.reset
[   OK ] VecPredReg.reset (0 ms)
[ RUN  ] VecPredReg.set
[   OK ] VecPredReg.set (0 ms)
[--] 2 tests from VecPredReg (0 ms total)

[--] 9 tests from TwoDifferentVecPredRegs
[ RUN  ] TwoDifferentVecPredRegs.Assignment
[   OK ] TwoDifferentVecPredRegs.Assignment (0 ms)
[ RUN  ] TwoDifferentVecPredRegs.Equality
[   OK ] TwoDifferentVecPredRegs.Equality (0 ms)
[ RUN  ] TwoDifferentVecPredRegs.Inequality
[   OK ] TwoDifferentVecPredRegs.Inequality (0 ms)
[ RUN  ] TwoDifferentVecPredRegs.Printing
[   OK ] TwoDifferentVecPredRegs.Printing (0 ms)
[ RUN  ] TwoDifferentVecPredRegs.ParseParam
[   OK ]

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Specialize some instructions for virtual 8086 mode.

2022-03-15 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55809 )


Change subject: arch-x86: Specialize some instructions for virtual 8086  
mode.

..

arch-x86: Specialize some instructions for virtual 8086 mode.

Some instructions behave in special ways in virtual 8086 mode. In some
cases, that means that they behave like they do in real mode, even
though the CPU has protected mode enabled. In other cases, it means that
there are extra checks, or even very different behaviors, which help
virtualize the system for the 8086 programs.

Change-Id: I70723b38ea0a7625c4a557bf4dd8f044e5715172
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55809
Reviewed-by: Matthew Poremba 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/x86/isa/decoder/one_byte_opcodes.isa
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
M  
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py

M src/arch/x86/isa/insts/general_purpose/flags/push_and_pop.py
M src/arch/x86/isa/insts/general_purpose/flags/set_and_clear.py
M src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
M src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
7 files changed, 160 insertions(+), 28 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa  
b/src/arch/x86/isa/decoder/one_byte_opcodes.isa

index 152f6e4..f4236a9 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -47,7 +47,7 @@
 }
 0x7: decode MODE_SUBMODE {
 0x0: UD2();
-0x4: POP_REAL(sEv);
+0x3, 0x4: POP_REAL(sEv);
 default: WarnUnimpl::pop_ES();
 }
 default: MultiInst::ADD(OPCODE_OP_BOTTOM3,
@@ -75,7 +75,7 @@
 }
 0x7: decode MODE_SUBMODE {
 0x0: UD2();
-0x4: POP_REAL(sSv);
+0x3, 0x4: POP_REAL(sSv);
 default: WarnUnimpl::pop_SS();
 }
 default: MultiInst::ADC(OPCODE_OP_BOTTOM3,
@@ -90,7 +90,7 @@
 }
 0x7: decode MODE_SUBMODE {
 0x0: UD2();
-0x4: POP_REAL(sDv);
+0x3, 0x4: POP_REAL(sDv);
 default: WarnUnimpl::pop_DS();
 }
 default: MultiInst::SBB(OPCODE_OP_BOTTOM3,
@@ -192,10 +192,22 @@
 0x1: IMUL(Gv,Ev,Iz);
 0x2: PUSH(Ib);
 0x3: IMUL(Gv,Ev,Ib);
-0x4: StringInst::INS(Yb,rD);
-0x5: StringInst::INS(Yz,rD);
-0x6: StringInst::OUTS(rD,Xb);
-0x7: StringInst::OUTS(rD,Xz);
+0x4: decode MODE_SUBMODE {
+0x3: StringInst::INS_VIRT(Yb,rD);
+default: StringInst::INS(Yb,rD);
+}
+0x5: decode MODE_SUBMODE {
+0x3: StringInst::INS_VIRT(Yz,rD);
+default: StringInst::INS(Yz,rD);
+}
+0x6: decode MODE_SUBMODE {
+0x3: StringInst::OUTS_VIRT(rD,Xb);
+default: StringInst::OUTS(rD,Xb);
+}
+0x7: decode MODE_SUBMODE {
+0x3: StringInst::OUTS_VIRT(rD,Xz);
+default: StringInst::OUTS(rD,Xz);
+}
 }
 0x0E: decode OPCODE_OP_BOTTOM3 {
 0x0: JO(Jb);
@@ -305,12 +317,18 @@
 0x1: CQO(rAv,rDv);
 0x2: decode MODE_SUBMODE {
 0x0: UD2();
-0x4: CALL_FAR_REAL(Iz);
+0x3, 0x4: CALL_FAR_REAL(Iz);
 default: WarnUnimpl::call_far_Ap();
 }
 0x3: WarnUnimpl::fwait(); //aka wait
-0x4: PUSHF();
-0x5: POPF();
+0x4: decode MODE_SUBMODE {
+0x3: PUSHF_VIRT();
+default: PUSHF();
+}
+0x5: decode MODE_SUBMODE {
+0x3: POPF_VIRT();
+default: POPF();
+}
 //The 64 bit versions of both of these should be illegal only
 //if CPUID says it isn't supported. For now, we'll just assume
 //that it's supported.
@@ -366,12 +384,12 @@
 0x3: RET_NEAR();
 0x4: decode MODE_SUBMODE {
 0x0: UD2();
-0x4: LES_REAL(Gz,Mz);
+0x3, 0x4: LES_REAL(Gz,Mz);
 default: WarnUnimpl::les_Gz_Mp();
 }
 0x5: decode MODE_SUBMODE {
 0x0: UD2();
-0x4: LDS_REAL(Gz,Mz);
+0x3, 0x4: LDS_REAL(Gz,Mz);
 default: WarnUnimpl::lds_Gz_Mp();
 }
 //0x6: group12_Eb_Ib();
@@ -400,7 +418,11 @@

[gem5-dev] Change in gem5/gem5[develop]: dev: Implement PS/2 keyboard echo and set scan code commands.

2022-03-15 Thread Gabe Black (Gerrit) via gem5-dev

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55807 )


Change subject: dev: Implement PS/2 keyboard echo and set scan code  
commands.

..

dev: Implement PS/2 keyboard echo and set scan code commands.

Don't actually let anyone set a scan code set other than 2, since that's
all our converter knows about. It's probably all anyone will want
anyway.

Change-Id: Ief2f35448adc80e30e8fdf13ef9d64d6f19447eb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55807
Reviewed-by: Matthew Poremba 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/dev/ps2/keyboard.cc
1 file changed, 36 insertions(+), 2 deletions(-)

Approvals:
  Matthew Poremba: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/ps2/keyboard.cc b/src/dev/ps2/keyboard.cc
index fb63d48..e3b13ac 100644
--- a/src/dev/ps2/keyboard.cc
+++ b/src/dev/ps2/keyboard.cc
@@ -128,9 +128,26 @@
 return true;
 }
   case keyboard::DiagnosticEcho:
-panic("Keyboard diagnostic echo unimplemented.\n");
+send(keyboard::DiagnosticEcho);
+return true;
   case keyboard::AlternateScanCodes:
-panic("Accessing alternate scan codes unimplemented.\n");
+if (data.size() == 1) {
+DPRINTF(PS2, "Got scan code set command.\n");
+sendAck();
+return false;
+} else {
+sendAck();
+uint8_t scan_code = data[1];
+if (scan_code == 0) {
+DPRINTF(PS2, "Sending hard coded current scan code set  
2.\n");

+send(0x2);
+} else {
+DPRINTF(PS2, "Setting scan code set to %d.\n", scan_code);
+panic_if(scan_code != 0x2,
+"PS/2 scan code set %d not supported.", scan_code);
+}
+}
+return true;
   case keyboard::TypematicInfo:
 if (data.size() == 1) {
 DPRINTF(PS2, "Setting typematic info.\n");

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/55807
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ief2f35448adc80e30e8fdf13ef9d64d6f19447eb
Gerrit-Change-Number: 55807
Gerrit-PatchSet: 13
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bradford Beckmann 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Re: Build failed in Jenkins: nightly #161

[gem5-dev] Change in gem5/gem5[develop]: base: zero initialize the underlying storage of bitunion

[gem5-dev] Change in gem5/gem5[develop]: mem: Add SharedMemoryServer

[gem5-dev] Change in gem5/gem5[develop]: util-docker: Add docker container for building riscv target

[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Don't use emulated driver in full system

[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Command processor read path from device

[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Support Scalar and Vector access to system pages

[gem5-dev] Change in gem5/gem5[develop]: gpu-compute: Handle mailbox/wakeup signals for GPUFS

[gem5-dev] Change in gem5/gem5[develop]: stdlib: Add the MinorCPU type to the stdlib

[gem5-dev] Change in gem5/gem5[develop]: tests: Add MinorCPU tests to the RISCV Boot tests

[gem5-dev] Change in gem5/gem5[develop]: tests: Add MinorCPU tests to Hello World tests

[gem5-dev] Re: Build failed in Jenkins: nightly #161

[gem5-dev] Change in gem5/gem5[develop]: dev-hsa: Properly mask HSA packet header bits

[gem5-dev] Change in gem5/gem5[develop]: dev-hsa: Update QCntxt readIndex in HW scheduler write

[gem5-dev] Change in gem5/gem5[develop]: mem: Add TlbiExtSync packet type

[gem5-dev] Change in gem5/gem5[develop]: mem: Add external TLBI flags to the Request object

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add DVM enabled flag in the Decoder class

[gem5-dev] Re: Build failed in Jenkins: nightly #161

[gem5-dev] Build failed in Jenkins: weekly #33

[gem5-dev] Build failed in Jenkins: nightly #161

[gem5-dev] Change in gem5/gem5[develop]: arch-x86: Specialize some instructions for virtual 8086 mode.

[gem5-dev] Change in gem5/gem5[develop]: dev: Implement PS/2 keyboard echo and set scan code commands.

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