[gem5-dev] Build failed in Jenkins: weekly #39

2022-03-28 Thread jenkins-no-reply--- via gem5-dev 
See 

Changes:

[Giacomo Travaglini] arch-arm, dev-arm: Implement EL2 Secure Physical Timer

[Giacomo Travaglini] arch-arm, dev-arm: Implement EL2 Secure Virtual Timer

[Giacomo Travaglini] arch-arm: Use uint64_t for AArch64 MiscReg operands

[Giacomo Travaglini] arch-arm: Fix RW permission access for _EL12 registers

[Giacomo Travaglini] dev-arm: Remove unused ELIsInHost redirection for 
CNTKCTL_EL1

[Bobby R. Bruce] tests: Increase test Dockers' memory limit to 18GB

[Bobby R. Bruce] dev-amdgpu: Remove unused variables in src/dev/amdgpu

[Bobby R. Bruce] dev-amdgpu: Add braces to stop clang compilation braces error

[matthew.poremba] configs: Add disjoint VIPER configuration

[matthew.poremba] configs: Add construct for GPU dirs

[matthew.poremba] dev-amdgpu: Setup VRAM memories in device

[Giacomo Travaglini] arch-arm: Move ISA::redirectRegVHE to .cc file

[Giacomo Travaglini] arch-arm: Fix ISA::redirectRegVHE method

[Giacomo Travaglini] arch-arm: _NS used in AArch32 if EL3 is AArch64

[gabe.black] arch: Add a mechanism to override methods of the Operand classes.

[matthew.poremba] gpu-compute,dev-hsa: Update CP and HSAPP for full-system

[matthew.poremba] arch-vega: Bypass Ruby for functional page walks

[matthew.poremba] dev-amdgpu: Always mark interrupts enabled

[matthew.poremba] configs: Fix XBar assert with odd number of CPUs

[matthew.poremba] configs: Force GPUFS config to use KVM

[matthew.poremba] dev-amdgpu: Add device memory

[matthew.poremba] configs: Add vega10 KVM script

[matthew.poremba] dev-amdgpu: Handle framebuffer reads from device cache

[matthew.poremba] configs: Add GPU TLBs for GPU full system

[matthew.poremba] mem: Add setter for RequestorID in request

[matthew.poremba] gpu-compute: Add methods to read GPU memory requestor ID


--
[...truncated 823.28 KB...]
 [SHCC] X86/ext/softfloat/s_shortShiftRight128.c -> .os
 [SHCC] X86/ext/softfloat/s_shortShiftRightExtendM.c -> .os
 [SHCC] X86/ext/softfloat/s_shortShiftRightJam128.c -> .os
 [SHCC] X86/ext/softfloat/s_shortShiftRightJam128Extra.c -> .os
 [SHCC] X86/ext/softfloat/s_shortShiftRightJam64.c -> .os
 [SHCC] X86/ext/softfloat/s_shortShiftRightJam64Extra.c -> .os
 [SHCC] X86/ext/softfloat/s_shortShiftRightM.c -> .os
 [SHCC] X86/ext/softfloat/s_sub128.c -> .os
 [SHCC] X86/ext/softfloat/s_sub1XM.c -> .os
 [SHCC] X86/ext/softfloat/s_sub256M.c -> .os
 [SHCC] X86/ext/softfloat/s_subMagsF128.c -> .os
 [SHCC] X86/ext/softfloat/s_subMagsF16.c -> .os
 [SHCC] X86/ext/softfloat/s_subMagsF32.c -> .os
 [SHCC] X86/ext/softfloat/s_subMagsF64.c -> .os
 [SHCC] X86/ext/softfloat/s_subM.c -> .os
 [SHCC] X86/ext/softfloat/ui32_to_f128.c -> .os
 [SHCC] X86/ext/softfloat/ui32_to_f16.c -> .os
 [SHCC] X86/ext/softfloat/ui32_to_f32.c -> .os
 [SHCC] X86/ext/softfloat/ui32_to_f64.c -> .os
 [SHCC] X86/ext/softfloat/ui64_to_f128.c -> .os
 [SHCC] X86/ext/softfloat/ui64_to_f16.c -> .os
 [SHCC] X86/ext/softfloat/ui64_to_f32.c -> .os
 [SHCC] X86/ext/softfloat/ui64_to_f64.c -> .os
build/X86/ext/libelf/native-elf-format > 
build/X86/ext/libelf/native-elf-format.h
 [  M4] X86/ext/libelf/elf_types.m4, libelf_convert.m4 -> libelf_convert.c
 [SHCC] X86/ext/libelf/elf_getarhdr.c -> .os
 [SHCC] X86/ext/libelf/gelf_getclass.c -> .os
 [SHCC] X86/ext/libelf/gelf_phdr.c -> .os
 [SHCC] X86/ext/libelf/elf_errmsg.c -> .os
 [SHCC] X86/ext/libelf/libelf_convert.c -> .os
 [SHCC] X86/ext/libelf/gelf_rel.c -> .os
 [SHCC] X86/ext/libelf/elf_getident.c -> .os
 [SHCC] X86/ext/libelf/elf_shstrndx.c -> .os
 [SHCC] X86/ext/libelf/gelf_rela.c -> .os
 [SHCC] X86/ext/libelf/libelf_open.c -> .os
 [SHCC] X86/ext/libelf/libelf_shdr.c -> .os
 [SHCC] X86/ext/libelf/libelf.c -> .os
 [SHCC] X86/ext/libelf/elf_memory.c -> .os
 [SHCC] X86/ext/libelf/libelf_extended.c -> .os
 [SHCC] X86/ext/libelf/libelf_allocate.c -> .os
 [SHCC] X86/ext/libelf/gelf_dyn.c -> .os
 [SHCC] X86/ext/libelf/elf_cntl.c -> .os
 [SHCC] X86/ext/libelf/libelf_ehdr.c -> .os
 [SHCC] X86/ext/libelf/elf_end.c -> .os
 [SHCC] X86/ext/libelf/gelf_xlate.c -> .os
 [SHCC] X86/ext/libelf/gelf_symshndx.c -> .os
 [SHCC] X86/ext/libelf/elf_shnum.c -> .os
 [SHCC] X86/ext/libelf/elf_rand.c -> .os
 [SHCC] X86/ext/libelf/gelf_shdr.c -> .os
 [SHCC] X86/ext/libelf/gelf_fsize.c -> .os
 [SHCC] X86/ext/libelf/gelf_checksum.c -> .os
 [SHCC] X86/ext/libelf/elf_getbase.c -> .os
 [SHCC] X86/ext/libelf/libelf_data.c -> .os
 [SHCC] X86/ext/libelf/elf_data.c -> .os
 [SHCC] X86/ext/libelf/libelf_ar_util.c -> .os
 [SHCC] X86/ext/libelf/elf_begin.c -> .os
 [SHCC] X86/ext/libelf/elf_scn.c -> .os
 [SHCC] X86/ext/libelf/elf_phnum.c -> .os
 [SHCC] X86/ext/libelf/gelf_syminfo.c -> .os
 [SHCC] X86/ext/libelf/elf_fill.c ->

[gem5-dev] Change in gem5/gem5[develop]: mem: Align mmap offset to page boundary

2022-03-28 Thread Jui-min Lee (Gerrit) via gem5-dev 
Jui-min Lee has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58289 )



Change subject: mem: Align mmap offset to page boundary
..

mem: Align mmap offset to page boundary

If we create abstract memories with a sub-page size on a system with
shared backstore, the offset of next mmap might become non-page-align
and cause an invalid argument error.

In this CL, we always upscale the range size to multiple of page before
updating the offset, so the offset is always on page boundary.

Change-Id: I3a6adf312f2cb5a09ee6a24a87adc62b630eac66
---
M src/mem/physical.cc
M src/mem/physical.hh
2 files changed, 24 insertions(+), 2 deletions(-)



diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index cae37a0..94438db 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -50,6 +50,7 @@
 #include 
 #include 

+#include "base/intmath.hh"
 #include "base/trace.hh"
 #include "debug/AddrRanges.hh"
 #include "debug/Checkpoint.hh"
@@ -81,7 +82,8 @@
const std::string& shared_backstore,
bool auto_unlink_shared_backstore) :
 _name(_name), size(0), mmapUsingNoReserve(mmap_using_noreserve),
-sharedBackstore(shared_backstore), sharedBackstoreSize(0)
+sharedBackstore(shared_backstore), sharedBackstoreSize(0),
+pageSize(sysconf(_SC_PAGE_SIZE))
 {
 // Register cleanup callback if requested.
 if (auto_unlink_shared_backstore && !sharedBackstore.empty()) {
@@ -217,7 +219,9 @@
 } else {
 // Newly create backstore will be located after previous one.
 map_offset = sharedBackstoreSize;
-sharedBackstoreSize += range.size();
+// mmap requires the offset to be multiple of page, so we need to
+// upscale the range size.
+sharedBackstoreSize += divCeil(range.size(), pageSize) * pageSize;
 DPRINTF(AddrRanges, "Sharing backing store as %s at offset %llu\n",
 sharedBackstore.c_str(), (uint64_t)map_offset);
 shm_fd = shm_open(sharedBackstore.c_str(), O_CREAT | O_RDWR, 0666);
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index 3a976ed..4997d80 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -156,6 +156,8 @@
 const std::string sharedBackstore;
 uint64_t sharedBackstoreSize;

+long pageSize;
+
 // The physical memory used to provide the memory in the simulated
 // system
 std::vector backingStore;

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/58289
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3a6adf312f2cb5a09ee6a24a87adc62b630eac66
Gerrit-Change-Number: 58289
Gerrit-PatchSet: 1
Gerrit-Owner: Jui-min Lee 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: configs: Update memory port name in Ruby

2022-03-28 Thread Srikant Bharadwaj (Gerrit) via gem5-dev 
Srikant Bharadwaj has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58189 )


Change subject: configs: Update memory port name in Ruby
..

configs: Update memory port name in Ruby

Memory port for controllers is now called memory_out_port.
'memory' is a depracated param according to this change:
https://gem5-review.googlesource.com/c/public/gem5/+/34417

Change-Id: I6a561f5603c7597a3974af1766ab642acb3e59de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58189
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/ruby/Ruby.py
1 file changed, 19 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index 631c65c..ba94c15 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -130,7 +130,7 @@
 if len(system.mem_ranges) > 1:
 crossbar = IOXBar()
 crossbars.append(crossbar)
-dir_cntrl.memory = crossbar.cpu_side_ports
+dir_cntrl.memory_out_port = crossbar.cpu_side_ports

 dir_ranges = []
 for r in system.mem_ranges:
@@ -152,7 +152,7 @@
 if crossbar != None:
 mem_ctrl.port = crossbar.mem_side_ports
 else:
-mem_ctrl.port = dir_cntrl.memory
+mem_ctrl.port = dir_cntrl.memory_out_port

 # Enable low-power DRAM states if option is set
 if issubclass(mem_type, DRAMInterface):

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/58189
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6a561f5603c7597a3974af1766ab642acb3e59de
Gerrit-Change-Number: 58189
Gerrit-PatchSet: 2
Gerrit-Owner: Srikant Bharadwaj 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Srikant Bharadwaj 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: arch: Split up src/dest register ID creation.

2022-03-28 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49747 )


 (

66 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch: Split up src/dest register ID creation.
..

arch: Split up src/dest register ID creation.

This will allow us to selectively change the RegID of an operand to, for
instance, convert it to InvalidRegClass just as a source so it never
actually gets read.

Change-Id: I9f8117cbb2088f8150080f815cdb5cb84bd7218e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49747
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/isa_parser/operand_types.py
1 file changed, 27 insertions(+), 4 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/isa_parser/operand_types.py  
b/src/arch/isa_parser/operand_types.py

index dbb4b2d..a9f5eab 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -143,6 +143,12 @@
 def regId(self):
 return f'RegId({self.reg_class}, {self.reg_spec})'

+def srcRegId(self):
+return self.regId()
+
+def destRegId(self):
+return self.regId()
+
 def __init__(self, parser, full_name, ext, is_src, is_dest):
 self.parser = parser
 self.full_name = full_name
@@ -238,13 +244,13 @@
 c_dest = ''

 if self.is_src:
-c_src = self.src_reg_constructor % self.regId()
+c_src = self.src_reg_constructor % self.srcRegId()
 if self.hasReadPred():
 c_src = '\n\tif (%s) {%s\n\t}' % \
 (self.read_predicate, c_src)

 if self.is_dest:
-c_dest = self.dst_reg_constructor % self.regId()
+c_dest = self.dst_reg_constructor % self.destRegId()
 c_dest += f'\n\t_numTypedDestRegs[{self.reg_class}]++;'
 if self.hasWritePred():
 c_dest = '\n\tif (%s) {%s\n\t}' % \
@@ -499,10 +505,10 @@
 c_dest = ''

 if self.is_src:
-c_src = self.src_reg_constructor % self.regId()
+c_src = self.src_reg_constructor % self.srcRegId()

 if self.is_dest:
-c_dest = self.dst_reg_constructor % self.regId()
+c_dest = self.dst_reg_constructor % self.destRegId()

 return c_src + c_dest


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/49747
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9f8117cbb2088f8150080f815cdb5cb84bd7218e
Gerrit-Change-Number: 49747
Gerrit-PatchSet: 68
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: dev-hsa: Properly mask HSA packet header bits

2022-03-28 Thread Matthew Poremba (Gerrit) via gem5-dev 
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57669 )


 (

14 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: dev-hsa: Properly mask HSA packet header bits
..

dev-hsa: Properly mask HSA packet header bits

The HSA packet macros were not actually masking the header bits
properly. Add a mask call around the width (number of bits) of the field
being masked.

Change-Id: Ia5e5fb0451296e99a85fb12a5f73b27aea72fc2e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57669
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/dev/hsa/hsa_packet_processor.cc
1 file changed, 20 insertions(+), 2 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/hsa/hsa_packet_processor.cc  
b/src/dev/hsa/hsa_packet_processor.cc

index 89fc3c1..1236256 100644
--- a/src/dev/hsa/hsa_packet_processor.cc
+++ b/src/dev/hsa/hsa_packet_processor.cc
@@ -60,12 +60,13 @@
   }

 #define PKT_TYPE(PKT) ((hsa_packet_type_t)(((PKT->header) >> \
-HSA_PACKET_HEADER_TYPE) & (HSA_PACKET_HEADER_WIDTH_TYPE - 1)))
+HSA_PACKET_HEADER_TYPE) & mask(HSA_PACKET_HEADER_WIDTH_TYPE)))

 // checks if the barrier bit is set in the header -- shift the barrier bit
 // to LSB, then bitwise "and" to mask off all other bits
 #define IS_BARRIER(PKT) ((hsa_packet_header_t)(((PKT->header) >> \
-HSA_PACKET_HEADER_BARRIER) & HSA_PACKET_HEADER_WIDTH_BARRIER))
+HSA_PACKET_HEADER_BARRIER) & \
+mask(HSA_PACKET_HEADER_WIDTH_BARRIER)))

 namespace gem5
 {

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/57669
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia5e5fb0451296e99a85fb12a5f73b27aea72fc2e
Gerrit-Change-Number: 57669
Gerrit-PatchSet: 17
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: configs,gpu-compute: Support fetch from system pages

2022-03-28 Thread Matthew Poremba (Gerrit) via gem5-dev 
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57652 )


Change subject: configs,gpu-compute: Support fetch from system pages
..

configs,gpu-compute: Support fetch from system pages

The amdgpu driver supports fetching instructions from pages which reside
in system memory rather than device memory. This changeset adds support
to do this by adding the system hub object added in a prior changeset to
the fetch unit and issues requests to the system hub if the system bit
in the memory page's PTE is set. Otherwise, the requestor ID is set to
be device memory and the request is routed through the Ruby network /
GPU caches to fetch the instructions.

Change-Id: Ib2fb47c589fdd5e544ab6493d7dbd8f2d9d7b0e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57652
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/example/gpufs/system/system.py
M src/gpu-compute/GPU.py
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/compute_unit.hh
M src/gpu-compute/fetch_unit.cc
M src/gpu-compute/fetch_unit.hh
M src/gpu-compute/shader.cc
M src/gpu-compute/shader.hh
8 files changed, 87 insertions(+), 3 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/gpufs/system/system.py  
b/configs/example/gpufs/system/system.py

index 8c9895f..972a4f9 100644
--- a/configs/example/gpufs/system/system.py
+++ b/configs/example/gpufs/system/system.py
@@ -133,6 +133,10 @@
 gpu_mem_mgr = AMDGPUMemoryManager()
 system.pc.south_bridge.gpu.memory_manager = gpu_mem_mgr

+# CPU data path (SystemHub)
+system_hub = AMDGPUSystemHub()
+shader.system_hub = system_hub
+
 # GPU, HSAPP, and GPUCommandProc are DMA devices
 system._dma_ports.append(gpu_hsapp)
 system._dma_ports.append(gpu_cmd_proc)
@@ -141,6 +145,7 @@
 system._dma_ports.append(sdma1)
 system._dma_ports.append(device_ih)
 system._dma_ports.append(pm4_pkt_proc)
+system._dma_ports.append(system_hub)
 system._dma_ports.append(gpu_mem_mgr)
 system._dma_ports.append(hsapp_pt_walker)
 system._dma_ports.append(cp_pt_walker)
@@ -154,6 +159,7 @@
 sdma1.pio = system.iobus.mem_side_ports
 device_ih.pio = system.iobus.mem_side_ports
 pm4_pkt_proc.pio = system.iobus.mem_side_ports
+system_hub.pio = system.iobus.mem_side_ports

 # Full system needs special TLBs for SQC, Scalar, and vector data ports
 args.full_system = True
diff --git a/src/gpu-compute/GPU.py b/src/gpu-compute/GPU.py
index 3e5fba6..a0154a7 100644
--- a/src/gpu-compute/GPU.py
+++ b/src/gpu-compute/GPU.py
@@ -224,6 +224,7 @@
 CUs = VectorParam.ComputeUnit('Number of compute units')
 gpu_cmd_proc = Param.GPUCommandProcessor('Command processor for GPU')
 dispatcher = Param.GPUDispatcher('GPU workgroup dispatcher')
+system_hub = Param.AMDGPUSystemHub(NULL, 'GPU System Hub (FS Mode  
only)')

 n_wf = Param.Int(10, 'Number of wavefront slots per SIMD')
 impl_kern_launch_acq = Param.Bool(True, """Insert acq packet into
  ruby at kernel launch""")
diff --git a/src/gpu-compute/compute_unit.cc  
b/src/gpu-compute/compute_unit.cc

index cc6244b..e1794a8 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -979,11 +979,18 @@
 bool
 ComputeUnit::SQCPort::recvTimingResp(PacketPtr pkt)
 {
-computeUnit->fetchStage.processFetchReturn(pkt);
+computeUnit->handleSQCReturn(pkt);
+
 return true;
 }

 void
+ComputeUnit::handleSQCReturn(PacketPtr pkt)
+{
+fetchStage.processFetchReturn(pkt);
+}
+
+void
 ComputeUnit::SQCPort::recvReqRetry()
 {
 int len = retries.size();
diff --git a/src/gpu-compute/compute_unit.hh  
b/src/gpu-compute/compute_unit.hh

index 87ed541..1c211d9 100644
--- a/src/gpu-compute/compute_unit.hh
+++ b/src/gpu-compute/compute_unit.hh
@@ -463,6 +463,8 @@
 bool isDone() const;
 bool isVectorAluIdle(uint32_t simdId) const;

+void handleSQCReturn(PacketPtr pkt);
+
   protected:
 RequestorID _requestorId;

diff --git a/src/gpu-compute/fetch_unit.cc b/src/gpu-compute/fetch_unit.cc
index 6e35818..640e29b 100644
--- a/src/gpu-compute/fetch_unit.cc
+++ b/src/gpu-compute/fetch_unit.cc
@@ -206,6 +206,15 @@

 computeUnit.sqcTLBPort.sendFunctional(pkt);

+/**
+ * For full system, if this is a device request we need to set the
+ * requestor ID of the packet to the GPU memory manager so it is  
routed

+ * through Ruby as a memory request and not a PIO request.
+ */
+if (!pkt->req->systemReq()) {
+pkt->req->requestorId(computeUnit.vramRequestorId());
+}
+
 GpuTranslationState *sender_state =
  safe_cast(pkt->senderState);

@@ -250,6 +259,15 @@
 }

 /**
+ * For

[gem5-dev] Change in gem5/gem5[develop]: dev-hsa: Update QCntxt readIndex in HW scheduler write

2022-03-28 Thread Matthew Poremba (Gerrit) via gem5-dev 
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57670 )


 (

10 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: dev-hsa: Update QCntxt readIndex in HW scheduler write
..

dev-hsa: Update QCntxt readIndex in HW scheduler write

The QCntxt is reused when a queue is unmapped and mapped again. This is
fairly common in GPU full system. If this is not done the readIndex on
the queue context is reset to 1, causing getCommandsFromHost to read
from the wrong slot which is typically an old dispatch packet or an
invalid packet. This causes simulation to stall as the incorrect
completion signal is eventually written.

Change-Id: I65541e559fe04f5eb44b936ca37e3f802262fe6a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57670
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
Tested-by: kokoro 
---
M src/dev/hsa/hw_scheduler.cc
1 file changed, 25 insertions(+), 0 deletions(-)

Approvals:
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/hsa/hw_scheduler.cc b/src/dev/hsa/hw_scheduler.cc
index 91779ae..a0f1e87 100644
--- a/src/dev/hsa/hw_scheduler.cc
+++ b/src/dev/hsa/hw_scheduler.cc
@@ -335,6 +335,11 @@
 uint32_t al_idx = dbMap[db_addr];
 // Modify the write pointer
 activeList[al_idx].qDesc->writeIndex = doorbell_reg;
+// If a queue is unmapped and remapped (common in full system) the  
qDesc
+// gets reused. Keep the readIndex up to date so that when the HSA  
packet

+// processor gets commands from host, the correct entry is read after
+// remapping.
+activeList[al_idx].qDesc->readIndex = doorbell_reg - 1;
 DPRINTF(HSAPacketProcessor, "queue %d qDesc->writeIndex %d\n",
 al_idx, activeList[al_idx].qDesc->writeIndex);
 // If this queue is mapped, then start DMA to fetch the

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/57670
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I65541e559fe04f5eb44b936ca37e3f802262fe6a
Gerrit-Change-Number: 57670
Gerrit-PatchSet: 17
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Kyle Roarty 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: tests: Remove accidentally included "exit 0" test code

2022-03-28 Thread Bobby Bruce (Gerrit) via gem5-dev 
Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58269 )


Change subject: tests: Remove accidentally included "exit 0" test code
..

tests: Remove accidentally included "exit 0" test code

This "exit 0" line was included accidentally in this commit:
https://gem5-review.googlesource.com/c/public/gem5/+/58169

It should not have been included, it was for testing purposes only.

Change-Id: Ia4be334d773bbb998906b0f0ae980f9ed14c87b4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58269
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M tests/nightly.sh
1 file changed, 19 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/tests/nightly.sh b/tests/nightly.sh
index b02f05b..7b784b2 100755
--- a/tests/nightly.sh
+++ b/tests/nightly.sh
@@ -88,7 +88,6 @@

 # Try to build the ISA targets.
 build_target NULL
-exit 0
 build_target RISCV
 build_target X86
 build_target ARM

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/58269
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia4be334d773bbb998906b0f0ae980f9ed14c87b4
Gerrit-Change-Number: 58269
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: scons: Put internal build files in a gem5.build directory.

2022-03-28 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56589 )


 (

9 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: scons: Put internal build files in a gem5.build directory.
..

scons: Put internal build files in a gem5.build directory.

This keeps them organized, and also creates an anchor for the build
directory other than a directory named "build".

Change-Id: I3ed2f569e9fcd62eb4eca1c4556b45cd0c3552d4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56589
Reviewed-by: Bobby Bruce 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M SConstruct
M site_scons/gem5_scons/configure.py
2 files changed, 248 insertions(+), 220 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/SConstruct b/SConstruct
index 0bd879a..684cc8c 100755
--- a/SConstruct
+++ b/SConstruct
@@ -80,7 +80,7 @@
 import os
 import sys

-from os import mkdir, environ
+from os import mkdir, remove, environ
 from os.path import abspath, dirname, expanduser
 from os.path import isdir, isfile
 from os.path import join, split
@@ -238,8 +238,6 @@
 mkdir(build_root)
 main['BUILDROOT'] = build_root

-main.SConsignFile(os.path.join(build_root, "sconsign"))
-

 
 #
@@ -281,154 +279,6 @@
 if main['GCC'] + main['CLANG'] > 1:
 error('Two compilers enabled at once?')

-# Set up default C++ compiler flags
-if main['GCC'] or main['CLANG']:
-# As gcc and clang share many flags, do the common parts here
-main.Append(CCFLAGS=['-pipe'])
-main.Append(CCFLAGS=['-fno-strict-aliasing'])
-
-# Enable -Wall and -Wextra and then disable the few warnings that
-# we consistently violate
-main.Append(CCFLAGS=['-Wall', '-Wundef', '-Wextra',
- '-Wno-sign-compare', '-Wno-unused-parameter'])
-
-# We always compile using C++17
-main.Append(CXXFLAGS=['-std=c++17'])
-
-if sys.platform.startswith('freebsd'):
-main.Append(CCFLAGS=['-I/usr/local/include'])
-main.Append(CXXFLAGS=['-I/usr/local/include'])
-# On FreeBSD we need libthr.
-main.Append(LIBS=['thr'])
-
-with gem5_scons.Configure(main) as conf:
-conf.CheckLinkFlag('-Wl,--as-needed')
-
-linker = GetOption('linker')
-if linker:
-with gem5_scons.Configure(main) as conf:
-if not conf.CheckLinkFlag(f'-fuse-ld={linker}'):
-error(f'Linker "{linker}" is not supported')
-if linker == 'gold' and not GetOption('with_lto'):
-# Tell the gold linker to use threads. The gold linker
-# segfaults if both threads and LTO are enabled.
-conf.CheckLinkFlag('-Wl,--threads')
-conf.CheckLinkFlag(
-'-Wl,--thread-count=%d' % GetOption('num_jobs'))
-
-# Treat warnings as errors but white list some warnings that we
-# want to allow (e.g., deprecation warnings).
-main.Append(CCFLAGS=['-Werror',
- '-Wno-error=deprecated-declarations',
- '-Wno-error=deprecated',
-])
-
-else:
-error('\n'.join((
-  "Don't know what compiler options to use for your compiler.",
-  "compiler: " + main['CXX'],
-  "version: " + CXX_version.replace('\n', '') if
-CXX_version else 'COMMAND NOT FOUND!',
-  "If you're trying to use a compiler other than GCC",
-  "or clang, there appears to be something wrong with your",
-  "environment.",
-  "",
-  "If you are trying to use a compiler other than those listed",
-  "above you will need to ease fix SConstruct and ",
-  "src/SConscript to support that compiler.")))
-
-if main['GCC']:
-if compareVersions(main['CXXVERSION'], "7") < 0:
-error('gcc version 7 or newer required.\n'
-  'Installed version:', main['CXXVERSION'])
-
-with gem5_scons.Configure(main) as conf:
-# This warning has a false positive in the systemc code in g++  
11.1.

-conf.CheckCxxFlag('-Wno-free-nonheap-object')
-
-# Add the appropriate Link-Time Optimization (LTO) flags if  
`--with-lto` is

-# set.
-if GetOption('with_lto'):
-# g++ uses "make" to parallelize LTO. The program can be overriden  
with
-# the environment variable "MAKE", but we currently make no  
attempt to

-# plumb that variable through.
-parallelism = ''
-if main.Detect('make'):
-parallelism = '=%d' % GetOption('num_jobs')
-else:
-warning('"make" not found, link time optimization will be '
-'single threaded.')
-
-for var in

[gem5-dev] Change in gem5/gem5[develop]: ext: Add a cont_choice keyword to kconfiglib.

2022-03-28 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56756 )


Change subject: ext: Add a cont_choice keyword to kconfiglib.
..

ext: Add a cont_choice keyword to kconfiglib.

This keyword lets you pick up a "choice" entry from elsewhere and add
new entries to it, greatly improving modularity of the Kconfig files.

Change-Id: Id20da6bc573e841e3ca7a42678911de827b53584
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56756
Maintainer: Gabe Black 
Tested-by: kokoro 
Reviewed-by: Andreas Sandberg 
---
M ext/Kconfiglib/import/kconfiglib.py
1 file changed, 51 insertions(+), 3 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/ext/Kconfiglib/import/kconfiglib.py  
b/ext/Kconfiglib/import/kconfiglib.py

index c67895c..e5c2dcc 100644
--- a/ext/Kconfiglib/import/kconfiglib.py
+++ b/ext/Kconfiglib/import/kconfiglib.py
@@ -2422,7 +2422,7 @@
 #
 # Named choices ('choice FOO') also end up here.

-if token is not _T_CHOICE:
+if token not in (_T_CHOICE, _T_CONTCHOICE):
 self._warn("style: quotes recommended around '{}'  
in '{}'"

.format(name, self._line.strip()),
self.filename, self.linenr)
@@ -3078,10 +3078,39 @@

 self._parse_props(node)
 self._parse_block(_T_ENDCHOICE, node, node)
-node.list = node.next

+node.list = node.next
 prev.next = prev = node

+elif t0 is _T_CONTCHOICE:
+# Named choice
+name = self._expect_str_and_eol()
+choice = self.named_choices.get(name)
+if not choice:
+self._parse_error(f"can't continue choice '{name}'")
+
+assert(len(choice.nodes))
+# Add more to the earlier node.
+node = choice.nodes[-1]
+
+# Find the end of its list so we can add to it.
+if node.list:
+sub_prev = node.list
+while sub_prev.next:
+sub_prev = sub_prev.next
+else:
+# If we don't have a list at all, temporarily make one  
up.

+sub_prev = MenuNode()
+
+# Parse any new properties.
+self._parse_props(node)
+# Read in new subnodes.
+self._parse_block(_T_ENDCHOICE, node, sub_prev)
+
+# If we made up a lead node, move the list to where it  
belongs.

+if not node.list:
+node.list = sub_prev.next
+
 elif t0 is _T_MAINMENU:
 self.top_node.prompt = (self._expect_str_and_eol(), self.y)

@@ -6856,6 +6885,7 @@
 _T_CLOSE_PAREN,
 _T_COMMENT,
 _T_CONFIG,
+_T_CONTCHOICE,
 _T_DEFAULT,
 _T_DEFCONFIG_LIST,
 _T_DEF_BOOL,
@@ -6899,7 +6929,7 @@
 _T_TRISTATE,
 _T_UNEQUAL,
 _T_VISIBLE,
-) = range(1, 51)
+) = range(1, 52)

 # Keyword to token map, with the get() method assigned directly as a small
 # optimization
@@ -6911,6 +6941,7 @@
 "choice": _T_CHOICE,
 "comment":_T_COMMENT,
 "config": _T_CONFIG,
+"cont_choice":_T_CONTCHOICE,
 "def_bool":   _T_DEF_BOOL,
 "def_hex":_T_DEF_HEX,
 "def_int":_T_DEF_INT,
@@ -7024,6 +7055,7 @@
 _T_BOOL,
 _T_CHOICE,
 _T_COMMENT,
+_T_CONTCHOICE,
 _T_HEX,
 _T_INT,
 _T_MAINMENU,

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/56756
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id20da6bc573e841e3ca7a42678911de827b53584
Gerrit-Change-Number: 56756
Gerrit-PatchSet: 13
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Jason Lowe-Power 
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: tests,gpu-compute,mem-ruby: Add GPU Ruby random test

2022-03-28 Thread Bobby Bruce (Gerrit) via gem5-dev 
Bobby Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58270 )



Change subject: tests,gpu-compute,mem-ruby: Add GPU Ruby random test
..

tests,gpu-compute,mem-ruby: Add GPU Ruby random test

This adds the GPU protocol random tester to the quick/Kokoro tests. The
input has been sized to take around 20 seconds and provides good
coverage for the coherence protocol.

This test can be run with the following:

```
cd tests
./main.py run -j`nproc` gem5/gpu
```

Change-Id: I08d199f0de8cca985f992b7f39b5f82e4218c82d
---
A tests/gem5/gpu/test_gpu_ruby_random.py
1 file changed, 83 insertions(+), 0 deletions(-)



diff --git a/tests/gem5/gpu/test_gpu_ruby_random.py  
b/tests/gem5/gpu/test_gpu_ruby_random.py

new file mode 100644
index 000..81fb281
--- /dev/null
+++ b/tests/gem5/gpu/test_gpu_ruby_random.py
@@ -0,0 +1,63 @@
+# Copyright (c) 2022 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+This test will first run the GPU protocol random tester -- it should take  
about

+30 seconds to run and provides good coverage for the coherence protocol.
+
+Input choices (some are default and thus implicit):
+ - use small cache size to encourage races
+ - use small system size to encourage races since more requests per CU (and
+   faster sim)
+ - use small address range to encourage more races
+ - use small episode length to encourage more races
+ - 50K tests runs in ~30 seconds with reasonably good coverage
+ - num-dmas = 0 because VIPER doesn't support partial cache line writes,  
which

+   DMAs need
+"""
+
+from testlib import *
+
+gem5_verify_config(
+name="ruby-gpu-random-test",
+fixtures=(),
+verifiers=(),
+config=joinpath(
+config.base_dir,
+"configs",
+"example",
+"ruby_gpu_random_test.py",
+),
+config_args=[
+"--test-length",
+"5",
+"--num-dmas",
+"0",
+],
+valid_isas=(constants.gcn3_x86_tag,),
+valid_hosts=constants.supported_hosts,
+length=constants.quick_tag,
+)
\ No newline at end of file

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/58270
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I08d199f0de8cca985f992b7f39b5f82e4218c82d
Gerrit-Change-Number: 58270
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby Bruce 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: tests: Remove accidentally included "exit 0" test code

2022-03-28 Thread Bobby Bruce (Gerrit) via gem5-dev 
Bobby Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58269 )



Change subject: tests: Remove accidentally included "exit 0" test code
..

tests: Remove accidentally included "exit 0" test code

This "exit 0" line was included accidentally in this commit:
https://gem5-review.googlesource.com/c/public/gem5/+/58169

It should not have been included, it was for testing purposes only.

Change-Id: Ia4be334d773bbb998906b0f0ae980f9ed14c87b4
---
M tests/nightly.sh
1 file changed, 14 insertions(+), 1 deletion(-)



diff --git a/tests/nightly.sh b/tests/nightly.sh
index b02f05b..7b784b2 100755
--- a/tests/nightly.sh
+++ b/tests/nightly.sh
@@ -88,7 +88,6 @@

 # Try to build the ISA targets.
 build_target NULL
-exit 0
 build_target RISCV
 build_target X86
 build_target ARM

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/58269
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia4be334d773bbb998906b0f0ae980f9ed14c87b4
Gerrit-Change-Number: 58269
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby Bruce 
Gerrit-MessageType: newchange
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-dev] Change in gem5/gem5[develop]: mem: Add SharedMemoryServer

2022-03-28 Thread Jui-min Lee (Gerrit) via gem5-dev 
Jui-min Lee has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/57729 )


Change subject: mem: Add SharedMemoryServer
..

mem: Add SharedMemoryServer

Add an utility class that provides a service for another process
query and get the fd of the corresponding region in gem5's physmem.

Basically, the service works in this way:
1. client connect to the unix socket created by a SharedMemoryServer
2. client send a request {start, end} to gem5
3. the server locates the corresponding shared memory
4. gem5 response {offset} and pass {fd} in ancillary data

mmap fd at offset will provide the client the view into the physical
memory of the request range.

Change-Id: I9d42fd8a41fc28dcfebb45dec10bc9ebb8e21d11
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57729
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Reviewed-by: Boris Shingarov 
Tested-by: kokoro 
---
M src/base/socket.hh
M src/mem/SConscript
A src/mem/SharedMemoryServer.py
M src/mem/physical.cc
M src/mem/physical.hh
A src/mem/shared_memory_server.cc
A src/mem/shared_memory_server.hh
7 files changed, 410 insertions(+), 11 deletions(-)

Approvals:
  Boris Shingarov: Looks good to me, approved
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/base/socket.hh b/src/base/socket.hh
index 4ed6185..3375ccc 100644
--- a/src/base/socket.hh
+++ b/src/base/socket.hh
@@ -62,14 +62,6 @@
  */
 static void cleanup();

-  private:
-/* Create a socket, adding SOCK_CLOEXEC if available. */
-static int socketCloexec(int domain, int type, int protocol);
-/* Accept a connection, adding SOCK_CLOEXEC if available. */
-static int acceptCloexec(int sockfd, struct sockaddr *addr,
-  socklen_t *addrlen);
-
-
   public:
 /**
  * @ingroup api_socket
@@ -84,6 +76,12 @@

 int getfd() const { return fd; }
 bool islistening() const { return listening; }
+
+/* Create a socket, adding SOCK_CLOEXEC if available. */
+static int socketCloexec(int domain, int type, int protocol);
+/* Accept a connection, adding SOCK_CLOEXEC if available. */
+static int acceptCloexec(int sockfd, struct sockaddr *addr,
+  socklen_t *addrlen);
 /** @} */ // end of api_socket
 };

diff --git a/src/mem/SConscript b/src/mem/SConscript
index 7790e1d..e07942e 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -56,6 +56,7 @@
 SimObject('ExternalMaster.py', sim_objects=['ExternalMaster'])
 SimObject('ExternalSlave.py', sim_objects=['ExternalSlave'])
 SimObject('CfiMemory.py', sim_objects=['CfiMemory'])
+SimObject('SharedMemoryServer.py', sim_objects=['SharedMemoryServer'])
 SimObject('SimpleMemory.py', sim_objects=['SimpleMemory'])
 SimObject('XBar.py', sim_objects=[
 'BaseXBar', 'NoncoherentXBar', 'CoherentXBar', 'SnoopFilter'])
@@ -80,6 +81,7 @@
 Source('packet_queue.cc')
 Source('port_proxy.cc')
 Source('physical.cc')
+Source('shared_memory_server.cc')
 Source('simple_mem.cc')
 Source('snoop_filter.cc')
 Source('stack_dist_calc.cc')
diff --git a/src/mem/SharedMemoryServer.py b/src/mem/SharedMemoryServer.py
new file mode 100644
index 000..3a63f45
--- /dev/null
+++ b/src/mem/SharedMemoryServer.py
@@ -0,0 +1,15 @@
+from m5.SimObject import SimObject
+from m5.params import Param
+from m5.proxy import Parent
+
+
+class SharedMemoryServer(SimObject):
+type = "SharedMemoryServer"
+cxx_header = "mem/shared_memory_server.hh"
+cxx_class = "gem5::memory::SharedMemoryServer"
+
+system = Param.System(
+Parent.any,
+"The system where the target shared memory is actually stored.")
+server_path = Param.String(
+"The unix socket path where the server should be running upon.")
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 08707eb..cae37a0 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -247,7 +247,8 @@
 // remember this backing store so we can checkpoint it and unmap
 // it appropriately
 backingStore.emplace_back(range, pmem,
-  conf_table_reported, in_addr_map, kvm_map);
+  conf_table_reported, in_addr_map, kvm_map,
+  shm_fd, map_offset);

 // point the memories to their backing store
 for (const auto& m : _memories) {
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index ff0dc61..3a976ed 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -70,9 +70,11 @@
  * pointers, because PhysicalMemory is responsible for that.
  */
 BackingStoreEntry(AddrRange range, uint8_t* pmem,
-  bool conf_table_reported, bool in_addr_map, bool  
kvm_map)
+  bool conf_table_reported, bool in_addr_map, bool  
kvm_map,

+  int shm_fd=-1, off_t shm_offset=0)
 : range(range),