[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Ensure the fast model license count is always at least 1.
Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/58490 ) Change subject: scons: Ensure the fast model license count is always at least 1. .. scons: Ensure the fast model license count is always at least 1. Even though the default value for the license count is 1, it seems that if fast model is disabled, kconfig will set it to 0. When creating a cycle using itertools over a list with zero elements, it will raise a StopIteration. Even though we don't actually try to build any fast model components in that case, we do still set them up with a license slot. If the cycle iterator is essentially broken, that will prevent that from working and break the build. This change forces the license count to be at least 1, even if fast model is disabled and the license count may be set to 0 in the config. Change-Id: Ia8df256a8f292deb6fb6fa3c5f9a7d58c2b7f782 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58490 Reviewed-by: Andreas Sandberg Maintainer: Gabe Black Tested-by: kokoro --- M src/arch/arm/fastmodel/SConscript 1 file changed, 30 insertions(+), 1 deletion(-) Approvals: Andreas Sandberg: Looks good to me, approved Gabe Black: Looks good to me, approved kokoro: Regressions pass diff --git a/src/arch/arm/fastmodel/SConscript b/src/arch/arm/fastmodel/SConscript index 23ddb84..b8ee987 100644 --- a/src/arch/arm/fastmodel/SConscript +++ b/src/arch/arm/fastmodel/SConscript @@ -268,7 +268,10 @@ t[0] = t[1] -license_count = int(env['CONF']['ARMLMD_LICENSE_COUNT']) +# If fast model is disabled, ARMLMD_LICENSE_COUNT will be 0 which will break +# the cycle() iterator below. The fast model components won't be built, but +# they still need to be set up successfully with valid license slots. +license_count = max(int(env['CONF']['ARMLMD_LICENSE_COUNT']), 1) arm_licenses = list((Value(object()) for i in range(license_count))) license_cycle = cycle(arm_licenses) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/58490 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ia8df256a8f292deb6fb6fa3c5f9a7d58c2b7f782 Gerrit-Change-Number: 58490 Gerrit-PatchSet: 3 Gerrit-Owner: Gabe Black Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: Earl Ou Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jui-min Lee Gerrit-Reviewer: Sudhanshu Jha Gerrit-Reviewer: Yu-hsin Wang Gerrit-Reviewer: kokoro Gerrit-CC: Gabe Black Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Fix script failed when default files not found
Yu-hsin Wang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/58809 )
Change subject: scons: Fix script failed when default files not found
..
scons: Fix script failed when default files not found
Change-Id: Ic673783cb5050159a141a869ca17b1ac09a924ef
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58809
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M SConstruct
1 file changed, 14 insertions(+), 1 deletion(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/SConstruct b/SConstruct
index cf130c1..95ebff1 100755
--- a/SConstruct
+++ b/SConstruct
@@ -633,7 +633,7 @@
(' or '.join(current_vars_files), default_vars_file))
else:
error("Cannot find variables file(s) %s or default
file(s) %s" %
-(' or '.join(current_vars_file),
+(' or '.join(current_vars_files),
' or '.join(default_vars_files)))
Exit(1)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic673783cb5050159a141a869ca17b1ac09a924ef
Gerrit-Change-Number: 58809
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch: Eliminate the now unused read_code and write_code args.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49743 )
(
64 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch: Eliminate the now unused read_code and write_code
args.
..
arch: Eliminate the now unused read_code and write_code args.
Also eliminate the buildReadCode and buildWriteCode methods.
Change-Id: I27b1b87ab51a44b5d7280e29e22f38d97d968a65
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49743
Maintainer: Gabe Black
Maintainer: Giacomo Travaglini
Reviewed-by: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/isa_parser/operand_types.py
1 file changed, 17 insertions(+), 57 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/isa_parser/operand_types.py
b/src/arch/isa_parser/operand_types.py
index a9f5eab..897235a 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -45,8 +45,7 @@
class OperandDesc(object):
def __init__(self, base_cls, dflt_ext, reg_spec, flags=None,
-sort_pri=None, read_code=None, write_code=None,
-read_predicate=None, write_predicate=None):
+sort_pri=None, read_predicate=None, write_predicate=None):
from .isa_parser import makeList
@@ -97,8 +96,6 @@
'reg_spec': reg_spec,
'flags': flags,
'sort_pri': sort_pri,
-'read_code': read_code,
-'write_code': write_code,
'read_predicate': read_predicate,
'write_predicate': write_predicate,
})
@@ -118,28 +115,6 @@
src_reg_constructor = '\n\tsetSrcRegIdx(_numSrcRegs++, %s);'
dst_reg_constructor = '\n\tsetDestRegIdx(_numDestRegs++, %s);'
-def buildReadCode(self, pred_read, op_idx):
-subst_dict = {"name": self.base_name,
- "reg_idx": self.reg_spec,
- "ctype": self.ctype,
- "op_idx": op_idx}
-code = self.read_code % subst_dict
-return f'{self.base_name} = {code};\n'
-
-def buildWriteCode(self, pred_write, op_idx):
-subst_dict = {"name": self.base_name,
- "reg_idx": self.reg_spec,
- "ctype": self.ctype,
- "final_val": self.base_name,
- "op_idx": op_idx}
-code = self.write_code % subst_dict
-return f'''
-{{
-{self.ctype} final_val = {self.base_name};
-{code};
-if (traceData) {{ traceData->setData(final_val); }}
-}}'''
-
def regId(self):
return f'RegId({self.reg_class}, {self.reg_spec})'
@@ -260,9 +235,6 @@
class RegValOperand(RegOperand):
def makeRead(self, pred_read, op_idx):
-if self.read_code != None:
-return self.buildReadCode(pred_read, op_idx)
-
reg_val = f'xc->getRegOperand(this, {op_idx})'
if self.ctype == 'float':
@@ -276,9 +248,6 @@
return f'{self.base_name} = {reg_val};\n'
def makeWrite(self, pred_write, op_idx):
-if self.write_code != None:
-return self.buildWriteCode(pred_write, op_idx)
-
reg_val = self.base_name
if self.ctype == 'float':
@@ -363,8 +332,6 @@
return c_read
def makeReadW(self, pred_write, op_idx):
-assert(self.read_code == None)
-
c_readw = f'\t\tauto _d{op_idx} = \n' \
f'\t\t*({self.parser.namespace}::VecRegContainer
*)\n' \
f'\t\txc->getWritableRegOperand(this, {op_idx});\n'
@@ -395,9 +362,6 @@
return c_read
def makeRead(self, pred_read, op_idx):
-if self.read_code != None:
-return self.buildReadCode(pred_read, op_idx)
-
name = self.base_name
if self.is_dest and self.is_src:
name += '_merger'
@@ -420,9 +384,6 @@
return c_read
def makeWrite(self, pred_write, op_idx):
-if self.write_code != None:
-return self.buildWriteCode(pred_write, op_idx)
-
return f'''
if (traceData) {{
traceData->setData(tmp_d{op_idx});
@@ -446,9 +407,6 @@
return ''
def makeRead(self, pred_read, op_idx):
-if self.read_code != None:
-return self.buildReadCode(pred_read, op_idx)
-
c_read = f'\t\t{self.parser.namespace}::VecPredRegContainer ' \
f'\t\ttmp_s{op_idx}; ' \
f'xc->getRegOperand(this, {op_idx}, _s{op_idx});\n'
@@ -459,8 +417,6 @@
return c_read
def makeReadW(self, pred_write, op_idx):
-assert(self.read_code == None)
-
c_readw = f'\t\tauto _d{op_idx} = \n' \
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-x86: Override make(Read|Write) instead of (read|write)_code.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49741 )
Change subject: arch-x86: Override make(Read|Write) instead of (read|
write)_code.
..
arch-x86: Override make(Read|Write) instead of (read|write)_code.
Change-Id: Iab077f58e19aa6bfeed555caa31a4c8b3d261059
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49741
Tested-by: kokoro
Reviewed-by: Gabe Black
Maintainer: Gabe Black
---
M src/arch/x86/isa/operands.isa
1 file changed, 31 insertions(+), 9 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 2eaab4b..afbb8a0 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -55,20 +55,29 @@
let {{
class IntReg(IntRegOp):
-def __init__(self, idx, id, *args, **kwargs):
+def __init__(self, idx, id, data_size='dataSize', *args, **kwargs):
super().__init__('uqw', idx, 'IsInteger', id, *args, **kwargs)
+self.attrs['data_size'] = data_size
class PickedReg(IntReg):
-def __init__(self, idx, id, size='dataSize'):
-super().__init__(idx, id,
-read_code='pick(xc->getRegOperand(this, %(op_idx)s), '
- '%(reg_idx)s, ' + size + ')')
+@overrideInOperand
+def makeRead(self, predRead, op_idx):
+return f'{self.base_name} = pick(xc->getRegOperand(' \
+f'this, {op_idx}), {self.reg_spec}, ' \
+f'{self.data_size});\n'
+
+def __init__(self, idx, id, data_size='dataSize'):
+super().__init__(idx, id, data_size)
class SignedPickedReg(IntReg):
-def __init__(self, idx, id, size='dataSize'):
-super().__init__(idx, id,
-read_code='signedPick(xc->getRegOperand(this, '
-'%(op_idx)s), %(reg_idx)s, ' + size + ')')
+@overrideInOperand
+def makeRead(self, predRead, op_idx):
+return f'{self.base_name} = signedPick(xc->getRegOperand(' \
+f'this, {op_idx}), {self.reg_spec}, ' \
+f'{self.data_size});\n'
+
+def __init__(self, idx, id, data_size='dataSize'):
+super().__init__(idx, id, data_size)
class FloatReg(FloatRegOp):
def __init__(self, idx, id):
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iab077f58e19aa6bfeed555caa31a4c8b3d261059
Gerrit-Change-Number: 49741
Gerrit-PatchSet: 67
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Bradford Beckmann
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Matt Sinclair
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib: Allow riscv-board to take more than 1 disk image
Hoa Nguyen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/58791 ) Change subject: stdlib: Allow riscv-board to take more than 1 disk image .. stdlib: Allow riscv-board to take more than 1 disk image This is done by, - Decoupling (PIO/VirtIO devices connection/device tree generation) and the (set disk image workload function). - Creating an abstract method for finializing all connections and device tree generation in KernelDiskWorkload. - The board now takes the `addtional_disk_array` parameter, which contains a list of disk image resources. Those images should not be mounted during kernel booting. - The old `disk_image` parameter will now become the root disk image param. This disk image should be mounted as '/' by the kernel. Change-Id: I560496a4db5b4d91d3e3e90901487d8d40bf581b Signed-off-by: Hoa Nguyen --- M src/python/gem5/components/boards/kernel_disk_workload.py M src/python/gem5/components/boards/riscv_board.py 2 files changed, 85 insertions(+), 26 deletions(-) diff --git a/src/python/gem5/components/boards/kernel_disk_workload.py b/src/python/gem5/components/boards/kernel_disk_workload.py index 031fc60..bfd5aa6 100644 --- a/src/python/gem5/components/boards/kernel_disk_workload.py +++ b/src/python/gem5/components/boards/kernel_disk_workload.py @@ -97,6 +97,17 @@ """ raise NotImplementedError +@abstractmethod +def _finalize_workload(self) -> None: +""" +Finalizes the board setup dependent on the workload. +This function connects the IO devices to the board, generates the +device tree and expose the location of the dtb to the gem5's workload +object. This function should be called after all IO devices are set up +(e.g. disk images, PIO devices.) +""" +raise NotImplementedError + def get_disk_root_partition( cls, disk_image: AbstractResource ) -> Optional[str]: @@ -132,7 +143,8 @@ def set_kernel_disk_workload( self, kernel: AbstractResource, -disk_image: AbstractResource, +root_disk_image: AbstractResource, +additional_disk_array: List[AbstractResource], readfile: Optional[str] = None, readfile_contents: Optional[str] = None, kernel_args: Optional[List[str]] = None, @@ -143,7 +155,10 @@ and a disk image. :param kernel: The kernel to boot. -:param disk_image: The disk image to mount. +:param root_disk_image: The disk image containing the '/' mount point. +:param additional_disk_array: An array of disk images to be mount +manually (they are not mounted at durring the Linux kernel booting +process). :param readfile: An optional parameter stating the file to be read by by `m5 readfile`. :param readfile_contents: An optional parameter stating the contents of @@ -163,7 +178,9 @@ self.workload.command_line = ( " ".join(kernel_args or self.get_default_kernel_args()) ).format( - root_value=self.get_default_kernel_root_val(disk_image=disk_image) +root_value=self.get_default_kernel_root_val( +disk_image=root_disk_image +) ) # Set the readfile. @@ -178,7 +195,12 @@ file.write(readfile_contents) file.close() -self._add_disk_to_board(disk_image=disk_image) +self._add_disk_to_board(disk_image=root_disk_image) +for disk_image in additional_disk_array: +self._add_disk_to_board(disk_image=disk_image) + +# Finalize the setup after all components of the workload are set. +self._finalize_workload() # Set whether to exit on work items. -self.exit_on_work_items = exit_on_work_items \ No newline at end of file +self.exit_on_work_items = exit_on_work_items diff --git a/src/python/gem5/components/boards/riscv_board.py b/src/python/gem5/components/boards/riscv_board.py index f72b31d..b227b39 100644 --- a/src/python/gem5/components/boards/riscv_board.py +++ b/src/python/gem5/components/boards/riscv_board.py @@ -116,12 +116,7 @@ self.iobus.default = self.iobus.badaddr_responder.pio # The virtio disk -self.disk = RiscvMmioVirtIO( -vio=VirtIOBlock(), -interrupt_id=0x8, -pio_size=4096, -pio_addr=0x10008000, -) +self.disk_array = [] # The virtio rng self.rng = RiscvMmioVirtIO( @@ -134,7 +129,8 @@ # Note: This overrides the platform's code because the platform isn't # general enough. self._on_chip_devices = [self.platform.clint, self.platform.plic] -self._off_chip_devices = [self.platform.uart, self.disk, self.rng] +self._off_chip_devices = [self.platform.uart,
[gem5-dev] [S] Change in gem5/gem5[develop]: configs: Fix the command in the comment of arm-hello.py
Hoa Nguyen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/58830 ) Change subject: configs: Fix the command in the comment of arm-hello.py .. configs: Fix the command in the comment of arm-hello.py Change-Id: I5e020e066c0f6792077fbf2ef65b7f90bb9c37f9 Signed-off-by: Hoa Nguyen --- M configs/example/gem5_library/arm-hello.py 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/configs/example/gem5_library/arm-hello.py b/configs/example/gem5_library/arm-hello.py index 3faa3ed..264731f 100644 --- a/configs/example/gem5_library/arm-hello.py +++ b/configs/example/gem5_library/arm-hello.py @@ -37,7 +37,7 @@ ``` scons build/ARM/gem5.opt -./build/ARM/gem5.opt configs/gem5_library/arm-hello.py +./build/ARM/gem5.opt configs/example/gem5_library/arm-hello.py ``` """ -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/58830 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I5e020e066c0f6792077fbf2ef65b7f90bb9c37f9 Gerrit-Change-Number: 58830 Gerrit-PatchSet: 1 Gerrit-Owner: Hoa Nguyen Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] [M] Change in gem5/gem5[develop]: stdlib, configs: Add examples of saving/restoring checkpoints
Hoa Nguyen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/58829 ) Change subject: stdlib, configs: Add examples of saving/restoring checkpoints .. stdlib, configs: Add examples of saving/restoring checkpoints This change consists of two scripts, - riscv-hello-save-checkpoint.py: runs the first million ticks of the simulation and save a checkpoint. - riscv-hello-load-checkpoint.py: loads the above checkpoint, and runs the rest of the simulation. Change-Id: I7bd97ba953fab52f298cbbcf213f2ea5c185cc38 Signed-off-by: Hoa Nguyen --- A configs/example/gem5_library/checkpoints/riscv-hello-restore-checkpoint.py A configs/example/gem5_library/checkpoints/riscv-hello-save-checkpoint.py 2 files changed, 231 insertions(+), 0 deletions(-) diff --git a/configs/example/gem5_library/checkpoints/riscv-hello-restore-checkpoint.py b/configs/example/gem5_library/checkpoints/riscv-hello-restore-checkpoint.py new file mode 100644 index 000..a7e1d52 --- /dev/null +++ b/configs/example/gem5_library/checkpoints/riscv-hello-restore-checkpoint.py @@ -0,0 +1,108 @@ +# Copyright (c) 2022 The Regents of the University of California +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +""" +This gem5 configuation script creates a simple board sharing the same +structure as the one in +configs/example/gem5_library/checkpoint/riscv-hello-save-checkpoint.py. +This script restores the checkpoint generated by the above script, and +runs the rest of "riscv-hello" binary simulation. +This configuration serves as an example of restoring a checkpoint. + +This is setup is the close to the simplest setup possible using the gem5 +library. It does not contain any kind of caching, IO, or any non-essential +components. + +Usage +- + +``` +scons build/RISCV/gem5.opt +./build/RISCV/gem5.opt \ + configs/example/gem5_library/checkpoint/riscv-hello-restore-checkpoint.py +``` +""" + +from gem5.isas import ISA +from gem5.utils.requires import requires +from gem5.resources.resource import Resource +from gem5.components.memory import SingleChannelDDR3_1600 +from gem5.components.processors.cpu_types import CPUTypes +from gem5.components.boards.simple_board import SimpleBoard +from gem5.components.cachehierarchies.classic.no_cache import NoCache +from gem5.components.processors.simple_processor import SimpleProcessor +from gem5.simulate.simulator import Simulator + +# This check ensures the gem5 binary is compiled to the RISCV ISA target. +# If not, an exception will be thrown. +requires(isa_required=ISA.RISCV) + +# In this setup we don't have a cache. `NoCache` can be used for such setups. +cache_hierarchy = NoCache() + +# We use a single channel DDR3_1600 memory system +memory = SingleChannelDDR3_1600(size="32MB") + +# We use a simple Timing processor with one core. +processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, isa=ISA.RISCV, +num_cores=1) + +# The gem5 library simble board which can be used to run simple SE-mode +# simulations. +board = SimpleBoard( +clk_freq="3GHz", +processor=processor, +memory=memory, +cache_hierarchy=cache_hierarchy, +) + +# Here we set the workload. In this case we want to run a simple "Hello World!" +# program compiled to the RISCV ISA. The `Resource` class will automatically +# download the binary from the gem5 Resources cloud bucket if it's not already +# present. +board.set_se_binary_workload( +
[gem5-dev] Re: Request for comments/reviews: Multiple Ruby protocols in a single binary
Hi all, I would really appreciate some reviews on these changes. This is something that I know many in the development community (Andreas, Gabe, others) have been asking for. Please take a look! I think most changes are pretty straightforward. There is one change where I would like some specific feedback on a good way to incorporate multiple Ruby protocols into the SConscript ( https://gem5-review.googlesource.com/c/public/gem5/+/58443/2) Hi Giacomo, I dug into the idea you proposed a bit more today, and I'm pretty convinced that it would be significant work. It's possible to make a SimObject be part of a submodule of m5.objects. However, the problem comes in the params. I don't think there's an easy way to create two params/.hh files for SimObjects which have the same name. Basically, we have a strong assumption in the SimObject generation code that no two SimObjects will have exactly the same name. Extending this to allow SimObjects with the same name would be quite a bit of effort. Right now, I don't believe this effort is worth the benefit for this set of changes. Let me know what you think. Cheers, Jason On Fri, Apr 1, 2022 at 7:48 AM Jason Lowe-Power wrote: > Sounds like a good idea. But I don't know how to do this easily. All > SimObjects are part of the m5.object module, and this is deeply embedded in > many different parts of gem5. > > My best guess at how to do this would be to add a new type of SimObject > which is not in m5.objects, but in a submodule. Then, we would also have to > extend the Scons concept of "SimObject" and how scons creates the SimObject > params files and the python m5.objects files. My initial thought is that > this would be a lot more work. I could be wrong, though. > > If you have a specific idea on how to implement this, or if you can > provide an implementation, I can try to integrate it with what I have done. > > Either way, it will require non-backwards compatible changes to configs to > import the correct module or use the new names. I'm not sure the benefit is > worth the investment, though. > > Let me know what you think :) > > Cheers, > Jason > > > > On Fri, Apr 1, 2022 at 7:31 AM Giacomo Travaglini < > giacomo.travagl...@arm.com> wrote: > >> Congrats to Jason and to everyone who’s making this possible! >> >> >> >> About the naming, I wonder if we could provide a different python module >> per ruby protocol. >> >> That would allow us to avoid prefixing in favour of something like: >> >> >> $from m5.objects.mi_example import L1Cache_Controller >> >> >> >> or >> >> >> $from m5.objects.msi import L1Cache_Controller >> >> >> >> Kind Regards >> >> >> >> Giacomo >> >> >> >> >> >> *From: *Jason Lowe-Power via gem5-dev >> *Date: *Thursday, 31 March 2022 at 18:43 >> *To: *gem5 Developer List >> *Cc: *Jason Lowe-Power >> *Subject: *[gem5-dev] Request for comments/reviews: Multiple Ruby >> protocols in a single binary >> >> Hi all, >> >> >> >> For as long as gem5 has been gem5, you have had to build a different gem5 >> binary if you want to use a different Ruby protocol. Making it possible to >> build multiple protocols has been on the roadmap for a long time (at least >> as long as I've been involved with the project). >> >> >> >> I'm excited to say that we've been able to do this (finally), and we have >> a set of changesets on gerrit for review/comments feedback. >> >> >> >> There are a couple of todo items before it's merged, and a couple of >> user-facing changes that we could not find a way to make fully backwards >> compatible. More on this below. >> >> >> >> Let me know what you think, and let me know if there are any questions! >> I'm excited to see this get in for gem5-22.0. >> >> >> >> Changes: https://gem5-review.googlesource.com/q/topic:all-ruby-protocols >> >> >> >> *Non-backwards compatible changes:* >> >> Previously each SLICC protocol used the same names for the same machine >> time. E.g., MI_example has an `L1Cache_Controller` and MSI has an >> `L1Cache_Controller`. These names were automatically generated from the >> MachineType (L1Cache) + "_Controller". Now, since we want to be able to >> compile these two protocols at the same time, we need to make sure there >> are no (python) name clashes. So, these have been renamed to have the >> protocol name prepended onto the machine name (e.g., >> `MI_example_L1Cache_Controller`). >> >> >> >> For most people using Ruby, we can provide backwards compatibility. If >> you simply instantiate the `L1Cache_Controller` in python, we can provide a >> new factory function that does the "right" thing. However, if you inherit >> from `L1Cache_Controller` to specialize the controller, this won't work. >> >> >> >> *The user-facing change is* if you have any local ruby protocol >> configuration files which use inheritance with the controllers, you will >> have to update the controller classes to use the name of the protocol >> prepended on the controller name. >> >> >> >> We have updated all of the
[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Fix bug in error message
Jason Lowe-Power has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/58429 ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: scons: Fix bug in error message .. scons: Fix bug in error message The variable p doesn't exist in the context. Just remove the extra print. Even without the specific variable printed the error message is pretty helpful. Change-Id: If681d686c228c1362b8cc46cb14a94d7302f3793 Signed-off-by: Jason Lowe-Power Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58429 Reviewed-by: Daniel Carvalho Maintainer: Gabe Black Tested-by: kokoro --- M build_tools/sim_object_param_struct_hh.py 1 file changed, 19 insertions(+), 1 deletion(-) Approvals: Daniel Carvalho: Looks good to me, approved Gabe Black: Looks good to me, approved kokoro: Regressions pass diff --git a/build_tools/sim_object_param_struct_hh.py b/build_tools/sim_object_param_struct_hh.py index ff525ee..261ac9b 100644 --- a/build_tools/sim_object_param_struct_hh.py +++ b/build_tools/sim_object_param_struct_hh.py @@ -73,7 +73,7 @@ try: ptypes = [p.ptype for p in params] except: -print(sim_object, p, p.ptype_str) +print(sim_object) print(params) raise -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/58429 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: If681d686c228c1362b8cc46cb14a94d7302f3793 Gerrit-Change-Number: 58429 Gerrit-PatchSet: 4 Gerrit-Owner: Jason Lowe-Power Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib, configs: Migrate riscv-ubuntu-run example to Simulator
Hoa Nguyen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/58790 )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: stdlib, configs: Migrate riscv-ubuntu-run example to
Simulator
..
stdlib, configs: Migrate riscv-ubuntu-run example to Simulator
Change-Id: Ie08fcf46139871bc98b9bf783d0b4d9913eace3e
Signed-off-by: Hoa Nguyen
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58790
Reviewed-by: Jason Lowe-Power
Reviewed-by: Bobby Bruce
Maintainer: Jason Lowe-Power
Maintainer: Bobby Bruce
Tested-by: kokoro
---
M configs/example/gem5_library/riscv-ubuntu-run.py
1 file changed, 19 insertions(+), 29 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/example/gem5_library/riscv-ubuntu-run.py
b/configs/example/gem5_library/riscv-ubuntu-run.py
index d54fa90..1c95d3f 100644
--- a/configs/example/gem5_library/riscv-ubuntu-run.py
+++ b/configs/example/gem5_library/riscv-ubuntu-run.py
@@ -53,6 +53,7 @@
from gem5.isas import ISA
from gem5.coherence_protocol import CoherenceProtocol
from gem5.resources.resource import Resource
+from gem5.simulate.simulator import Simulator
# This runs a check to ensure the gem5 binary is compiled for RISCV.
@@ -116,32 +117,5 @@
root = Root(full_system=True, system=board)
-m5.instantiate()
-
-# We simulate the system till we encounter `m5_exit instruction
encountered`.
-
-exit_event = m5.simulate()
-
-# We check whether the simulation ended with `m5_exit instruction
encountered`
-
-if exit_event.getCause() == "m5_exit instruction encountered":
-# We acknowledge the user that the boot was successful.
-
-print("Successfully completed booting!")
-else:
-# `m5_exit instruction encountered` was never encountered. We exit the
-# program unsuccessfully.
-
-print("The startup was not completed successfully!",)
-print(
-"Exiting @ tick {} because {}."\
-.format(m5.curTick(), exit_event.getCause())
-)
-exit(-1)
-
-# We are done with the simulation. We exit the program now.
-
-print(
-"Exiting @ tick {} because {}."\
-.format(m5.curTick(), exit_event.getCause())
-)
+simulator = Simulator(board=board)
+simulator.run()
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/58790
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie08fcf46139871bc98b9bf783d0b4d9913eace3e
Gerrit-Change-Number: 58790
Gerrit-PatchSet: 3
Gerrit-Owner: Hoa Nguyen
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Hoa Nguyen
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Disable failing 8-core Boot Tests for Timing/Atomic
Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/58770 )
Change subject: tests: Disable failing 8-core Boot Tests for Timing/Atomic
..
tests: Disable failing 8-core Boot Tests for Timing/Atomic
As noted here: https://gem5.atlassian.net/browse/GEM5-1217, the Atomic
and Timing Core systems are not working with 8 cores when run with a
classic or MI_example cache heirarchy. Until the root cause of this
issue can be determined. These tests are being disabled.
Change-Id: Ia19579029bd20c57cca8d225068d17c4b29f1773
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58770
Maintainer: Bobby Bruce
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
---
M tests/gem5/x86-boot-tests/test_linux_boot.py
1 file changed, 20 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Bobby Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/tests/gem5/x86-boot-tests/test_linux_boot.py
b/tests/gem5/x86-boot-tests/test_linux_boot.py
index ee9c257..7e3ad4e 100644
--- a/tests/gem5/x86-boot-tests/test_linux_boot.py
+++ b/tests/gem5/x86-boot-tests/test_linux_boot.py
@@ -238,13 +238,13 @@
1: True,
2: True,
4: False, # We already run this in the long (Nightly) tests.
-8: True,
+8: False, # Jira: https://gem5.atlassian.net/browse/GEM5-1217
},
"timing": {
1: True,
2: True,
4: True,
-8: True,
+8: False, # Jira: https://gem5.atlassian.net/browse/GEM5-1217
},
"o3": {
1: False, # Timeout
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/58770
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia19579029bd20c57cca8d225068d17c4b29f1773
Gerrit-Change-Number: 58770
Gerrit-PatchSet: 4
Gerrit-Owner: Bobby Bruce
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: mem-ruby: CHI fix for WUs on local+upstream line
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/57299 )
(
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: mem-ruby: CHI fix for WUs on local+upstream line
..
mem-ruby: CHI fix for WUs on local+upstream line
Fix for WriteUnique operations on cache lines that are both local and
upstream
JIRA: https://gem5.atlassian.net/browse/GEM5-1097
Change-Id: I99def32948d3f0ced9cfc7f7712a0f4ae9aab0cd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57299
Reviewed-by: Tiago Muck
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Maintainer: Bobby Bruce
Tested-by: kokoro
---
M src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
1 file changed, 31 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Tiago Muck: Looks good to me, approved
Bobby Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
b/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
index c4eb8ff..0f1a7c6 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
@@ -337,7 +337,7 @@
// WriteUniquePtl
-transition({UD,UD_RU,UD_RSD,UD_RSC,UC,UC_RU,UC_RSC},
+transition({UD,UD_RSD,UD_RSC,UC,UC_RSC},
{WriteUnique, WriteUniquePtl_PoC, WriteUniqueFull_PoC,
WriteUniqueFull_PoC_Alloc},
BUSY_BLKD) {
Initiate_Request;
@@ -347,6 +347,16 @@
ProcessNextState;
}
+transition({UD_RU,UC_RU},
+ {WriteUnique, WriteUniquePtl_PoC, WriteUniqueFull_PoC,
WriteUniqueFull_PoC_Alloc},
+ BUSY_BLKD) {
+ Initiate_Request;
+ Initiate_WriteUnique_LocalWrite;
+ Profile_Miss;
+ Pop_ReqRdyQueue;
+ ProcessNextState;
+}
+
transition({SD, SD_RSD, SD_RSC, SC, SC_RSC},
{WriteUniquePtl_PoC, WriteUniqueFull_PoC,
WriteUniqueFull_PoC_Alloc},
BUSY_BLKD) {
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/57299
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I99def32948d3f0ced9cfc7f7712a0f4ae9aab0cd
Gerrit-Change-Number: 57299
Gerrit-PatchSet: 7
Gerrit-Owner: Giacomo Travaglini
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-CC: Tiago Muck
Gerrit-MessageType: merged
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