[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Add missing ()s in get_supported_isas.

2022-04-16 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58929 )


Change subject: stdlib: Add missing ()s in get_supported_isas.
..

stdlib: Add missing ()s in get_supported_isas.

A function was used directly instead of being called when interating
through ISA names.

Change-Id: I9dc53259a766a68070e0b79bb55f721a93fcdeed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58929
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/python/gem5/runtime.py
1 file changed, 17 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/gem5/runtime.py b/src/python/gem5/runtime.py
index 108dfc4..0984f6f 100644
--- a/src/python/gem5/runtime.py
+++ b/src/python/gem5/runtime.py
@@ -48,7 +48,7 @@
 if "TARGET_ISA" in buildEnv.keys():
 supported_isas.add(get_isa_from_str(buildEnv["TARGET_ISA"]))
 else:
-for key in get_isas_str_set:
+for key in get_isas_str_set():
 if buildEnv[f"USE_{key.upper()}_ISA"]:
 supported_isas.add(get_isa_from_str(key))
 return supported_isas

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9dc53259a766a68070e0b79bb55f721a93fcdeed
Gerrit-Change-Number: 58929
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Jenkins build is back to normal : nightly #195

2022-04-16 Thread jenkins-no-reply--- via gem5-dev 
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[gem5-dev] [S] Change in gem5/gem5[develop]: configs: Fix the command in the comment of arm-hello.py

2022-04-16 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58830 )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: configs: Fix the command in the comment of arm-hello.py
..

configs: Fix the command in the comment of arm-hello.py

Change-Id: I5e020e066c0f6792077fbf2ef65b7f90bb9c37f9
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58830
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M configs/example/gem5_library/arm-hello.py
1 file changed, 15 insertions(+), 1 deletion(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/gem5_library/arm-hello.py  
b/configs/example/gem5_library/arm-hello.py

index 3faa3ed..264731f 100644
--- a/configs/example/gem5_library/arm-hello.py
+++ b/configs/example/gem5_library/arm-hello.py
@@ -37,7 +37,7 @@

 ```
 scons build/ARM/gem5.opt
-./build/ARM/gem5.opt configs/gem5_library/arm-hello.py
+./build/ARM/gem5.opt configs/example/gem5_library/arm-hello.py
 ```
 """


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5e020e066c0f6792077fbf2ef65b7f90bb9c37f9
Gerrit-Change-Number: 58830
Gerrit-PatchSet: 3
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: configs: Fix spelling mistakes.

2022-04-16 Thread WenDi Gan (Gerrit) via gem5-dev 
WenDi Gan has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58229 )


Change subject: configs: Fix spelling mistakes.
..

configs: Fix spelling mistakes.

Replace "fequency" to "frequency".

Change-Id: I307c8b6d8e60cfcb213f22aca3f6abd43c6b5b1e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58229
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/example/hmc_hello.py
M configs/example/hmctest.py
M configs/learning_gem5/part1/simple.py
M configs/learning_gem5/part1/two_level.py
M configs/learning_gem5/part2/simple_cache.py
M configs/learning_gem5/part2/simple_memobj.py
M configs/learning_gem5/part3/ruby_test.py
M configs/learning_gem5/part3/simple_ruby.py
8 files changed, 23 insertions(+), 8 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/hmc_hello.py b/configs/example/hmc_hello.py
index 4507768..11d52c0 100644
--- a/configs/example/hmc_hello.py
+++ b/configs/example/hmc_hello.py
@@ -49,7 +49,7 @@
 system = System()
 # use timing mode for the interaction between requestor-responder ports
 system.mem_mode = 'timing'
-# set the clock fequency of the system
+# set the clock frequency of the system
 clk = '1GHz'
 vd = VoltageDomain(voltage='1V')
 system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
diff --git a/configs/example/hmctest.py b/configs/example/hmctest.py
index f4c0a2c..429ea4a 100644
--- a/configs/example/hmctest.py
+++ b/configs/example/hmctest.py
@@ -50,7 +50,7 @@
 system = System()
 # use timing mode for the interaction between requestor-responder ports
 system.mem_mode = 'timing'
-# set the clock fequency of the system
+# set the clock frequency of the system
 clk = '100GHz'
 vd = VoltageDomain(voltage='1V')
 system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
diff --git a/configs/learning_gem5/part1/simple.py  
b/configs/learning_gem5/part1/simple.py

index 235165b..7810c3d 100644
--- a/configs/learning_gem5/part1/simple.py
+++ b/configs/learning_gem5/part1/simple.py
@@ -43,7 +43,7 @@
 # create the system we are going to simulate
 system = System()

-# Set the clock fequency of the system (and all of its children)
+# Set the clock frequency of the system (and all of its children)
 system.clk_domain = SrcClockDomain()
 system.clk_domain.clock = '1GHz'
 system.clk_domain.voltage_domain = VoltageDomain()
diff --git a/configs/learning_gem5/part1/two_level.py  
b/configs/learning_gem5/part1/two_level.py

index 591be0c..7a7956c 100644
--- a/configs/learning_gem5/part1/two_level.py
+++ b/configs/learning_gem5/part1/two_level.py
@@ -70,7 +70,7 @@
 # create the system we are going to simulate
 system = System()

-# Set the clock fequency of the system (and all of its children)
+# Set the clock frequency of the system (and all of its children)
 system.clk_domain = SrcClockDomain()
 system.clk_domain.clock = '1GHz'
 system.clk_domain.voltage_domain = VoltageDomain()
diff --git a/configs/learning_gem5/part2/simple_cache.py  
b/configs/learning_gem5/part2/simple_cache.py

index adda386..dc3a162 100644
--- a/configs/learning_gem5/part2/simple_cache.py
+++ b/configs/learning_gem5/part2/simple_cache.py
@@ -39,7 +39,7 @@
 # create the system we are going to simulate
 system = System()

-# Set the clock fequency of the system (and all of its children)
+# Set the clock frequency of the system (and all of its children)
 system.clk_domain = SrcClockDomain()
 system.clk_domain.clock = '1GHz'
 system.clk_domain.voltage_domain = VoltageDomain()
diff --git a/configs/learning_gem5/part2/simple_memobj.py  
b/configs/learning_gem5/part2/simple_memobj.py

index 49b0846..eaceae9 100644
--- a/configs/learning_gem5/part2/simple_memobj.py
+++ b/configs/learning_gem5/part2/simple_memobj.py
@@ -39,7 +39,7 @@
 # create the system we are going to simulate
 system = System()

-# Set the clock fequency of the system (and all of its children)
+# Set the clock frequency of the system (and all of its children)
 system.clk_domain = SrcClockDomain()
 system.clk_domain.clock = '1GHz'
 system.clk_domain.voltage_domain = VoltageDomain()
diff --git a/configs/learning_gem5/part3/ruby_test.py  
b/configs/learning_gem5/part3/ruby_test.py

index d0c3910..05096ec 100644
--- a/configs/learning_gem5/part3/ruby_test.py
+++ b/configs/learning_gem5/part3/ruby_test.py
@@ -44,7 +44,7 @@
 # create the system we are going to simulate
 system = System()

-# Set the clock fequency of the system (and all of its children)
+# Set the clock frequency of the system (and all of its children)
 system.clk_domain = SrcClockDomain()
 system.clk_domain.clock = '1GHz'
 system.clk_domain.voltage_domain = VoltageDomain()
diff --git a/configs/learning_gem5/part3/simple_ruby.py  
b/configs/learning_gem5/part3/simple_ruby.py

index