date:20221107

[gem5-dev] [M] Change in gem5/gem5[develop]: systemc: Add the stream id entry and its conversion in control extension

2022-11-07 Thread Han-sheng Liu (Gerrit) via gem5-dev

Han-sheng Liu has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65371?usp=email )



Change subject: systemc: Add the stream id entry and its conversion in  
control extension

..

systemc: Add the stream id entry and its conversion in control extension

stream id and substream id are properties of gem5 Request. This CL adds
the information into gem5 ControlExtension to manipulate them in SystemC
level, and adds the conversion between ControlExtension and Packet.

Change-Id: Id13d181561ba496c2012f7237eb800f0a9786d05
---
M src/systemc/tlm_bridge/sc_ext.cc
M src/systemc/tlm_bridge/sc_ext.hh
2 files changed, 67 insertions(+), 1 deletion(-)



diff --git a/src/systemc/tlm_bridge/sc_ext.cc  
b/src/systemc/tlm_bridge/sc_ext.cc

index 4d12fb3..95ce138 100644
--- a/src/systemc/tlm_bridge/sc_ext.cc
+++ b/src/systemc/tlm_bridge/sc_ext.cc
@@ -33,6 +33,8 @@

 #include "systemc/tlm_bridge/sc_ext.hh"

+#include 
+
 #include "systemc/ext/utils/sc_report_handler.hh"
 #include "systemc/tlm_bridge/gem5_to_tlm.hh"
 #include "systemc/tlm_bridge/tlm_to_gem5.hh"
@@ -76,6 +78,14 @@
 }

 pkt->qosValue(control_ex->getQos());
+
+if (control_ex->getStreamId().has_value()) {
+ 
pkt->req->setStreamId(control_ex->getStreamId().value());

+}
+if (control_ex->getSubstreamId().has_value()) {
+pkt->req->setSubstreamId(
+control_ex->getSubstreamId().value());
+}
 });
 sc_gem5::addPacketToPayloadConversionStep(
 [] (PacketPtr pkt, tlm::tlm_generic_payload )
@@ -90,6 +100,14 @@
 control_ex->setSecure(pkt->req->isSecure());
 control_ex->setInstruction(pkt->req->isInstFetch());
 control_ex->setQos(pkt->qosValue());
+if (pkt->req->hasStreamId()) {
+control_ex->setStreamId(
+std::make_optional(pkt->req->streamId()));
+}
+if (pkt->req->hasSubstreamId()) {
+control_ex->setSubstreamId(
+std::make_optional(pkt->req->substreamId()));
+}
 });
 }
 };
@@ -263,4 +281,28 @@
 qos = q;
 }

-} // namespace Gem5SystemC
+std::optional
+ControlExtension::getStreamId() const
+{
+return stream_id;
+}
+
+void
+ControlExtension::setStreamId(std::optional s)
+{
+stream_id = s;
+}
+
+std::optional
+ControlExtension::getSubstreamId() const
+{
+return substream_id;
+}
+
+void
+ControlExtension::setSubstreamId(std::optional s)
+{
+substream_id = s;
+}
+
+}  // namespace Gem5SystemC
diff --git a/src/systemc/tlm_bridge/sc_ext.hh  
b/src/systemc/tlm_bridge/sc_ext.hh

index bb67676..790b734 100644
--- a/src/systemc/tlm_bridge/sc_ext.hh
+++ b/src/systemc/tlm_bridge/sc_ext.hh
@@ -36,6 +36,7 @@

 #include 
 #include 
+#include 

 #include "base/amo.hh"
 #include "mem/packet.hh"
@@ -115,6 +116,12 @@
 uint8_t getQos() const;
 void setQos(uint8_t q);

+/* Stream ID and Substream ID */
+std::optional getStreamId() const;
+void setStreamId(std::optional s);
+std::optional getSubstreamId() const;
+void setSubstreamId(std::optional s);
+
   private:
 /* Secure and privileged access */
 bool privileged;
@@ -123,6 +130,10 @@

 /* Quality of Service (AXI4) */
 uint8_t qos;
+
+/* Stream ID and Substream ID */
+std::optional stream_id;
+std::optional substream_id;
 };

 } // namespace Gem5SystemC

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id13d181561ba496c2012f7237eb800f0a9786d05
Gerrit-Change-Number: 65371
Gerrit-PatchSet: 1
Gerrit-Owner: Han-sheng Liu 
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Make the Matched board a package

2022-11-07 Thread Hoa Nguyen (Gerrit) via gem5-dev

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65331?usp=email )


Change subject: stdlib: Make the Matched board a package
..

stdlib: Make the Matched board a package

So that the board and its components can be reused.

Change-Id: Idae1a4493fbb4d826ac8da76532692a985f8025f
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65331
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
---
M src/python/SConscript
A src/python/gem5/prebuilt/riscvmatched/__init__.py
2 files changed, 18 insertions(+), 0 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved




diff --git a/src/python/SConscript b/src/python/SConscript
index 66e9842..e7e464e 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -225,6 +225,8 @@
 PySource('gem5.prebuilt.demo', 'gem5/prebuilt/demo/__init__.py')
 PySource('gem5.prebuilt.demo', 'gem5/prebuilt/demo/x86_demo_board.py')
 PySource('gem5.prebuilt.riscvmatched',
+'gem5/prebuilt/riscvmatched/__init__.py')
+PySource('gem5.prebuilt.riscvmatched',
 'gem5/prebuilt/riscvmatched/riscvmatched_board.py')
 PySource('gem5.prebuilt.riscvmatched',
 'gem5/prebuilt/riscvmatched/riscvmatched_cache.py')
diff --git a/src/python/gem5/prebuilt/riscvmatched/__init__.py  
b/src/python/gem5/prebuilt/riscvmatched/__init__.py

new file mode 100644
index 000..e69de29
--- /dev/null
+++ b/src/python/gem5/prebuilt/riscvmatched/__init__.py

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idae1a4493fbb4d826ac8da76532692a985f8025f
Gerrit-Change-Number: 65331
Gerrit-PatchSet: 2
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: dev-amdgpu: Fix SDMA ring buffer wrap around

2022-11-07 Thread Matthew Poremba (Gerrit) via gem5-dev

Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65351?usp=email )



Change subject: dev-amdgpu: Fix SDMA ring buffer wrap around
..

dev-amdgpu: Fix SDMA ring buffer wrap around

The current SDMA wrap around handling only considers the ring buffer
location as seen by the GPU. Eventually when the end of the SDMA ring
buffer is reached, the driver waits until the rptr written back to the
host catches up to what the driver sees before wrapping around back to
the beginning of the buffer. This writeback currently does not happen at
all, causing hangs for applications with a lot of SDMA commands.

This changeset first fixes the sizes of the queues, especially RLC
queues, so that the wrap around occurs in the correct place. Second, we
now store the rptr writeback address and the absoluate (unwrapped) rptr
value in each SDMA queue. The absolulte rptr is what the driver sends to
the device and what it expects to be written back.

This was tested with an application which basically does a few hundred
thousand hipMemcpy() calls in a loop. It should also fix the issue with
pannotia BC in fullsystem mode.

Change-Id: I53ebdcc6b02fb4eb4da435c9a509544066a97069
---
M src/dev/amdgpu/pm4_packet_processor.cc
M src/dev/amdgpu/sdma_engine.cc
M src/dev/amdgpu/sdma_engine.hh
3 files changed, 73 insertions(+), 15 deletions(-)



diff --git a/src/dev/amdgpu/pm4_packet_processor.cc  
b/src/dev/amdgpu/pm4_packet_processor.cc

index 404beab..4f98f18 100644
--- a/src/dev/amdgpu/pm4_packet_processor.cc
+++ b/src/dev/amdgpu/pm4_packet_processor.cc
@@ -441,12 +441,17 @@
 PM4PacketProcessor::processSDMAMQD(PM4MapQueues *pkt, PM4Queue *q, Addr  
addr,

 SDMAQueueDesc *mqd, uint16_t vmid)
 {
+uint32_t rlc_size = 4UL << bits(mqd->sdmax_rlcx_rb_cntl, 6, 1);
+Addr rptr_wb_addr = mqd->sdmax_rlcx_rb_rptr_addr_hi;
+rptr_wb_addr <<= 32;
+rptr_wb_addr |= mqd->sdmax_rlcx_rb_rptr_addr_lo;
+
 DPRINTF(PM4PacketProcessor, "SDMAMQD: rb base: %#lx rptr: %#x/%#x  
wptr: "

-"%#x/%#x ib: %#x/%#x size: %d ctrl: %#x\n", mqd->rb_base,
-mqd->sdmax_rlcx_rb_rptr, mqd->sdmax_rlcx_rb_rptr_hi,
+"%#x/%#x ib: %#x/%#x size: %d ctrl: %#x rptr wb addr: %#lx\n",
+mqd->rb_base, mqd->sdmax_rlcx_rb_rptr,  
mqd->sdmax_rlcx_rb_rptr_hi,

 mqd->sdmax_rlcx_rb_wptr, mqd->sdmax_rlcx_rb_wptr_hi,
 mqd->sdmax_rlcx_ib_base_lo, mqd->sdmax_rlcx_ib_base_hi,
-mqd->sdmax_rlcx_ib_size, mqd->sdmax_rlcx_rb_cntl);
+rlc_size, mqd->sdmax_rlcx_rb_cntl, rptr_wb_addr);

 // Engine 2 points to SDMA0 while engine 3 points to SDMA1
 assert(pkt->engineSel == 2 || pkt->engineSel == 3);
@@ -454,7 +459,8 @@

 // Register RLC queue with SDMA
 sdma_eng->registerRLCQueue(pkt->doorbellOffset << 2,
-   mqd->rb_base << 8);
+   mqd->rb_base << 8, rlc_size,
+   rptr_wb_addr);

 // Register doorbell with GPU device
 gpuDevice->setSDMAEngine(pkt->doorbellOffset << 2, sdma_eng);
diff --git a/src/dev/amdgpu/sdma_engine.cc b/src/dev/amdgpu/sdma_engine.cc
index e9a4c17..a7c5c12 100644
--- a/src/dev/amdgpu/sdma_engine.cc
+++ b/src/dev/amdgpu/sdma_engine.cc
@@ -161,7 +161,8 @@
 }

 void
-SDMAEngine::registerRLCQueue(Addr doorbell, Addr rb_base)
+SDMAEngine::registerRLCQueue(Addr doorbell, Addr rb_base, uint32_t size,
+ Addr rptr_wb_addr)
 {
 // Get first free RLC
 if (!rlc0.valid()) {
@@ -171,19 +172,19 @@
 rlc0.base(rb_base);
 rlc0.rptr(0);
 rlc0.wptr(0);
+rlc0.rptrWbAddr(rptr_wb_addr);
 rlc0.processing(false);
-// TODO: size - I think pull from MQD 2^rb_cntrl[6:1]-1
-rlc0.size(1024*1024);
+rlc0.size(size);
 } else if (!rlc1.valid()) {
 DPRINTF(SDMAEngine, "Doorbell %lx mapped to RLC1\n", doorbell);
 rlcInfo[1] = doorbell;
 rlc1.valid(true);
 rlc1.base(rb_base);
-rlc1.rptr(1);
-rlc1.wptr(1);
+rlc1.rptr(0);
+rlc1.wptr(0);
+rlc1.rptrWbAddr(rptr_wb_addr);
 rlc1.processing(false);
-// TODO: size - I think pull from MQD 2^rb_cntrl[6:1]-1
-rlc1.size(1024*1024);
+rlc1.size(size);
 } else {
 panic("No free RLCs. Check they are properly unmapped.");
 }
@@ -291,6 +292,17 @@
 { decodeHeader(q, header); });
 dmaReadVirt(q->rptr(), sizeof(uint32_t), cb, >dmaBuffer);
 } else {
+// The driver expects the rptr to be written back to host memory
+// periodically. In simulation, we writeback rptr after each burst  
of

+// packets from a doorbell, rather than using the cycle count which
+// is not accurate in all simulation settings (e.g., KVM).
+DPRINTF(SDMAEngine, "Writing rptr %#lx back to host

[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Make the Matched board a package

2022-11-07 Thread Hoa Nguyen (Gerrit) via gem5-dev

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65331?usp=email )



Change subject: stdlib: Make the Matched board a package
..

stdlib: Make the Matched board a package

So that the board and its components can be reused.

Change-Id: Idae1a4493fbb4d826ac8da76532692a985f8025f
Signed-off-by: Hoa Nguyen 
---
M src/python/SConscript
A src/python/gem5/prebuilt/riscvmatched/__init__.py
2 files changed, 14 insertions(+), 0 deletions(-)



diff --git a/src/python/SConscript b/src/python/SConscript
index 66e9842..e7e464e 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -225,6 +225,8 @@
 PySource('gem5.prebuilt.demo', 'gem5/prebuilt/demo/__init__.py')
 PySource('gem5.prebuilt.demo', 'gem5/prebuilt/demo/x86_demo_board.py')
 PySource('gem5.prebuilt.riscvmatched',
+'gem5/prebuilt/riscvmatched/__init__.py')
+PySource('gem5.prebuilt.riscvmatched',
 'gem5/prebuilt/riscvmatched/riscvmatched_board.py')
 PySource('gem5.prebuilt.riscvmatched',
 'gem5/prebuilt/riscvmatched/riscvmatched_cache.py')
diff --git a/src/python/gem5/prebuilt/riscvmatched/__init__.py  
b/src/python/gem5/prebuilt/riscvmatched/__init__.py

new file mode 100644
index 000..e69de29
--- /dev/null
+++ b/src/python/gem5/prebuilt/riscvmatched/__init__.py

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idae1a4493fbb4d826ac8da76532692a985f8025f
Gerrit-Change-Number: 65331
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
Gerrit-MessageType: newchange
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[gem5-dev] Build failed in Jenkins: nightly #412

2022-11-07 Thread jenkins-no-reply--- via gem5-dev

See 

Changes:


--
[...truncated 462.67 KB...]
 [SO Param] m5.objects.ArmISA, ArmISA -> ALL/python/_m5/param_ArmISA.cc
 [ENUM STR] m5.objects.ArmISA, DecoderFlavor -> ALL/enums/DecoderFlavor.cc
 [ CXX] ALL/arch/arm/ArmMMU.py.cc -> .o
 [SO Param] m5.objects.ArmMMU, ArmTableWalker -> 
ALL/python/_m5/param_ArmTableWalker.cc
 [ CXX] ALL/enums/DecoderFlavor.cc -> .o
 [ CXX] ALL/python/_m5/param_ArmISA.cc -> .o
 [SO Param] m5.objects.ArmMMU, ArmMMU -> ALL/python/_m5/param_ArmMMU.cc
 [ CXX] ALL/python/_m5/param_ArmTableWalker.cc -> .o
 [ CXX] ALL/arch/arm/ArmNativeTrace.py.cc -> .o
 [ CXX] ALL/python/_m5/param_ArmMMU.cc -> .o
 [SO Param] m5.objects.ArmNativeTrace, ArmNativeTrace -> 
ALL/python/_m5/param_ArmNativeTrace.cc
 [ CXX] ALL/arch/arm/ArmSemihosting.py.cc -> .o
 [SO Param] m5.objects.ArmSemihosting, ArmSemihosting -> 
ALL/python/_m5/param_ArmSemihosting.cc
 [ CXX] ALL/python/_m5/param_ArmNativeTrace.cc -> .o
 [ CXX] ALL/arch/arm/ArmSeWorkload.py.cc -> .o
 [ CXX] ALL/python/_m5/param_ArmSemihosting.cc -> .o
 [SO Param] m5.objects.ArmSeWorkload, ArmSEWorkload -> 
ALL/python/_m5/param_ArmSEWorkload.cc
 [SO Param] m5.objects.ArmSeWorkload, ArmEmuLinux -> 
ALL/python/_m5/param_ArmEmuLinux.cc
 [ CXX] ALL/python/_m5/param_ArmSEWorkload.cc -> .o
 [ CXX] ALL/python/_m5/param_ArmEmuLinux.cc -> .o
 [SO Param] m5.objects.ArmSeWorkload, ArmEmuFreebsd -> 
ALL/python/_m5/param_ArmEmuFreebsd.cc
 [ CXX] ALL/arch/arm/ArmSystem.py.cc -> .o
 [SO Param] m5.objects.ArmSystem, ArmSystem -> ALL/python/_m5/param_ArmSystem.cc
 [ CXX] ALL/python/_m5/param_ArmSystem.cc -> .o
 [ CXX] ALL/python/_m5/param_ArmEmuFreebsd.cc -> .o
 [SO Param] m5.objects.ArmSystem, ArmRelease -> 
ALL/python/_m5/param_ArmRelease.cc
 [ CXX] ALL/python/_m5/param_ArmRelease.cc -> .o
 [ENUM STR] m5.objects.ArmSystem, ArmExtension -> ALL/enums/ArmExtension.cc
 [ CXX] ALL/arch/arm/ArmTLB.py.cc -> .o
 [ CXX] ALL/enums/ArmExtension.cc -> .o
 [SO Param] m5.objects.ArmTLB, ArmTLB -> ALL/python/_m5/param_ArmTLB.cc
 [ CXX] ALL/python/_m5/param_ArmTLB.cc -> .o
 [ENUM STR] m5.objects.ArmTLB, ArmLookupLevel -> ALL/enums/ArmLookupLevel.cc
 [ CXX] ALL/arch/arm/ArmPMU.py.cc -> .o
 [SO Param] m5.objects.ArmPMU, ArmPMU -> ALL/python/_m5/param_ArmPMU.cc
 [ CXX] ALL/enums/ArmLookupLevel.cc -> .o
 [ CXX] ALL/python/_m5/param_ArmPMU.cc -> .o
 [ CXX] ALL/arch/arm/ArmCPU.py.cc -> .o
 [ CXX] ALL/debug/Arm.cc -> .o
 [ CXX] ALL/debug/ArmTme.cc -> .o
 [ CXX] ALL/debug/Semihosting.cc -> .o
 [ CXX] ALL/debug/PMUVerbose.cc -> .o
 [ CXX] ALL/arch/arm/generated/decoder.cc -> .o
 [ CXX] ALL/arch/arm/generated/inst-constrs-1.cc -> .o
 [ CXX] ALL/arch/arm/generated/inst-constrs-2.cc -> .o
 [ CXX] ALL/arch/arm/generated/inst-constrs-3.cc -> .o
 [ CXX] ALL/arch/arm/generated/generic_cpu_exec_1.cc -> .o
 [ CXX] ALL/arch/arm/generated/generic_cpu_exec_2.cc -> .o
 [ CXX] ALL/arch/arm/generated/generic_cpu_exec_3.cc -> .o
 [ CXX] ALL/arch/arm/generated/generic_cpu_exec_4.cc -> .o
 [ CXX] ALL/arch/arm/generated/generic_cpu_exec_5.cc -> .o
 [ CXX] ALL/arch/arm/generated/generic_cpu_exec_6.cc -> .o
 [ CXX] ALL/arch/arm/tracers/TarmacTrace.py.cc -> .o
 [SO Param] m5.objects.TarmacTrace, TarmacParser -> 
ALL/python/_m5/param_TarmacParser.cc
 [SO Param] m5.objects.TarmacTrace, TarmacTracer -> 
ALL/python/_m5/param_TarmacTracer.cc
 [ENUM STR] m5.objects.TarmacTrace, TarmacDump -> ALL/enums/TarmacDump.cc
 [SO Param] m5.objects.TarmacTrace, TarmacParser -> ALL/params/TarmacParser.hh
 [ENUMDECL] m5.objects.TarmacTrace, TarmacDump -> ALL/enums/TarmacDump.hh
 [SO Param] m5.objects.TarmacTrace, TarmacTracer -> ALL/params/TarmacTracer.hh
 [ CXX] ALL/arch/arm/tracers/tarmac_base.cc -> .o
 [ CXX] ALL/enums/TarmacDump.cc -> .o
 [ CXX] ALL/python/_m5/param_TarmacTracer.cc -> .o
 [ CXX] ALL/python/_m5/param_TarmacParser.cc -> .o
 [ CXX] ALL/arch/arm/tracers/tarmac_parser.cc -> .o
 [ CXX] ALL/arch/arm/tracers/tarmac_tracer.cc -> .o
 [ CXX] ALL/arch/arm/tracers/tarmac_record.cc -> .o
 [ CXX] ALL/arch/arm/tracers/tarmac_record_v8.cc -> .o
 [ CXX] ALL/arch/arm/gdb-xml/gdb_xml_arm_target.cc -> .o
 [ CXX] ALL/arch/arm/gdb-xml/gdb_xml_arm_core.cc -> .o
 [ CXX] ALL/arch/arm/gdb-xml/gdb_xml_arm_vfpv3.cc -> .o
 [ CXX] ALL/arch/arm/gdb-xml/gdb_xml_aarch64_target.cc -> .o
 [ CXX] ALL/arch/arm/gdb-xml/gdb_xml_aarch64_core.cc -> .o
 [ CXX] ALL/arch/arm/gdb-xml/gdb_xml_aarch64_fpu.cc -> .o
 [ CXX] ALL/arch/generic/htm.cc -> .o
 [ CXX] ALL/arch/generic/mmu.cc -> .o
 [ CXX] ALL/arch/generic/BaseInterrupts.py.cc -> .o
 [SO Param] m5.objects.BaseInterrupts, BaseInterrupts -> 
ALL/python/_m5/param_BaseInterrupts.cc
 [ CXX] ALL/python/_m5/param_BaseInterrupts.cc -> .o
 [ CXX] ALL/arch/generic/BaseISA.py.cc -> .o
 [SO

[gem5-dev] [M] Change in gem5/gem5[develop]: systemc: Add the stream id entry and its conversion in control extension

[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Make the Matched board a package

[gem5-dev] [M] Change in gem5/gem5[develop]: dev-amdgpu: Fix SDMA ring buffer wrap around

[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: Make the Matched board a package

[gem5-dev] Build failed in Jenkins: nightly #412

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