[gem5-dev] Build failed in Jenkins: nightly #426

2022-11-18 Thread jenkins-no-reply--- via gem5-dev 
See 

Changes:

[quentin.forcioli] base: query now works the same way normal command worked

[matthew.poremba] dev-amdgpu: Store SDMA queue type, use for ring ID

[Bobby R. Bruce] arch-arm: Revert 'Setup TC/ISA at construction time..'


--
[...truncated 325.88 KB...]
Starting Test Suite: realview-simple-atomic-ALL-x86_64-opt 
Logging call to command: /nobackup/jenkins/workspace/nightly/build/ALL/gem5.opt 
-d /tmp/gem5outl1ubnprb -re --silent-redirect 
/nobackup/jenkins/workspace/nightly/tests/gem5/fs/linux/arm/run.py 
/nobackup/jenkins/workspace/nightly/tests/gem5/configs/realview64-minor-dual.py 
/nobackup/jenkins/workspace/nightly/tests/gem5/resources/arm 
/nobackup/jenkins/workspace/nightly
Logging call to command: /nobackup/jenkins/workspace/nightly/build/ALL/gem5.opt 
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/nobackup/jenkins/workspace/nightly/tests/gem5/fs/linux/arm/run.py 
/nobackup/jenkins/workspace/nightly/tests/gem5/configs/realview-switcheroo-timing.py
 /nobackup/jenkins/workspace/nightly/tests/gem5/resources/arm 
/nobackup/jenkins/workspace/nightly
Starting Test Case: realview-simple-atomic-ALL-x86_64-opt
Starting Test Suite: realview-simple-timing-ALL-x86_64-opt 
Starting Test Case: realview-simple-timing-ALL-x86_64-opt
Starting Test Suite: realview-minor-ALL-x86_64-opt 
Starting Test Case: realview-minor-ALL-x86_64-opt
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Starting Test Case: realview-switcheroo-o3-ALL-x86_64-opt
Starting Test Suite: realview64-o3-dual-ALL-x86_64-opt 
Starting Test Case: realview64-o3-dual-ALL-x86_64-opt
Starting Test Suite: realview64-minor-dual-ALL-x86_64-opt 
Starting Test Case: realview64-minor-dual-ALL-x86_64-opt
Starting Test Suite: realview-switcheroo-timing-ALL-x86_64-opt 
Starting Test Case: realview-switcheroo-timing-ALL-x86_64-opt
Test: realview-switcheroo-timing-ALL-x86_64-opt Passed
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/nobackup/jenkins/workspace/nightly/tests/gem5/fs/linux/arm/run.py 
/nobackup/jenkins/workspace/nightly/tests/gem5/configs/realview-o3.py 
/nobackup/jenkins/workspace/nightly/tests/gem5/resources/arm 
/nobackup/jenkins/workspace/nightly
Starting Test Suite: realview-o3-ALL-x86_64-opt 
Starting Test Case: realview-o3-ALL-x86_64-opt
Test: realview-simple-atomic-ALL-x86_64-opt Passed
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 /nobackup/jenkins/workspace/nightly/tests/gem5/resources/arm 
/nobackup/jenkins/workspace/nightly
Starting Test Suite: realview-simple-atomic-checkpoint-ALL-x86_64-opt 
Starting Test Case: realview-simple-atomic-checkpoint-ALL-x86_64-opt
Test: realview-simple-timing-ALL-x86_64-opt Passed
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/nobackup/jenkins/workspace/nightly/tests/gem5/fs/linux/arm/run.py 
/nobackup/jenkins/workspace/nightly/tests/gem5/configs/realview-switcheroo-atomic.py
 /nobackup/jenkins/workspace/nightly/tests/gem5/resources/arm 
/nobackup/jenkins/workspace/nightly
Starting Test Suite: realview-switcheroo-atomic-ALL-x86_64-opt 
Starting Test Case: realview-switcheroo-atomic-ALL-x86_64-opt
Test: realview64-minor-dual-ALL-x86_64-opt Passed
Test: realview64-minor-dual-ALL-x86_64-opt-MatchFileRegex Passed
Starting Test Case: realview64-minor-dual-ALL-x86_64-opt-MatchFileRegex
Logging call to command: /nobackup/jenkins/workspace/nightly/build/ALL/gem5.opt 
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 /nobackup/jenkins/workspace/nightly/tests/gem5/resources/arm 
/nobackup/jenkins/workspace/nightly
Starting Test Suite: realview64-switcheroo-o3-ALL-x86_64-opt 
Starting Test Case: realview64-switcheroo-o3-ALL-x86_64-opt
Test: realview-switcheroo-atomic-ALL-x86_64-opt Passed
Logging call to command: /nobackup/jenkins/workspace/nightly/build/ALL/gem5.opt 
-d /tmp/gem5outrj7dpxn6 -re --silent-redirect 
/nobackup/jenkins/workspace/nightly/tests/gem5/fs/linux/arm/run.py 
/nobackup/jenkins/workspace/nightly/tests/gem5/configs/realview64-switcheroo-full.py
 /nobackup/jenkins/workspace/nightly/tests/gem5/resources/arm 
/nobackup/jenkins/workspace/nightly
Starting Test Suite: realview64-switcheroo-full-ALL-x86_64-opt 
Starting Test Case: realview64-switcheroo-full-ALL-x86_64-opt
Test: realview64-o3-ALL-x86_64-opt Passed
Logging call

[gem5-dev] [M] Change in gem5/gem5[develop]: dev-amdgpu: Writeback RLC queue MQD when unmapped

2022-11-18 Thread Matthew Poremba (Gerrit) via gem5-dev 
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65791?usp=email )



Change subject: dev-amdgpu: Writeback RLC queue MQD when unmapped
..

dev-amdgpu: Writeback RLC queue MQD when unmapped

Currently when RLC queues (user mode queues) are mapped, the read/write
pointers of the ring buffer are set to zero. However, these queues could
be unmapped and then remapped later. In that situation the read/write
pointers should be the previous value before unmapping occurred. Since
the read pointer gets reset to zero, the queue begins reading from the
start of the ring, which usually contains older packets. There is a 99%
chance those packets contain addresses which are no longer in the page
tables which will cause a page fault.

To fix this we update the MQD with the current read/write pointer values
and then writeback the MQD to memory when the queue is unmapped. This
requires adding a pointer to the MQD and the host address of the MQD
where it should be written back to. The interface for registering RLC
queue is also simplified. Since we need to pass the MQD anyway, we can
get values from it as well.

Fixes b+tree and streamcluster from rodinia (when using RLC queues).

Change-Id: Ie5dad4d7d90ea240c3e9f0cddf3e844a3cd34c4f
---
M src/dev/amdgpu/pm4_packet_processor.cc
M src/dev/amdgpu/pm4_queues.hh
M src/dev/amdgpu/sdma_engine.cc
M src/dev/amdgpu/sdma_engine.hh
4 files changed, 106 insertions(+), 19 deletions(-)



diff --git a/src/dev/amdgpu/pm4_packet_processor.cc  
b/src/dev/amdgpu/pm4_packet_processor.cc

index f78f833..152fd4d 100644
--- a/src/dev/amdgpu/pm4_packet_processor.cc
+++ b/src/dev/amdgpu/pm4_packet_processor.cc
@@ -458,9 +458,7 @@
 SDMAEngine *sdma_eng = gpuDevice->getSDMAById(pkt->engineSel - 2);

 // Register RLC queue with SDMA
-sdma_eng->registerRLCQueue(pkt->doorbellOffset << 2,
-   mqd->rb_base << 8, rlc_size,
-   rptr_wb_addr);
+sdma_eng->registerRLCQueue(pkt->doorbellOffset << 2, addr, mqd);

 // Register doorbell with GPU device
 gpuDevice->setSDMAEngine(pkt->doorbellOffset << 2, sdma_eng);
diff --git a/src/dev/amdgpu/pm4_queues.hh b/src/dev/amdgpu/pm4_queues.hh
index 8b6626d..ddadd65 100644
--- a/src/dev/amdgpu/pm4_queues.hh
+++ b/src/dev/amdgpu/pm4_queues.hh
@@ -33,6 +33,8 @@
 #ifndef __DEV_AMDGPU_PM4_QUEUES_HH__
 #define __DEV_AMDGPU_PM4_QUEUES_HH__

+#include "dev/amdgpu/pm4_defines.hh"
+
 namespace gem5
 {

@@ -201,10 +203,24 @@
 };
 uint64_t rb_base;
 };
-uint32_t sdmax_rlcx_rb_rptr;
-uint32_t sdmax_rlcx_rb_rptr_hi;
-uint32_t sdmax_rlcx_rb_wptr;
-uint32_t sdmax_rlcx_rb_wptr_hi;
+union
+{
+struct
+{
+uint32_t sdmax_rlcx_rb_rptr;
+uint32_t sdmax_rlcx_rb_rptr_hi;
+};
+uint64_t rptr;
+};
+union
+{
+struct
+{
+uint32_t sdmax_rlcx_rb_wptr;
+uint32_t sdmax_rlcx_rb_wptr_hi;
+};
+uint64_t wptr;
+};
 uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
 uint32_t sdmax_rlcx_rb_rptr_addr_hi;
 uint32_t sdmax_rlcx_rb_rptr_addr_lo;
diff --git a/src/dev/amdgpu/sdma_engine.cc b/src/dev/amdgpu/sdma_engine.cc
index 02203c8..4c03bf5 100644
--- a/src/dev/amdgpu/sdma_engine.cc
+++ b/src/dev/amdgpu/sdma_engine.cc
@@ -165,30 +165,40 @@
 }

 void
-SDMAEngine::registerRLCQueue(Addr doorbell, Addr rb_base, uint32_t size,
- Addr rptr_wb_addr)
+SDMAEngine::registerRLCQueue(Addr doorbell, Addr mqdAddr, SDMAQueueDesc  
*mqd)

 {
+uint32_t rlc_size = 4UL << bits(mqd->sdmax_rlcx_rb_cntl, 6, 1);
+Addr rptr_wb_addr = mqd->sdmax_rlcx_rb_rptr_addr_hi;
+rptr_wb_addr <<= 32;
+rptr_wb_addr |= mqd->sdmax_rlcx_rb_rptr_addr_lo;
+
 // Get first free RLC
 if (!rlc0.valid()) {
 DPRINTF(SDMAEngine, "Doorbell %lx mapped to RLC0\n", doorbell);
 rlcInfo[0] = doorbell;
 rlc0.valid(true);
-rlc0.base(rb_base);
+rlc0.base(mqd->rb_base << 8);
+rlc0.size(rlc_size);
 rlc0.rptr(0);
-rlc0.wptr(0);
+rlc0.incRptr(mqd->rptr);
+rlc0.setWptr(mqd->wptr);
 rlc0.rptrWbAddr(rptr_wb_addr);
 rlc0.processing(false);
-rlc0.size(size);
+rlc0.setMQD(mqd);
+rlc0.setMQDAddr(mqdAddr);
 } else if (!rlc1.valid()) {
 DPRINTF(SDMAEngine, "Doorbell %lx mapped to RLC1\n", doorbell);
 rlcInfo[1] = doorbell;
 rlc1.valid(true);
-rlc1.base(rb_base);
+rlc1.base(mqd->rb_base << 8);
+rlc1.size(rlc_size);
 rlc1.rptr(0);
-rlc1.wptr(0);
+rlc1.incRptr(mqd->rptr);
+rlc1.setWptr(mqd->wptr);
 rlc1.rptrWbAddr(rptr_wb_addr);
 rlc1.processing(false);
-rlc1.size(size);
+rlc1.setMQD(mqd);
+rlc1.setMQDAddr(mqdAddr);
 }

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Revert 'Setup TC/ISA at construction time..'

2022-11-18 Thread Bobby Bruce (Gerrit) via gem5-dev 
Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65732?usp=email )


Change subject: arch-arm: Revert 'Setup TC/ISA at construction time..'
..

arch-arm: Revert 'Setup TC/ISA at construction time..'

Reverts:

dd2f1fb2f8520849f10fc25fc5eab5beaa90a7d4
https://gem5-review.googlesource.com/c/public/gem5/+/65174

and

47bd56ee71ba1d684138365e7123aa779989ba1d
https://gem5-review.googlesource.com/c/public/gem5/+/65291

The 47bd56ee change resulted in the
`SuiteUID:tests/gem5/fs/linux/arm/test.py:realview-switcheroo-noncaching-timing-ALL-x86_64-opt`
nightly test stalling. This behavior can be reproduced with:

```
./build/ALL/gem5.opt tests/gem5/fs/linux/arm/run.py  
tests/gem5/configs/realview-switcheroo-noncaching-timing.py  
tests/gem5/resources/arm “$(pwd)”

```

The subsequent change, dd2f1fb2, must be reverted for this change to be
reverted.

Change-Id: I6fed74f33d013f321b93cf1a73eee404cb87ce18
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65732
Reviewed-by: Jason Lowe-Power 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M src/arch/arm/isa.cc
M src/dev/arm/gic_v3.cc
M src/dev/arm/gic_v3_cpu_interface.cc
M src/dev/arm/gic_v3_cpu_interface.hh
4 files changed, 62 insertions(+), 20 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass
  Bobby Bruce: Looks good to me, approved




diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index fd19f72..a30fd94 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -523,6 +523,16 @@
 return;

 selfDebug->init(tc);
+
+Gicv3 *gicv3 = dynamic_cast(system->getGIC());
+if (!gicv3)
+return;
+
+if (!gicv3CpuInterface)
+gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
+
+gicv3CpuInterface->setISA(this);
+gicv3CpuInterface->setThreadContext(tc);
 }

 void
@@ -1998,15 +2008,7 @@
 BaseISADevice &
 ISA::getGICv3CPUInterface()
 {
-if (gicv3CpuInterface)
-return *gicv3CpuInterface.get();
-
-assert(system);
-Gicv3 *gicv3 = dynamic_cast(system->getGIC());
-panic_if(!gicv3, "The system does not have a GICv3 irq controller\n");
-
-gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
-
+panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
 return *gicv3CpuInterface.get();
 }

diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc
index e14d1f2..dde3818 100644
--- a/src/dev/arm/gic_v3.cc
+++ b/src/dev/arm/gic_v3.cc
@@ -147,7 +147,7 @@

 for (int i = 0; i < threads; i++) {
 redistributors[i] = new Gicv3Redistributor(this, i);
-cpuInterfaces[i] = new Gicv3CPUInterface(this, sys->threads[i]);
+cpuInterfaces[i] = new Gicv3CPUInterface(this, i);
 }

 distRange = RangeSize(params().dist_addr,
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc  
b/src/dev/arm/gic_v3_cpu_interface.cc

index a11dd9b..0e1dbaa 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -55,19 +55,15 @@
 const uint8_t Gicv3CPUInterface::GIC_MIN_BPR;
 const uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS;

-Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, ThreadContext *_tc)
+Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
 : BaseISADevice(),
   gic(gic),
   redistributor(nullptr),
   distributor(nullptr),
-  tc(_tc),
-  maintenanceInterrupt(gic->params().maint_int->get(tc)),
-  cpuId(tc->contextId())
+  cpuId(cpu_id)
 {
 hppi.prio = 0xff;
 hppi.intid = Gicv3::INTID_SPURIOUS;
-
-setISA(static_cast(tc->getIsaPtr()));
 }

 void
@@ -84,6 +80,15 @@
 hppi.prio = 0xff;
 }

+void
+Gicv3CPUInterface::setThreadContext(ThreadContext *_tc)
+{
+tc = _tc;
+maintenanceInterrupt = gic->params().maint_int->get(tc);
+fatal_if(maintenanceInterrupt->num() >=  
redistributor->irqPending.size(),

+"Invalid maintenance interrupt number\n");
+}
+
 bool
 Gicv3CPUInterface::getHCREL2FMO() const
 {
diff --git a/src/dev/arm/gic_v3_cpu_interface.hh  
b/src/dev/arm/gic_v3_cpu_interface.hh

index c39fab7..e860373 100644
--- a/src/dev/arm/gic_v3_cpu_interface.hh
+++ b/src/dev/arm/gic_v3_cpu_interface.hh
@@ -68,11 +68,11 @@
 Gicv3 * gic;
 Gicv3Redistributor * redistributor;
 Gicv3Distributor * distributor;
-
-ThreadContext *tc;
-ArmInterruptPin *maintenanceInterrupt;
 uint32_t cpuId;

+ArmInterruptPin *maintenanceInterrupt;
+ThreadContext *tc;
+
 BitUnion64(ICC_CTLR_EL1)
 Bitfield<63, 20> res0_3;
 Bitfield<19> ExtRange;
@@ -359,7 +359,7 @@
 void setBankedMiscReg(ArmISA::MiscRegIndex misc_reg, RegVal val) const;
   public:

-Gicv3CPUInterface(Gicv3 * gic, ThreadContext *tc);
+Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id);

 void init();

@@ -369,6 +369,7 @@
   public: // BaseISADevice
 RegVal

[gem5-dev] [S] Change in gem5/gem5[develop]: dev-amdgpu: Store SDMA queue type, use for ring ID

2022-11-18 Thread Matthew Poremba (Gerrit) via gem5-dev 
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65691?usp=email )


Change subject: dev-amdgpu: Store SDMA queue type, use for ring ID
..

dev-amdgpu: Store SDMA queue type, use for ring ID

Currently the SDMA queue type is guessed in the trap method by looking
at which queue in the engine is processing packets. It is possible for
both queues to be processing (e.g., one queue sent a DMA and is waiting
then switch to another queue), triggering an assert.

Instead store the queue type in the queue itself and use that type in
trap to determine which ring ID to use for the interrupt packet.

Change-Id: If91c458e60a03f2013c0dc42bab0b1673e3dbd84
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65691
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/dev/amdgpu/sdma_engine.cc
M src/dev/amdgpu/sdma_engine.hh
2 files changed, 30 insertions(+), 6 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/amdgpu/sdma_engine.cc b/src/dev/amdgpu/sdma_engine.cc
index 59c5027..02203c8 100644
--- a/src/dev/amdgpu/sdma_engine.cc
+++ b/src/dev/amdgpu/sdma_engine.cc
@@ -55,11 +55,15 @@
 gfxIb.parent();
 gfx.valid(true);
 gfxIb.valid(true);
+gfx.queueType(SDMAGfx);
+gfxIb.queueType(SDMAGfx);

 page.ib();
 pageIb.parent();
 page.valid(true);
 pageIb.valid(true);
+page.queueType(SDMAPage);
+pageIb.queueType(SDMAPage);

 rlc0.ib();
 rlc0Ib.parent();
@@ -727,11 +731,7 @@

 DPRINTF(SDMAEngine, "Trap contextId: %p\n", pkt->intrContext);

-uint32_t ring_id = 0;
-assert(page.processing() ^ gfx.processing());
-if (page.processing()) {
-ring_id = 3;
-}
+uint32_t ring_id = (q->queueType() == SDMAPage) ? 3 : 0;

 gpuDevice->getIH()->prepareInterruptCookie(pkt->intrContext, ring_id,
getIHClientId(), TRAP_ID);
diff --git a/src/dev/amdgpu/sdma_engine.hh b/src/dev/amdgpu/sdma_engine.hh
index d0afaf7..0bfee12 100644
--- a/src/dev/amdgpu/sdma_engine.hh
+++ b/src/dev/amdgpu/sdma_engine.hh
@@ -64,9 +64,10 @@
 bool _processing;
 SDMAQueue *_parent;
 SDMAQueue *_ib;
+SDMAType _type;
   public:
 SDMAQueue() : _rptr(0), _wptr(0), _valid(false),  
_processing(false),

-_parent(nullptr), _ib(nullptr) {}
+_parent(nullptr), _ib(nullptr), _type(SDMAGfx) {}

 Addr base() { return _base; }
 Addr rptr() { return _base + _rptr; }
@@ -80,6 +81,7 @@
 bool processing() { return _processing; }
 SDMAQueue* parent() { return _parent; }
 SDMAQueue* ib() { return _ib; }
+SDMAType queueType() { return _type; }

 void base(Addr value) { _base = value; }

@@ -111,6 +113,7 @@
 void processing(bool value) { _processing = value; }
 void parent(SDMAQueue* q) { _parent = q; }
 void ib(SDMAQueue* ib) { _ib = ib; }
+void queueType(SDMAType type) { _type = type; }
 };

 /* SDMA Engine ID */

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/65691?usp=email
To unsubscribe, or for help writing mail filters, visit  
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If91c458e60a03f2013c0dc42bab0b1673e3dbd84
Gerrit-Change-Number: 65691
Gerrit-PatchSet: 2
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Build failed in Jenkins: nightly #425

2022-11-18 Thread jenkins-no-reply--- via gem5-dev 
See 

Changes:


--
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/nobackup/jenkins/workspace/nightly/build/NULL/gem5.build/variables
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[gem5-dev] Build failed in Jenkins: compiler-checks #426

2022-11-18 Thread jenkins-no-reply--- via gem5-dev 
See 

Changes:


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[gem5-dev] [M] Change in gem5/gem5[develop]: base: query now works the same way normal command worked

2022-11-18 Thread Quentin Forcioli (Gerrit) via gem5-dev 
Quentin Forcioli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/63537?usp=email )


 (

9 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: base: query now works the same way normal command worked
..

base: query now works the same way normal command worked

Query can now return true or false like normal command, to interrupt
execution, it might be needed if a query need to wait for another event.

Change-Id: Ic463287ecd88e6b63a53f2cb9a46c83d3419618c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63537
Reviewed-by: Bobby Bruce 
Tested-by: kokoro 
Maintainer: Bobby Bruce 
---
M src/base/remote_gdb.cc
M src/base/remote_gdb.hh
2 files changed, 41 insertions(+), 20 deletions(-)

Approvals:
  kokoro: Regressions pass
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved




diff --git a/src/base/remote_gdb.cc b/src/base/remote_gdb.cc
index da3f113..c19dede 100644
--- a/src/base/remote_gdb.cc
+++ b/src/base/remote_gdb.cc
@@ -1333,13 +1333,14 @@
 { "sThreadInfo", { ::querySThreadInfo } },
 };

-void
+bool
 BaseRemoteGDB::queryC(QuerySetCommand::Context )
 {
 send("QC%x", encodeThreadId(tc->contextId()));
+return true;
 }

-void
+bool
 BaseRemoteGDB::querySupported(QuerySetCommand::Context )
 {
 std::ostringstream oss;
@@ -1350,9 +1351,10 @@
 for (const auto& feature : availableFeatures())
 oss << ';' << feature;
 send(oss.str());
+return true;
 }

-void
+bool
 BaseRemoteGDB::queryXfer(QuerySetCommand::Context )
 {
 auto split = splitAt(ctx.args.at(0), ":");
@@ -1391,15 +1393,16 @@
 std::string encoded;
 encodeXferResponse(content, encoded, offset, length);
 send(encoded);
+return true;
 }
-void
+bool
 BaseRemoteGDB::querySymbol(QuerySetCommand::Context )
 {
 //The target does not need to look up any (more) symbols.
 send("OK");
+return true;
 }
-
-void
+bool
 BaseRemoteGDB::queryAttached(QuerySetCommand::Context )
 {
 std::string pid="";
@@ -1409,17 +1412,19 @@
 DPRINTF(GDBMisc, "QAttached : pid=%s\n",pid);
 //The remote server is attached to an existing process.
 send("1");
+return true;
 }


-void
+bool
 BaseRemoteGDB::queryFThreadInfo(QuerySetCommand::Context )
 {
 threadInfoIdx = 0;
 querySThreadInfo(ctx);
+return true;
 }

-void
+bool
 BaseRemoteGDB::querySThreadInfo(QuerySetCommand::Context )
 {
 if (threadInfoIdx >= threads.size()) {
@@ -1430,6 +1435,7 @@
 std::advance(it, threadInfoIdx++);
 send("m%x", encodeThreadId(it->second->contextId()));
 }
+return true;
 }

 bool
@@ -1461,10 +1467,9 @@
 remaining = std::move(arg_split.second);
 }
 }
-
-(this->*(query.func))(qctx);
-
-return true;
+//returning true if the query want to pursue GDB command processing
+//false means that the command processing stop until it's trigger  
again.

+return (this->*(query.func))(qctx);
 }

 std::vector
diff --git a/src/base/remote_gdb.hh b/src/base/remote_gdb.hh
index ad64bc7..4da1dcc 100644
--- a/src/base/remote_gdb.hh
+++ b/src/base/remote_gdb.hh
@@ -416,7 +416,7 @@
 Context(const std::string &_name) : name(_name) {}
 };

-using Func = void (BaseRemoteGDB::*)(Context );
+using Func = bool (BaseRemoteGDB::*)(Context );

 const char * const argSep;
 const Func func;
@@ -428,15 +428,15 @@

 static std::map queryMap;

-void queryC(QuerySetCommand::Context );
-void querySupported(QuerySetCommand::Context );
-void queryXfer(QuerySetCommand::Context );
-void querySymbol(QuerySetCommand::Context );
-void queryAttached(QuerySetCommand::Context );
+bool queryC(QuerySetCommand::Context );
+bool querySupported(QuerySetCommand::Context );
+bool queryXfer(QuerySetCommand::Context );
+bool querySymbol(QuerySetCommand::Context );
+bool queryAttached(QuerySetCommand::Context );

 size_t threadInfoIdx = 0;
-void queryFThreadInfo(QuerySetCommand::Context );
-void querySThreadInfo(QuerySetCommand::Context );
+bool queryFThreadInfo(QuerySetCommand::Context );
+bool querySThreadInfo(QuerySetCommand::Context );

   protected:
 ThreadContext *context() { return tc; }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic463287ecd88e6b63a53f2cb9a46c83d3419618c
Gerrit-Change-Number: 63537
Gerrit-PatchSet: 12
Gerrit-Owner: Quentin Forcioli 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Quentin Forcioli 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged

[gem5-dev] [M] Change in gem5/gem5[develop]: mem: Add an API for requesting a back door without a Packet/Request.

2022-11-18 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65752?usp=email )



Change subject: mem: Add an API for requesting a back door without a  
Packet/Request.

..

mem: Add an API for requesting a back door without a Packet/Request.

Make this part of the Functional protocol, since it should always
return immediately, can be shared by the atomic and timing protocols,
and thematically fits with that protocol.

The default implementation on the receiving end just ignores the
request and leaves the back door pointer set to null, effectively
making back doors default "off" which matches their behavior in the
atomic protocol.

This mechamism helps fix a bug in the TLM gem5 bridges which need to
translate to/from the DMI and back door mechanisms, where there can be
an explicit request for a back door which does not have a transaction
associated with it. It is also necessary for bridging DMI requests in
timing mode, since the DMI requests must be instant, and the timing
protocol does not send/receive packets instantly.

Change-Id: I905f13b9bc83c3fa7877b05ce932e17c308125e2
---
M src/mem/port.cc
M src/mem/port.hh
M src/mem/protocol/functional.cc
M src/mem/protocol/functional.hh
4 files changed, 99 insertions(+), 0 deletions(-)



diff --git a/src/mem/port.cc b/src/mem/port.cc
index 00f7ce6..18793d4 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -102,6 +102,11 @@

 // Functional protocol.
 void recvFunctional(PacketPtr) override { blowUp(); }
+void
+recvMemBackdoorReq(const MemBackdoorReq &, MemBackdoorPtr &) override
+{
+blowUp();
+}

 // General.
 AddrRangeList getAddrRanges() const override { return AddrRangeList();  
}

@@ -205,4 +210,15 @@
 return recvAtomic(pkt);
 }

+void
+ResponsePort::recvMemBackdoorReq(const MemBackdoorReq ,
+MemBackdoorPtr )
+{
+if (!defaultBackdoorWarned) {
+DPRINTF(ResponsePort,
+"Port %s doesn't support requesting a back door.", name());
+defaultBackdoorWarned = true;
+}
+}
+
 } // namespace gem5
diff --git a/src/mem/port.hh b/src/mem/port.hh
index 33ff117..fb0f4b8 100644
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -161,6 +161,21 @@
  */
 void sendFunctional(PacketPtr pkt) const;

+/**
+ * Send a request for a back door to a range of memory.
+ *
+ * @param req An object which describes what back door is being  
requested.
+ * @param backdoor Can be set to a back door pointer by the target to  
let
+ *caller have direct access to the requested range. The  
original
+ *caller should initialize this pointer to nullptr. If a  
receiver

+ *does not want to provide a back door, they should leave this
+ *value. If an intermediary wants to support a back door  
across it,
+ *it should pass this pointer through, or if not, return  
without

+ *passing the request further downstream.
+ */
+void sendMemBackdoorReq(const MemBackdoorReq ,
+MemBackdoorPtr );
+
   public:
 /* The timing protocol. */

@@ -438,6 +453,8 @@
  * Default implementations.
  */
 Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr )  
override;

+void recvMemBackdoorReq(const MemBackdoorReq ,
+MemBackdoorPtr ) override;

 bool
 tryTiming(PacketPtr pkt) override
@@ -491,6 +508,18 @@
 }
 }

+inline void
+RequestPort::sendMemBackdoorReq(const MemBackdoorReq ,
+MemBackdoorPtr )
+{
+try {
+return FunctionalRequestProtocol::sendMemBackdoorReq(
+_responsePort, req, backdoor);
+} catch (UnboundPortException) {
+reportUnbound();
+}
+}
+
 inline bool
 RequestPort::sendTimingReq(PacketPtr pkt)
 {
diff --git a/src/mem/protocol/functional.cc b/src/mem/protocol/functional.cc
index 0f54d92..29cec23 100644
--- a/src/mem/protocol/functional.cc
+++ b/src/mem/protocol/functional.cc
@@ -53,6 +53,14 @@
 return peer->recvFunctional(pkt);
 }

+void
+FunctionalRequestProtocol::sendMemBackdoorReq(
+FunctionalResponseProtocol *peer,
+const MemBackdoorReq , MemBackdoorPtr )
+{
+return peer->recvMemBackdoorReq(req, backdoor);
+}
+
 /* The response protocol. */

 void
diff --git a/src/mem/protocol/functional.hh b/src/mem/protocol/functional.hh
index 27db171..4f330b4 100644
--- a/src/mem/protocol/functional.hh
+++ b/src/mem/protocol/functional.hh
@@ -41,6 +41,7 @@
 #ifndef __MEM_GEM5_PROTOCOL_FUNCTIONAL_HH__
 #define __MEM_GEM5_PROTOCOL_FUNCTIONAL_HH__

+#include "mem/backdoor.hh"
 #include "mem/packet.hh"

 namespace gem5
@@ -66,6 +67,16 @@
  * Receive a functional snoop request packet from the peer.
  */
 virtual void recvFunctionalSnoop(PacketPtr pkt) = 0;
+
+/**
+ * Send a request for a back door to a range of memory.
+ *
+ * @param req An object which describes

[gem5-dev] [S] Change in gem5/gem5[develop]: mem: Add a class to describe a back door request.

2022-11-18 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65751?usp=email )



Change subject: mem: Add a class to describe a back door request.
..

mem: Add a class to describe a back door request.

In cases where a back door is not being requested alongside a packet
or request, there needs to be a structure which describes the address
range to use, and what type of access the back door should support. It
would be possible to make a Packet/Request to carry that information,
but those types are actually pretty big, and have a lot of extra
overhead which would be overkill for this purpose.

Change-Id: I3638361ffa758ee959cb3bc57f7c35f2aa34a36c
---
M src/mem/backdoor.hh
1 file changed, 35 insertions(+), 0 deletions(-)



diff --git a/src/mem/backdoor.hh b/src/mem/backdoor.hh
index 73e6670..54fe4ac 100644
--- a/src/mem/backdoor.hh
+++ b/src/mem/backdoor.hh
@@ -126,6 +126,25 @@

 typedef MemBackdoor *MemBackdoorPtr;

+class MemBackdoorReq
+{
+  private:
+AddrRange _range;
+MemBackdoor::Flags _flags;
+
+  public:
+MemBackdoorReq(AddrRange r, MemBackdoor::Flags new_flags) :
+_range(r), _flags(new_flags)
+{}
+
+const AddrRange () const { return _range; }
+
+bool readable() const { return _flags & MemBackdoor::Readable; }
+bool writeable() const { return _flags & MemBackdoor::Writeable; }
+
+MemBackdoor::Flags flags() const { return _flags; }
+};
+
 } // namespace gem5

 #endif  //__MEM_BACKDOOR_HH__

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3638361ffa758ee959cb3bc57f7c35f2aa34a36c
Gerrit-Change-Number: 65751
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-CC: Gabe Black 
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: dev,mem,systemc: Implement and use the recvMemBackdoorReq func.

2022-11-18 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65753?usp=email )



Change subject: dev,mem,systemc: Implement and use the recvMemBackdoorReq  
func.

..

dev,mem,systemc: Implement and use the recvMemBackdoorReq func.

Change-Id: If6e12d4fcef0c31131a9768099a72542a8f62ab1
---
M src/mem/cfi_mem.cc
M src/mem/cfi_mem.hh
M src/mem/coherent_xbar.cc
M src/mem/coherent_xbar.hh
M src/mem/mem_ctrl.cc
M src/mem/mem_ctrl.hh
M src/mem/noncoherent_xbar.cc
M src/mem/noncoherent_xbar.hh
M src/mem/simple_mem.cc
M src/mem/simple_mem.hh
M src/mem/sys_bridge.hh
M src/systemc/tlm_bridge/gem5_to_tlm.cc
M src/systemc/tlm_bridge/gem5_to_tlm.hh
M src/systemc/tlm_bridge/tlm_to_gem5.cc
14 files changed, 165 insertions(+), 16 deletions(-)



diff --git a/src/mem/cfi_mem.cc b/src/mem/cfi_mem.cc
index 70dc43f..f8c1084 100644
--- a/src/mem/cfi_mem.cc
+++ b/src/mem/cfi_mem.cc
@@ -275,6 +275,14 @@
 pkt->popLabel();
 }

+void
+CfiMemory::recvMemBackdoorReq(const MemBackdoorReq ,
+MemBackdoorPtr &_backdoor)
+{
+if (backdoor.ptr())
+_backdoor = 
+}
+
 bool
 CfiMemory::recvTimingReq(PacketPtr pkt)
 {
@@ -486,6 +494,13 @@
 mem.recvFunctional(pkt);
 }

+void
+CfiMemory::MemoryPort::recvMemBackdoorReq(const MemBackdoorReq ,
+MemBackdoorPtr &_backdoor)
+{
+mem.recvMemBackdoorReq(req, _backdoor);
+}
+
 bool
 CfiMemory::MemoryPort::recvTimingReq(PacketPtr pkt)
 {
diff --git a/src/mem/cfi_mem.hh b/src/mem/cfi_mem.hh
index 5a7a1c5..4a02267 100644
--- a/src/mem/cfi_mem.hh
+++ b/src/mem/cfi_mem.hh
@@ -248,6 +248,8 @@
 Tick recvAtomicBackdoor(
 PacketPtr pkt, MemBackdoorPtr &_backdoor) override;
 void recvFunctional(PacketPtr pkt) override;
+void recvMemBackdoorReq(const MemBackdoorReq ,
+MemBackdoorPtr &_backdoor) override;
 bool recvTimingReq(PacketPtr pkt) override;
 void recvRespRetry() override;
 AddrRangeList getAddrRanges() const override;
@@ -361,6 +363,8 @@
 Tick recvAtomic(PacketPtr pkt);
 Tick recvAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr &_backdoor);
 void recvFunctional(PacketPtr pkt);
+void recvMemBackdoorReq(const MemBackdoorReq ,
+MemBackdoorPtr &_backdoor);
 bool recvTimingReq(PacketPtr pkt);
 void recvRespRetry();

diff --git a/src/mem/coherent_xbar.cc b/src/mem/coherent_xbar.cc
index 7d1cd5d..8163299 100644
--- a/src/mem/coherent_xbar.cc
+++ b/src/mem/coherent_xbar.cc
@@ -998,6 +998,14 @@
 }

 void
+CoherentXBar::recvMemBackdoorReq(const MemBackdoorReq ,
+MemBackdoorPtr )
+{
+PortID dest_id = findPort(req.range());
+memSidePorts[dest_id]->sendMemBackdoorReq(req, backdoor);
+}
+
+void
 CoherentXBar::recvFunctional(PacketPtr pkt, PortID cpu_side_port_id)
 {
 if (!pkt->isPrint()) {
diff --git a/src/mem/coherent_xbar.hh b/src/mem/coherent_xbar.hh
index 1c55cc0..9693d92 100644
--- a/src/mem/coherent_xbar.hh
+++ b/src/mem/coherent_xbar.hh
@@ -136,6 +136,13 @@
 xbar.recvFunctional(pkt, id);
 }

+void
+recvMemBackdoorReq(const MemBackdoorReq ,
+MemBackdoorPtr ) override
+{
+xbar.recvMemBackdoorReq(req, backdoor);
+}
+
 AddrRangeList
 getAddrRanges() const override
 {
@@ -374,6 +381,11 @@
 transaction.*/
 void recvFunctional(PacketPtr pkt, PortID cpu_side_port_id);

+/** Function called by the port when the crossbar receives a request  
for

+a memory backdoor.*/
+void recvMemBackdoorReq(const MemBackdoorReq ,
+MemBackdoorPtr );
+
 /** Function called by the port when the crossbar is receiving a  
functional

 snoop transaction.*/
 void recvFunctionalSnoop(PacketPtr pkt, PortID mem_side_port_id);
diff --git a/src/mem/mem_ctrl.cc b/src/mem/mem_ctrl.cc
index c65d68a..beaace1 100644
--- a/src/mem/mem_ctrl.cc
+++ b/src/mem/mem_ctrl.cc
@@ -1364,6 +1364,17 @@
  pkt->print());
 }

+void
+MemCtrl::recvMemBackdoorReq(const MemBackdoorReq ,
+MemBackdoorPtr )
+{
+panic_if(!dram->getAddrRange().contains(req.range().start()),
+"Can't handle address range for backdoor %s.",
+req.range().to_string());
+
+dram->getBackdoor(backdoor);
+}
+
 bool
 MemCtrl::recvFunctionalLogic(PacketPtr pkt, MemInterface* mem_intr)
 {
@@ -1474,6 +1485,13 @@
 pkt->popLabel();
 }

+void
+MemCtrl::MemoryPort::recvMemBackdoorReq(const MemBackdoorReq ,
+MemBackdoorPtr )
+{
+ctrl.recvMemBackdoorReq(req, backdoor);
+}
+
 Tick
 MemCtrl::MemoryPort::recvAtomic(PacketPtr pkt)
 {
diff --git a/src/mem/mem_ctrl.hh b/src/mem/mem_ctrl.hh
index fe5d478..2819fb4 100644
--- a/src/mem/mem_ctrl.hh
+++ b/src/mem/mem_ctrl.hh
@@ -267,6 +267,8 @@
 PacketPtr pkt, MemBackdoorPtr ) override;

 void recvFunctional(PacketPtr pkt) override;
+void

[gem5-dev] [S] Change in gem5/gem5[develop]: systemc: Enable DMI in the non-blocking/timing mode bridge.

2022-11-18 Thread Gabe Black (Gerrit) via gem5-dev 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65754?usp=email )



Change subject: systemc: Enable DMI in the non-blocking/timing mode bridge.
..

systemc: Enable DMI in the non-blocking/timing mode bridge.

Change-Id: Ia618081e2dbf8b49f62480ac5dc29f87100cd4f1
---
M src/systemc/tlm_bridge/tlm_to_gem5.cc
1 file changed, 34 insertions(+), 2 deletions(-)



diff --git a/src/systemc/tlm_bridge/tlm_to_gem5.cc  
b/src/systemc/tlm_bridge/tlm_to_gem5.cc

index 468ea83..bb8d578 100644
--- a/src/systemc/tlm_bridge/tlm_to_gem5.cc
+++ b/src/systemc/tlm_bridge/tlm_to_gem5.cc
@@ -241,6 +241,29 @@

 trans.acquire();

+MemBackdoor::Flags flags;
+switch (trans.get_command()) {
+  case tlm::TLM_READ_COMMAND:
+flags = MemBackdoor::Readable;
+break;
+  case tlm::TLM_WRITE_COMMAND:
+flags = MemBackdoor::Writeable;
+break;
+  default:
+panic("TlmToGem5Bridge: "
+"received transaction with unsupported command");
+}
+Addr start_addr = trans.get_address();
+Addr length = trans.get_data_length();
+
+MemBackdoorReq req({start_addr, start_addr + length}, flags);
+MemBackdoorPtr backdoor = nullptr;
+
+bmp.sendMemBackdoorReq(req, backdoor);
+
+if (backdoor)
+trans.set_dmi_allowed(true);
+
 auto res = payload2packet(_id, trans);
 auto pkt = res.first;
 pkt->pushSenderState(new Gem5SystemC::TlmSenderState(trans));
@@ -580,12 +603,12 @@
 DPRINTF(TlmBridge, "register blocking interface");
 socket.register_b_transport(
 this, ::b_transport);
-socket.register_get_direct_mem_ptr(
-this, ::get_direct_mem_ptr);
 } else {
 panic("gem5 operates neither in Timing nor in Atomic mode");
 }

+socket.register_get_direct_mem_ptr(
+this, ::get_direct_mem_ptr);
 socket.register_transport_dbg(
 this, ::transport_dbg);


--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia618081e2dbf8b49f62480ac5dc29f87100cd4f1
Gerrit-Change-Number: 65754
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-CC: Gabe Black 
Gerrit-MessageType: newchange
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