[gem5-dev] [S] Change in gem5/gem5[develop]: cpu: Allow PcCountTracker to compile in NULL ISA
Melissa Jost has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/68597?usp=email )
Change subject: cpu: Allow PcCountTracker to compile in NULL ISA
..
cpu: Allow PcCountTracker to compile in NULL ISA
While the PcCountTracker isn't necessary in the NULL ISA, the
structure of the standard library requires us to have it built
when running the replacement policy tests, which should fix
these tests failing within the nightlies at the moment.
Change-Id: I225b7923f2a11d351c24bdceba3ded4ed2b3bc87
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68597
Maintainer: Jason Lowe-Power
Reviewed-by: Jason Lowe-Power
Tested-by: kokoro
---
M src/cpu/probes/SConscript
1 file changed, 7 insertions(+), 8 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/probes/SConscript b/src/cpu/probes/SConscript
index c96ca78..9f43317 100644
--- a/src/cpu/probes/SConscript
+++ b/src/cpu/probes/SConscript
@@ -26,12 +26,11 @@
Import("*")
-if not env["CONF"]["USE_NULL_ISA"]:
-SimObject(
-"PcCountTracker.py",
-sim_objects=["PcCountTracker", "PcCountTrackerManager"],
-)
-Source("pc_count_tracker.cc")
-Source("pc_count_tracker_manager.cc")
+SimObject(
+"PcCountTracker.py",
+sim_objects=["PcCountTracker", "PcCountTrackerManager"],
+)
+Source("pc_count_tracker.cc")
+Source("pc_count_tracker_manager.cc")
-DebugFlag("PcCountTracker")
+DebugFlag("PcCountTracker")
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I225b7923f2a11d351c24bdceba3ded4ed2b3bc87
Gerrit-Change-Number: 68597
Gerrit-PatchSet: 2
Gerrit-Owner: Melissa Jost
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Melissa Jost
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: mem: Add a parameter which will make a memory truly a ROM.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/68557?usp=email )
Change subject: mem: Add a parameter which will make a memory truly a ROM.
..
mem: Add a parameter which will make a memory truly a ROM.
This piggy-backs on the writeOK method which already exists. It also
modifies the flags returned as part of the memory's backdoor
descriptor which doesn't enforce that the memory is read only, but will
let the other party know it's expected not to write to it.
Change-Id: Ib95e619c76c327d302e62a88515a92af11815981
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68557
Maintainer: Gabe Black
Tested-by: kokoro
Reviewed-by: Matthew Poremba
---
M src/mem/AbstractMemory.py
M src/mem/abstract_mem.cc
M src/mem/abstract_mem.hh
3 files changed, 14 insertions(+), 4 deletions(-)
Approvals:
Matthew Poremba: Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/AbstractMemory.py b/src/mem/AbstractMemory.py
index ea88fd8..7ab24bc 100644
--- a/src/mem/AbstractMemory.py
+++ b/src/mem/AbstractMemory.py
@@ -74,3 +74,5 @@
image_file = Param.String(
"", "Image to load into memory as its initial contents"
)
+
+writeable = Param.Bool(True, "Allow writes to this memory")
diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index 03f2557..9340f7e 100644
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -59,10 +59,11 @@
AbstractMemory::AbstractMemory(const Params ) :
ClockedObject(p), range(p.range), pmemAddr(NULL),
backdoor(params().range, nullptr,
- (MemBackdoor::Flags)(MemBackdoor::Readable |
- MemBackdoor::Writeable)),
+ (MemBackdoor::Flags)(p.writeable ?
+ MemBackdoor::Readable | MemBackdoor::Writeable :
+ MemBackdoor::Readable)),
confTableReported(p.conf_table_reported), inAddrMap(p.in_addr_map),
-kvmMap(p.kvm_map), _system(NULL),
+kvmMap(p.kvm_map), writeable(p.writeable), _system(NULL),
stats(*this)
{
panic_if(!range.valid() || !range.size(),
diff --git a/src/mem/abstract_mem.hh b/src/mem/abstract_mem.hh
index 53b7940..7f12487 100644
--- a/src/mem/abstract_mem.hh
+++ b/src/mem/abstract_mem.hh
@@ -129,6 +129,9 @@
// Should KVM map this memory for the guest
const bool kvmMap;
+// Are writes allowed to this memory
+const bool writeable;
+
std::list lockedAddrList;
// helper function for checkLockedAddrs(): we really want to
@@ -149,8 +152,12 @@
// requesting execution context), 'true' otherwise. Note that
// this method must be called on *all* stores since even
// non-conditional stores must clear any matching lock addresses.
-bool writeOK(PacketPtr pkt) {
+bool
+writeOK(PacketPtr pkt)
+{
const RequestPtr = pkt->req;
+if (!writeable)
+return false;
if (lockedAddrList.empty()) {
// no locked addrs: nothing to check, store_conditional fails
bool isLLSC = pkt->isLLSC();
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib95e619c76c327d302e62a88515a92af11815981
Gerrit-Change-Number: 68557
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jui-min Lee
Gerrit-Reviewer: Matthew Poremba
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: cpu: Allow PcCountTracker to compile in NULL ISA
Melissa Jost has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/68597?usp=email )
Change subject: cpu: Allow PcCountTracker to compile in NULL ISA
..
cpu: Allow PcCountTracker to compile in NULL ISA
While the PcCountTracker isn't necessary in the NULL ISA, the
structure of the standard library requires us to have it built
when running the replacement policy tests, which should fix
these tests failing within the nightlies at the moment.
Change-Id: I225b7923f2a11d351c24bdceba3ded4ed2b3bc87
---
M src/cpu/probes/SConscript
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/src/cpu/probes/SConscript b/src/cpu/probes/SConscript
index c96ca78..9f43317 100644
--- a/src/cpu/probes/SConscript
+++ b/src/cpu/probes/SConscript
@@ -26,12 +26,11 @@
Import("*")
-if not env["CONF"]["USE_NULL_ISA"]:
-SimObject(
-"PcCountTracker.py",
-sim_objects=["PcCountTracker", "PcCountTrackerManager"],
-)
-Source("pc_count_tracker.cc")
-Source("pc_count_tracker_manager.cc")
+SimObject(
+"PcCountTracker.py",
+sim_objects=["PcCountTracker", "PcCountTrackerManager"],
+)
+Source("pc_count_tracker.cc")
+Source("pc_count_tracker_manager.cc")
-DebugFlag("PcCountTracker")
+DebugFlag("PcCountTracker")
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I225b7923f2a11d351c24bdceba3ded4ed2b3bc87
Gerrit-Change-Number: 68597
Gerrit-PatchSet: 1
Gerrit-Owner: Melissa Jost
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-riscv,dev: Add HiFive Base Platform
Roger Chang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/68199?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch-riscv,dev: Add HiFive Base Platform .. arch-riscv,dev: Add HiFive Base Platform This is basic abstract platform and all of RISC-V system should use platform inherit from HiFiveBase, HiFiveBase declared the common way to handle interrupt. Change-Id: I52122e1c82c200d7e6012433c2535c07d427f637 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68199 Maintainer: Jason Lowe-Power Reviewed-by: Yu-hsin Wang Tested-by: kokoro --- M src/dev/riscv/HiFive.py M src/dev/riscv/SConscript M src/dev/riscv/hifive.cc M src/dev/riscv/hifive.hh 4 files changed, 107 insertions(+), 79 deletions(-) Approvals: kokoro: Regressions pass Yu-hsin Wang: Looks good to me, approved Jason Lowe-Power: Looks good to me, approved diff --git a/src/dev/riscv/HiFive.py b/src/dev/riscv/HiFive.py index 4669686..5bd6363 100755 --- a/src/dev/riscv/HiFive.py +++ b/src/dev/riscv/HiFive.py @@ -1,5 +1,6 @@ # Copyright (c) 2021 Huawei International # Copyright (c) 2022 EXAscale Performance SYStems (EXAPSYS) +# Copyright (c) 2023 Google LLC # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -63,24 +64,14 @@ _dma_coherent = True -class HiFive(Platform): -"""HiFive Platform +class HiFiveBase(Platform): +"""HiFive Base Abstract Platform Implementation: This is the base class for SiFive's HiFive board series. It contains the CLINT and PLIC interrupt controllers, Uart and Disk. -Implementation details are based on SiFive -FU540-C000. https://sifive.cdn.prismic.io/ -sifive/b5e7a29c-d3c2-44ea-85fb-acc1df282e2 -1_FU540-C000-v1p3.pdf - -Setup: -The following sections outline the required -setup for a RISC-V HiFive platform. See -configs/example/riscv/fs_linux.py for example. - Driving CLINT: CLINT has an interrupt pin which increments mtime. It can be connected to any interrupt @@ -88,7 +79,7 @@ abstract RTC wrapper called RiscvRTC can be used. -Attaching PLIC devices: +Driving PLIC: PLIC handles external interrupts. Interrupt PioDevices should inherit from PlicIntDevice (PCI and DMA not yet implemented). It contains @@ -96,63 +87,30 @@ to call platform->postPciInt(id). All PLIC interrupt devices should be returned -by _off_chip_devices(). Calling attachPlic sets -up the PLIC interrupt source count. - -Uart: -The HiFive platform also has an uart_int_id. -This is because Uart8250 uses postConsoleInt -instead of postPciInt. In the future if a Uart -that inherits PlicIntDevice is implemented, -this can be removed. - -Disk: -See fs_linux.py for setup example. - -PMAChecker: -The PMAChecker will be attached to the MMU of -each CPU (which allows them to differ). See -fs_linux.py for setup example. +by _off_chip_devices(). """ -type = "HiFive" +type = "HiFiveBase" cxx_header = "dev/riscv/hifive.hh" -cxx_class = "gem5::HiFive" +cxx_class = "gem5::HiFiveBase" # CLINT -clint = Param.Clint(Clint(pio_addr=0x200), "CLINT") +clint = Param.Clint(NULL, "CLINT") # PLIC -plic = Param.Plic(Plic(pio_addr=0xC00), "PLIC") +plic = Param.PlicBase(NULL, "PLIC") -# PCI -pci_host = GenericRiscvPciHost( -conf_base=0x3000, -conf_size="256MB", -conf_device_bits=12, -pci_pio_base=0x2F00, -pci_mem_base=0x4000, -) - -# Uart -uart = RiscvUart8250(pio_addr=0x1000) # Int source ID to redirect console interrupts to # Set to 0 if using a pci interrupt for Uart instead -uart_int_id = Param.Int(0xA, "PLIC Uart interrupt ID") -terminal = Terminal() +uart_int_id = Param.Int(0, "PLIC Uart interrupt ID") def _on_chip_devices(self): """Returns a list of on-chip peripherals""" -return [self.clint, self.plic] +return [] def _off_chip_devices(self): """Returns a list of off-chip peripherals""" -devices = [self.uart] -if hasattr(self, "disk"): -devices.append(self.disk) -if hasattr(self, "rng"): -devices.append(self.rng) -return devices +return [] def _on_chip_ranges(self): """Returns a list of on-chip peripherals @@ -172,17 +130,6 @@ for dev in self._off_chip_devices() ] -def attachPlic(self): -"""Count number of PLIC interrupt sources""" -plic_srcs = [ -
[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv,dev: Add PLIC abstract class to support multiple PLIC impl...
Roger Chang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/68197?usp=email )
(
7 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-riscv,dev: Add PLIC abstract class to support
multiple PLIC implementation
..
arch-riscv,dev: Add PLIC abstract class to support multiple PLIC
implementation
We should create PLIC abstract and have common interface to let
HiFive platform send and clear interrupt to variable type of PLIC
Change-Id: Ic3a2ffc2a2a002540b400c70c85c3495fa838f2a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68197
Maintainer: Jason Lowe-Power
Reviewed-by: Yu-hsin Wang
Tested-by: kokoro
---
M src/dev/riscv/Plic.py
M src/dev/riscv/SConscript
M src/dev/riscv/plic.cc
M src/dev/riscv/plic.hh
4 files changed, 41 insertions(+), 7 deletions(-)
Approvals:
kokoro: Regressions pass
Yu-hsin Wang: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
diff --git a/src/dev/riscv/Plic.py b/src/dev/riscv/Plic.py
index 33b6940..b4486b9 100644
--- a/src/dev/riscv/Plic.py
+++ b/src/dev/riscv/Plic.py
@@ -1,4 +1,5 @@
# Copyright (c) 2021 Huawei International
+# Copyright (c) 2023 Google LLC
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -39,7 +40,22 @@
from m5.util.fdthelper import *
-class Plic(BasicPioDevice):
+class PlicBase(BasicPioDevice):
+"""
+This is abstract class of PLIC and
+define interface to handle received
+interrupt singal from device
+"""
+
+type = "PlicBase"
+cxx_header = "dev/riscv/plic.hh"
+cxx_class = "gem5::PlicBase"
+abstract = True
+
+pio_size = Param.Addr("PIO Size")
+
+
+class Plic(PlicBase):
"""
This implementation of PLIC is based on
the SiFive U54MC datasheet:
@@ -51,7 +67,7 @@
type = "Plic"
cxx_header = "dev/riscv/plic.hh"
cxx_class = "gem5::Plic"
-pio_size = Param.Addr(0x400, "PIO Size")
+pio_size = 0x400
n_src = Param.Int("Number of interrupt sources")
n_contexts = Param.Int(
"Number of interrupt contexts. Usually the number "
diff --git a/src/dev/riscv/SConscript b/src/dev/riscv/SConscript
index af0b96b..6e3376b 100755
--- a/src/dev/riscv/SConscript
+++ b/src/dev/riscv/SConscript
@@ -2,6 +2,7 @@
# Copyright (c) 2021 Huawei International
# Copyright (c) 2022 EXAscale Performance SYStems (EXAPSYS)
+# Copyright (c) 2023 Google LLC
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -34,7 +35,7 @@
SimObject('LupV.py', sim_objects=['LupV'], tags='riscv isa')
SimObject('Clint.py', sim_objects=['Clint'], tags='riscv isa')
SimObject('PlicDevice.py', sim_objects=['PlicIntDevice'], tags='riscv isa')
-SimObject('Plic.py', sim_objects=['Plic'], tags='riscv isa')
+SimObject('Plic.py', sim_objects=['PlicBase', 'Plic'], tags='riscv isa')
SimObject('RTC.py', sim_objects=['RiscvRTC'], tags='riscv isa')
SimObject('RiscvVirtIOMMIO.py', sim_objects=['RiscvMmioVirtIO'],
tags='riscv isa')
diff --git a/src/dev/riscv/plic.cc b/src/dev/riscv/plic.cc
index 371af9e..fd42920 100644
--- a/src/dev/riscv/plic.cc
+++ b/src/dev/riscv/plic.cc
@@ -45,6 +45,7 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "params/Plic.hh"
+#include "params/PlicBase.hh"
#include "sim/system.hh"
namespace gem5
@@ -53,7 +54,7 @@
using namespace RiscvISA;
Plic::Plic(const Params ) :
-BasicPioDevice(params, params.pio_size),
+PlicBase(params),
system(params.system),
nSrc(params.n_src),
nContext(params.n_contexts),
diff --git a/src/dev/riscv/plic.hh b/src/dev/riscv/plic.hh
index d077e73..00128ee 100644
--- a/src/dev/riscv/plic.hh
+++ b/src/dev/riscv/plic.hh
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2021 Huawei International
+ * Copyright (c) 2023 Google LLC
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -47,6 +48,7 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "params/Plic.hh"
+#include "params/PlicBase.hh"
#include "sim/system.hh"
namespace gem5
@@ -94,7 +96,21 @@
std::vector maxPriority;
};
-class Plic : public BasicPioDevice
+class PlicBase : public BasicPioDevice
+{
+ public:
+typedef PlicBaseParams Params;
+PlicBase(const Params ) :
+ BasicPioDevice(params, params.pio_size)
+{}
+
+// Interrupt interface to send signal to PLIC
+virtual void post(int src_id) = 0;
+// Interrupt interface to clear signal to PLIC
+virtual void clear(int src_id) = 0;
+};
+
+class Plic : public PlicBase
{
// Params
protected:
@@ -125,8 +141,8 @@
/**
* Interrupt interface
*/
-void post(int src_id);
-void clear(int src_id);
+void post(int src_id) override;
+void clear(int src_id)
[gem5-dev] [S] Change in gem5/gem5[develop]: mem: Add a parameter which will make a memory truly a ROM.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/68557?usp=email )
Change subject: mem: Add a parameter which will make a memory truly a ROM.
..
mem: Add a parameter which will make a memory truly a ROM.
This piggy-backs on the writeOK method which already exists. It also
modifies the flags returned as part of the memory's backdoor
descriptor which doesn't enforce that the memory is read only, but will
let the other party know it's expected not to write to it.
Bug: 254411221
Test: Used this flag with the GSA's boot ROM and saw that it no longer
Test: accepted a corrupting write which overwrote the reset vector.
Change-Id: Ib95e619c76c327d302e62a88515a92af11815981
---
M src/mem/AbstractMemory.py
M src/mem/abstract_mem.cc
M src/mem/abstract_mem.hh
3 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/src/mem/AbstractMemory.py b/src/mem/AbstractMemory.py
index ea88fd8..7ab24bc 100644
--- a/src/mem/AbstractMemory.py
+++ b/src/mem/AbstractMemory.py
@@ -74,3 +74,5 @@
image_file = Param.String(
"", "Image to load into memory as its initial contents"
)
+
+writeable = Param.Bool(True, "Allow writes to this memory")
diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index 03f2557..9340f7e 100644
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -59,10 +59,11 @@
AbstractMemory::AbstractMemory(const Params ) :
ClockedObject(p), range(p.range), pmemAddr(NULL),
backdoor(params().range, nullptr,
- (MemBackdoor::Flags)(MemBackdoor::Readable |
- MemBackdoor::Writeable)),
+ (MemBackdoor::Flags)(p.writeable ?
+ MemBackdoor::Readable | MemBackdoor::Writeable :
+ MemBackdoor::Readable)),
confTableReported(p.conf_table_reported), inAddrMap(p.in_addr_map),
-kvmMap(p.kvm_map), _system(NULL),
+kvmMap(p.kvm_map), writeable(p.writeable), _system(NULL),
stats(*this)
{
panic_if(!range.valid() || !range.size(),
diff --git a/src/mem/abstract_mem.hh b/src/mem/abstract_mem.hh
index 53b7940..7f12487 100644
--- a/src/mem/abstract_mem.hh
+++ b/src/mem/abstract_mem.hh
@@ -129,6 +129,9 @@
// Should KVM map this memory for the guest
const bool kvmMap;
+// Are writes allowed to this memory
+const bool writeable;
+
std::list lockedAddrList;
// helper function for checkLockedAddrs(): we really want to
@@ -149,8 +152,12 @@
// requesting execution context), 'true' otherwise. Note that
// this method must be called on *all* stores since even
// non-conditional stores must clear any matching lock addresses.
-bool writeOK(PacketPtr pkt) {
+bool
+writeOK(PacketPtr pkt)
+{
const RequestPtr = pkt->req;
+if (!writeable)
+return false;
if (lockedAddrList.empty()) {
// no locked addrs: nothing to check, store_conditional fails
bool isLLSC = pkt->isLLSC();
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib95e619c76c327d302e62a88515a92af11815981
Gerrit-Change-Number: 68557
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black
Gerrit-CC: Gabe Black
Gerrit-MessageType: newchange
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[gem5-dev] [M] Change in gem5/gem5[develop]: scons: allow building without duplicating source files
Alex Richardson has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/68518?usp=email )
Change subject: scons: allow building without duplicating source files
..
scons: allow building without duplicating source files
This adds a new scons flag --no-duplicate to build without linking source
files to the build directory.
I find this very helpful when using CLion, since i can now generate a
compilation database using `bear scons build/ALL/gem5.debug --no-duplicate`
and CLion will now correctly semantically analyze all the files inside src/.
It also ensures that clicking on a build warning/error now opens the
real source file rather than a symlink.
This is not enabled by default since it's possible that certain use
cases are not working correctly, but the basic testing I've done so
far appears to work just fine.
Change-Id: Iddc9bf9c8211e68e5432c0a07f5c95f427c1ca16
---
M SConstruct
M ext/drampower/SConscript
M ext/dramsim2/SConscript
M ext/dramsim3/SConscript
M ext/fputils/SConscript
M ext/iostream3/SConscript
M ext/libelf/SConscript
M ext/libfdt/SConscript
M ext/nomali/SConscript
M ext/softfloat/SConscript
M ext/systemc/SConscript
M site_scons/gem5_scons/sources.py
M src/SConscript
M src/mem/slicc/symbols/SymbolTable.py
M util/m5/SConstruct
M util/statetrace/SConstruct
M util/tlm/SConstruct
17 files changed, 90 insertions(+), 73 deletions(-)
diff --git a/SConstruct b/SConstruct
index 6abbb51..0f0340e 100755
--- a/SConstruct
+++ b/SConstruct
@@ -145,6 +145,8 @@
help='Enable support for the gprof profiler')
AddOption('--pprof', action='store_true',
help='Enable support for the pprof profiler')
+AddOption('--no-duplicate', action='store_false', dest='duplicate_sources',
+ help='Enable support for the pprof profiler')
# Inject the built_tools directory into the python path.
sys.path[1:1] = [ Dir('#build_tools').abspath ]
@@ -264,6 +266,7 @@
# Add shared top-level headers
main.Prepend(CPPPATH=Dir('include'))
+main.Prepend(CPPPATH=Dir('src'))
@@ -774,11 +777,13 @@
build_dir = os.path.relpath(root, ext_dir)
SConscript(os.path.join(root, 'SConscript'),
variant_dir=os.path.join(variant_ext, build_dir),
- exports=exports)
+ exports=exports,
+ duplicate=GetOption('duplicate_sources'))
# The src/SConscript file sets up the build rules in 'env' according
# to the configured variables. It returns a list of environments,
# one for each variant build (debug, opt, etc.)
-SConscript('src/SConscript', variant_dir=variant_path, exports=exports)
+SConscript('src/SConscript', variant_dir=variant_path, exports=exports,
+ duplicate=GetOption('duplicate_sources'))
atexit.register(summarize_warnings)
diff --git a/ext/drampower/SConscript b/ext/drampower/SConscript
index 870d050..38acbf4 100644
--- a/ext/drampower/SConscript
+++ b/ext/drampower/SConscript
@@ -41,7 +41,7 @@
Import('env')
-env.Prepend(CPPPATH=Dir('./src'))
+env.Prepend(CPPPATH=Dir('./src').srcnode())
# Add the appropriate files for the library
drampower_files = []
diff --git a/ext/dramsim2/SConscript b/ext/dramsim2/SConscript
index 7eb178d..c296538 100644
--- a/ext/dramsim2/SConscript
+++ b/ext/dramsim2/SConscript
@@ -85,6 +85,6 @@
dramenv.Library('dramsim2', [dramenv.SharedObject(f) for f in dram_files])
-env.Prepend(CPPPATH=Dir('.'))
+env.Prepend(CPPPATH=Dir('.').srcnode())
env.Append(LIBS=['dramsim2'])
env.Prepend(LIBPATH=[Dir('.')])
diff --git a/ext/dramsim3/SConscript b/ext/dramsim3/SConscript
index b717816..6be9690 100644
--- a/ext/dramsim3/SConscript
+++ b/ext/dramsim3/SConscript
@@ -56,12 +56,12 @@
if thermal:
superlu_path = os.path.join(dramsim_path, 'ext/SuperLU_MT_3.1/lib')
-env.Prepend(CPPPATH=Dir('.'))
+env.Prepend(CPPPATH=Dir('.').srcnode())
env.Append(LIBS=['dramsim3', 'superlu_mt_OPENMP', 'm', 'f77blas',
'atlas', 'gomp'],
LIBPATH=[dramsim_path, superlu_path])
else:
-env.Prepend(CPPPATH=Dir('.'))
+env.Prepend(CPPPATH=Dir('.').srcnode())
# a littel hacky but can get a shared library working
env.Append(LIBS=['dramsim3', 'gomp'],
LIBPATH=[dramsim_path], # compile-time lookup
diff --git a/ext/fputils/SConscript b/ext/fputils/SConscript
index 6a8e44f..bc158c2 100644
--- a/ext/fputils/SConscript
+++ b/ext/fputils/SConscript
@@ -30,7 +30,7 @@
Import('env')
-env.Prepend(CPPPATH=Dir('./include'))
+env.Prepend(CPPPATH=Dir('./include').srcnode())
fpenv = env.Clone()
diff --git a/ext/iostream3/SConscript b/ext/iostream3/SConscript
index df0b213..3b4e937 100644
--- a/ext/iostream3/SConscript
+++ b/ext/iostream3/SConscript
@@ -41,6 +41,6 @@
env.Library('iostream3',
[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Fix GCC -W(maybe-)uninitialized warnings
Alex Richardson has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/68517?usp=email )
Change subject: tests: Fix GCC -W(maybe-)uninitialized warnings
..
tests: Fix GCC -W(maybe-)uninitialized warnings
These all look like valid (but harmless) diagnostics to me and are
all simple to fix. Most of them can be fixed by using ASSERT_* variants
of the GTest checkers to ensure that the remainder of the function is
not executed and the uninitialized result isn't touched.
Change-Id: Ib5fe2ac2ec539c880d670ebc3321ce98940c7e38
---
M src/base/circlebuf.test.cc
M src/base/str.test.cc
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/base/circlebuf.test.cc b/src/base/circlebuf.test.cc
index 02fe396..c7913f7 100644
--- a/src/base/circlebuf.test.cc
+++ b/src/base/circlebuf.test.cc
@@ -136,7 +136,7 @@
TEST(CircleBufTest, ProduceConsumeEmpty)
{
CircleBuf buf(8);
-char foo[1];
+char foo[1] = {'a'};
// buf is empty to begin with.
EXPECT_TRUE(buf.empty());
diff --git a/src/base/str.test.cc b/src/base/str.test.cc
index f999c98..815c553 100644
--- a/src/base/str.test.cc
+++ b/src/base/str.test.cc
@@ -254,7 +254,7 @@
{
int8_t output;
std::string input = "-128";
-EXPECT_TRUE(to_number(input, output));
+ASSERT_TRUE(to_number(input, output));
EXPECT_EQ(-128, output);
}
@@ -276,7 +276,7 @@
{
uint8_t output;
std::string input = "255";
-EXPECT_TRUE(to_number(input, output));
+ASSERT_TRUE(to_number(input, output));
EXPECT_EQ(255, output);
}
@@ -292,11 +292,11 @@
{
uint8_t output;
std::string input_1 = "2.99";
-EXPECT_TRUE(to_number(input_1, output));
+ASSERT_TRUE(to_number(input_1, output));
EXPECT_EQ(2, output);
std::string input_2 = "3.99";
-EXPECT_TRUE(to_number(input_2, output));
+ASSERT_TRUE(to_number(input_2, output));
EXPECT_EQ(3, output);
}
@@ -308,7 +308,7 @@
{
uint8_t output;
std::string input = "255.99";
-EXPECT_TRUE(to_number(input, output));
+ASSERT_TRUE(to_number(input, output));
EXPECT_EQ(255, output);
}
@@ -344,7 +344,7 @@
int64_t output;
int64_t input_number = 0x;
std::string input = std::to_string(input_number);
-EXPECT_TRUE(to_number(input, output));
+ASSERT_TRUE(to_number(input, output));
EXPECT_EQ(input_number, output);
}
@@ -363,7 +363,7 @@
};
Number output;
std::string input = "2";
-EXPECT_TRUE(to_number(input, output));
+ASSERT_TRUE(to_number(input, output));
EXPECT_EQ(TWO, output);
}
@@ -384,7 +384,7 @@
float output;
std::string input = "0.1";
float expected_output = 0.1;
-EXPECT_TRUE(to_number(input, output));
+ASSERT_TRUE(to_number(input, output));
EXPECT_EQ(expected_output, output);
}
@@ -393,7 +393,7 @@
float output;
std::string input = "10";
float expected_output = 10.0;
-EXPECT_TRUE(to_number(input, output));
+ASSERT_TRUE(to_number(input, output));
EXPECT_EQ(expected_output, output);
}
@@ -402,7 +402,7 @@
float output;
std::string input = "-0.1";
float expected_output = -0.1;
-EXPECT_TRUE(to_number(input, output));
+ASSERT_TRUE(to_number(input, output));
EXPECT_EQ(expected_output, output);
}
--
To view, visit
https://gem5-review.googlesource.com/c/public/gem5/+/68517?usp=email
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib5fe2ac2ec539c880d670ebc3321ce98940c7e38
Gerrit-Change-Number: 68517
Gerrit-PatchSet: 1
Gerrit-Owner: Alex Richardson
Gerrit-MessageType: newchange
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