[gem5-dev] [XS] Change in gem5/gem5[develop]: stdlib: Fix bug in MESI_Three_Level_Cache initialization
Hoa Nguyen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/68857?usp=email ) Change subject: stdlib: Fix bug in MESI_Three_Level_Cache initialization .. stdlib: Fix bug in MESI_Three_Level_Cache initialization Change-Id: I2d06c842955aa1868053a0d852fc523392480154 Signed-off-by: Hoa Nguyen Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68857 Tested-by: kokoro Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- M src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py M src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py 2 files changed, 3 insertions(+), 3 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, but someone else must approve; Looks good to me, approved Hoa Nguyen: Looks good to me, approved kokoro: Regressions pass diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py index 9f47e41..b485481 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py @@ -68,14 +68,14 @@ self.Icache = RubyCache( size=l1i_size, assoc=l1i_assoc, -start_index_bit=self.getBlockSizeBits(cache_line_size.value), +start_index_bit=self.getBlockSizeBits(cache_line_size), is_icache=True, replacement_policy=LRURP(), ) self.Dcache = RubyCache( size=l1d_size, assoc=l1d_assoc, -start_index_bit=self.getBlockSizeBits(cache_line_size.value), +start_index_bit=self.getBlockSizeBits(cache_line_size), is_icache=False, replacement_policy=LRURP(), ) diff --git a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py index d8c9659..d54e1ab 100644 --- a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py +++ b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py @@ -67,7 +67,7 @@ self.cache = RubyCache( size=l2_size, assoc=l2_assoc, -start_index_bit=self.getBlockSizeBits(cache_line_size.value), +start_index_bit=self.getBlockSizeBits(cache_line_size), is_icache=False, ) # l2_select_num_bits is ruby backend terminology. -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/68857?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I2d06c842955aa1868053a0d852fc523392480154 Gerrit-Change-Number: 68857 Gerrit-PatchSet: 3 Gerrit-Owner: Hoa Nguyen Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Hoa Nguyen Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: stdlib: use atomic_noncaching when using AtomicSimpleCPU with Ruby
Hoa Nguyen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/68877?usp=email ) Change subject: stdlib: use atomic_noncaching when using AtomicSimpleCPU with Ruby .. stdlib: use atomic_noncaching when using AtomicSimpleCPU with Ruby mem_mode is supposed to be atomic_noncaching when running AtomicSimpleCPU with Ruby cache. Change-Id: Icb419f9370038f5c1f80dd879b187338279a5b93 Signed-off-by: Hoa Nguyen Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68877 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M src/python/gem5/components/processors/base_cpu_processor.py M src/python/gem5/components/processors/simple_switchable_processor.py 2 files changed, 11 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/python/gem5/components/processors/base_cpu_processor.py b/src/python/gem5/components/processors/base_cpu_processor.py index d311a0f..9a75615 100644 --- a/src/python/gem5/components/processors/base_cpu_processor.py +++ b/src/python/gem5/components/processors/base_cpu_processor.py @@ -97,6 +97,7 @@ "'atomic_noncaching' memory mode. This will skip caching " "completely." ) +board.set_mem_mode(MemMode.ATOMIC_NONCACHING) else: board.set_mem_mode(MemMode.ATOMIC) else: diff --git a/src/python/gem5/components/processors/simple_switchable_processor.py b/src/python/gem5/components/processors/simple_switchable_processor.py index 56603fa..e397841 100644 --- a/src/python/gem5/components/processors/simple_switchable_processor.py +++ b/src/python/gem5/components/processors/simple_switchable_processor.py @@ -103,6 +103,16 @@ def incorporate_processor(self, board: AbstractBoard) -> None: super().incorporate_processor(board=board) +if ( +board.get_cache_hierarchy().is_ruby() +and self._mem_mode == MemMode.ATOMIC +): +warn( +"Using an atomic core with Ruby will result in " +"'atomic_noncaching' memory mode. This will skip caching " +"completely." +) +self._mem_mode = MemMode.ATOMIC_NONCACHING board.set_mem_mode(self._mem_mode) def switch(self): -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/68877?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Icb419f9370038f5c1f80dd879b187338279a5b93 Gerrit-Change-Number: 68877 Gerrit-PatchSet: 4 Gerrit-Owner: Hoa Nguyen Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Hoa Nguyen Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[develop]: stdlib: use atomic_noncaching when using AtomicSimpleCPU with Ruby
Hoa Nguyen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/68877?usp=email ) Change subject: stdlib: use atomic_noncaching when using AtomicSimpleCPU with Ruby .. stdlib: use atomic_noncaching when using AtomicSimpleCPU with Ruby mem_mode is supposed to be atomic_noncaching when running AtomicSimpleCPU with Ruby cache. Change-Id: Icb419f9370038f5c1f80dd879b187338279a5b93 Signed-off-by: Hoa Nguyen --- M src/python/gem5/components/processors/base_cpu_processor.py M src/python/gem5/components/processors/simple_switchable_processor.py 2 files changed, 6 insertions(+), 0 deletions(-) diff --git a/src/python/gem5/components/processors/base_cpu_processor.py b/src/python/gem5/components/processors/base_cpu_processor.py index d311a0f..9a75615 100644 --- a/src/python/gem5/components/processors/base_cpu_processor.py +++ b/src/python/gem5/components/processors/base_cpu_processor.py @@ -97,6 +97,7 @@ "'atomic_noncaching' memory mode. This will skip caching " "completely." ) +board.set_mem_mode(MemMode.ATOMIC_NONCACHING) else: board.set_mem_mode(MemMode.ATOMIC) else: diff --git a/src/python/gem5/components/processors/simple_switchable_processor.py b/src/python/gem5/components/processors/simple_switchable_processor.py index 56603fa..bfeb9bc 100644 --- a/src/python/gem5/components/processors/simple_switchable_processor.py +++ b/src/python/gem5/components/processors/simple_switchable_processor.py @@ -103,6 +103,11 @@ def incorporate_processor(self, board: AbstractBoard) -> None: super().incorporate_processor(board=board) +# special case: +# ruby cache doesn't support "atomic" mem mode; however, ruby cache +# supports "atomic_noncaching" mem mode, which bypasses the cache. +if board.get_cache_hierarchy().is_ruby() and self._mem_mode = MemMode.ATOMIC: +self._mem_mode = MemMode.ATOMIC_NONCACHING board.set_mem_mode(self._mem_mode) def switch(self): -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/68877?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Icb419f9370038f5c1f80dd879b187338279a5b93 Gerrit-Change-Number: 68877 Gerrit-PatchSet: 1 Gerrit-Owner: Hoa Nguyen Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
