[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Add "--no-duplicate-sources" option to SConstruct in util/

2023-04-13 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69797?usp=email )


Change subject: scons: Add "--no-duplicate-sources" option to SConstruct in  
util/

..

scons: Add "--no-duplicate-sources" option to SConstruct in util/

Patch [1] caused building util/m5 to fail due to the flag was not
an option in the SConstruct file. It is apparently the case for other
programs in util/ relying on scons.

This patch fixes the above problem, and also adheres to the default
behavior introduced by [2].

[1] This patch introduced the "--no-duplicate-sources" flag to the
scons build in util/
https://gem5-review.googlesource.com/c/public/gem5/+/68518

[2] This patch turns this flag off by default,
https://gem5-review.googlesource.com/c/public/gem5/+/69717

Change-Id: I51376f7b3bf06438b7bc7ff84bc599deecac5bd1
Signed-off-by: Hoa Nguyen 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69797
Maintainer: Bobby Bruce 
Reviewed-by: Alex Richardson 
Tested-by: kokoro 
Reviewed-by: Ayaz Akram 
---
M util/m5/SConstruct
M util/statetrace/SConstruct
M util/tlm/SConstruct
3 files changed, 15 insertions(+), 0 deletions(-)

Approvals:
  kokoro: Regressions pass
  Alex Richardson: Looks good to me, but someone else must approve
  Bobby Bruce: Looks good to me, approved
  Ayaz Akram: Looks good to me, approved




diff --git a/util/m5/SConstruct b/util/m5/SConstruct
index c2c4a50..7f07b94 100644
--- a/util/m5/SConstruct
+++ b/util/m5/SConstruct
@@ -49,6 +49,9 @@
 AddOption('--run-tests', dest='run_tests', action='store_true',
   help='Enable test output xml files as build targets.')
 AddOption('--verbose', dest='verbose', action='store_true')
+AddOption('--no-duplicate-sources', action='store_false', default=True,
+  dest='duplicate_sources',
+  help='Do not create symlinks to sources in the build directory')

 # Universal settings.
 if GetOption('debug_build'):
diff --git a/util/statetrace/SConstruct b/util/statetrace/SConstruct
index 945976e..2e1a631 100644
--- a/util/statetrace/SConstruct
+++ b/util/statetrace/SConstruct
@@ -57,6 +57,12 @@

 main['CXX'] = ARGUMENTS.get('CXX', main['CXX'])

+# An option not to link source files in the build directory.
+# Not enabled by default.
+AddOption('--no-duplicate-sources', action='store_false', default=True,
+  dest='duplicate_sources',
+  help='Do not create symlinks to sources in the build directory')
+
 for arch in arches:
 env = main.Clone()
 env['CXX'] = ARGUMENTS.get(arch.upper() + 'CXX', env['CXX'])
diff --git a/util/tlm/SConstruct b/util/tlm/SConstruct
index 6c65cfd..3f4abf8 100644
--- a/util/tlm/SConstruct
+++ b/util/tlm/SConstruct
@@ -80,6 +80,12 @@
 AddOption('--no-colors', dest='use_colors', action='store_false',
   help="Don't add color to abbreviated scons output")

+# An option not to link source files in the build directory.
+# Not enabled by default.
+AddOption('--no-duplicate-sources', action='store_false', default=True,
+  dest='duplicate_sources',
+  help='Do not create symlinks to sources in the build directory')
+
 env.SConsignFile('build/systemc/sconsign')
 SConscript(gem5_root + '/ext/systemc/SConscript',
variant_dir='build/systemc',

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I51376f7b3bf06438b7bc7ff84bc599deecac5bd1
Gerrit-Change-Number: 69797
Gerrit-PatchSet: 3
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Alex Richardson 
Gerrit-Reviewer: Ayaz Akram 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Build failed in Jenkins: nightly #574

2023-04-13 Thread jenkins-no-reply--- via gem5-dev 
See 

Changes:

[gabe.black] base: fatal() if a socket path doesn't fit in sockaddr_un.sun_path.

[rogerycchang] arch-riscv: Insert symbol table of bootloader into debug symbol 
table


--
[...truncated 4.44 MB...]
 [   SHCXX] RISCV/python/_m5/param_QemuFwCfgMmio.cc -> .os
 [ TRACING]  -> RISCV/debug/QemuFwCfg.hh
 [   SHCXX] RISCV/python/_m5/param_QemuFwCfgIo.cc -> .os
 [ TRACING]  -> RISCV/debug/QemuFwCfgVerbose.hh
 [ TRACING]  -> RISCV/debug/QemuFwCfg.cc
 [ TRACING]  -> RISCV/debug/QemuFwCfgVerbose.cc
 [   SHCXX] src/dev/qemu/fw_cfg.cc -> RISCV/dev/qemu/fw_cfg.os
 [   SHCXX] RISCV/debug/QemuFwCfgVerbose.cc -> .os
 [   SHCXX] RISCV/debug/QemuFwCfg.cc -> .os
 [   SHCXX] RISCV/dev/serial/Serial.py.cc -> .os
 [SO Param] m5.objects.Serial, SerialDevice -> 
RISCV/python/_m5/param_SerialDevice.cc
 [SO Param] m5.objects.Serial, SerialDevice -> RISCV/params/SerialDevice.hh
 [SO Param] m5.objects.Serial, SerialNullDevice -> 
RISCV/python/_m5/param_SerialNullDevice.cc
 [   SHCXX] RISCV/dev/serial/Terminal.py.cc -> .os
 [SO Param] m5.objects.Terminal, Terminal -> RISCV/python/_m5/param_Terminal.cc
 [ENUM STR] m5.objects.Terminal, TerminalDump -> RISCV/enums/TerminalDump.cc
 [   SHCXX] RISCV/dev/serial/Uart.py.cc -> .os
 [   SHCXX] RISCV/python/_m5/param_SerialDevice.cc -> .os
 [SO Param] m5.objects.Serial, SerialNullDevice -> 
RISCV/params/SerialNullDevice.hh
 [ENUMDECL] m5.objects.Terminal, TerminalDump -> RISCV/enums/TerminalDump.hh
 [SO Param] m5.objects.Terminal, Terminal -> RISCV/params/Terminal.hh
 [   SHCXX] RISCV/python/_m5/param_SerialNullDevice.cc -> .os
 [   SHCXX] RISCV/enums/TerminalDump.cc -> .os
 [   SHCXX] RISCV/python/_m5/param_Terminal.cc -> .os
 [SO Param] m5.objects.Uart, Uart -> RISCV/python/_m5/param_Uart.cc
 [SO Param] m5.objects.Uart, Uart -> RISCV/params/Uart.hh
 [   SHCXX] RISCV/python/_m5/param_Uart.cc -> .os
 [SO Param] m5.objects.Uart, SimpleUart -> RISCV/python/_m5/param_SimpleUart.cc
 [SO Param] m5.objects.Uart, SimpleUart -> RISCV/params/SimpleUart.hh
 [SO Param] m5.objects.Uart, Uart8250 -> RISCV/python/_m5/param_Uart8250.cc
 [   SHCXX] RISCV/python/_m5/param_SimpleUart.cc -> .os
 [SO Param] m5.objects.Uart, Uart8250 -> RISCV/params/Uart8250.hh
 [   SHCXX] RISCV/python/_m5/param_Uart8250.cc -> .os
 [   SHCXX] src/dev/serial/serial.cc -> RISCV/dev/serial/serial.os
 [   SHCXX] src/dev/serial/simple.cc -> RISCV/dev/serial/simple.os
 [ TRACING]  -> RISCV/debug/Terminal.hh
 [ TRACING]  -> RISCV/debug/TerminalVerbose.hh
 [   SHCXX] src/dev/serial/terminal.cc -> RISCV/dev/serial/terminal.os
 [   SHCXX] src/dev/serial/uart.cc -> RISCV/dev/serial/uart.os
 [ TRACING]  -> RISCV/debug/Uart.hh
 [   SHCXX] src/dev/serial/uart8250.cc -> RISCV/dev/serial/uart8250.os
 [ TRACING]  -> RISCV/debug/Terminal.cc
 [   SHCXX] RISCV/debug/Terminal.cc -> .os
 [ TRACING]  -> RISCV/debug/TerminalVerbose.cc
 [ TRACING]  -> RISCV/debug/Uart.cc
 [   SHCXX] RISCV/debug/TerminalVerbose.cc -> .os
 [   SHCXX] RISCV/debug/Uart.cc -> .os
 [   SHCXX] RISCV/dev/i2c/I2C.py.cc -> .os
 [SO Param] m5.objects.I2C, I2CDevice -> RISCV/python/_m5/param_I2CDevice.cc
 [SO Param] m5.objects.I2C, I2CBus -> RISCV/python/_m5/param_I2CBus.cc
 [SO Param] m5.objects.I2C, I2CBus -> RISCV/params/I2CBus.hh
 [SO Param] m5.objects.I2C, I2CDevice -> RISCV/params/I2CDevice.hh
 [   SHCXX] RISCV/dev/pci/PciDevice.py.cc -> .os
 [SO Param] m5.objects.PciDevice, PciBar -> RISCV/python/_m5/param_PciBar.cc
 [SO Param] m5.objects.PciDevice, PciBarNone -> 
RISCV/python/_m5/param_PciBarNone.cc
 [SO Param] m5.objects.PciDevice, PciIoBar -> RISCV/python/_m5/param_PciIoBar.cc
 [   SHCXX] RISCV/python/_m5/param_I2CBus.cc -> .os
 [   SHCXX] RISCV/python/_m5/param_PciBar.cc -> .os
 [   SHCXX] RISCV/python/_m5/param_PciBarNone.cc -> .os
 [   SHCXX] RISCV/python/_m5/param_PciIoBar.cc -> .os
 [   SHCXX] src/dev/i2c/bus.cc -> RISCV/dev/i2c/bus.os
 [   SHCXX] RISCV/python/_m5/param_I2CDevice.cc -> .os
 [SO Param] m5.objects.PciDevice, PciLegacyIoBar -> 
RISCV/python/_m5/param_PciLegacyIoBar.cc
 [   SHCXX] RISCV/python/_m5/param_PciLegacyIoBar.cc -> .os
 [SO Param] m5.objects.PciDevice, PciMemBar -> 
RISCV/python/_m5/param_PciMemBar.cc
 [SO Param] m5.objects.PciDevice, PciMemUpperBar -> 
RISCV/python/_m5/param_PciMemUpperBar.cc
 [   SHCXX] RISCV/python/_m5/param_PciMemBar.cc -> .os
 [SO Param] m5.objects.PciDevice, PciDevice -> 
RISCV/python/_m5/param_PciDevice.cc
 [ TRACING]  -> RISCV/debug/PciDevice.hh
 [ TRACING]  -> RISCV/debug/PciDevice.cc
 [   SHCXX] src/dev/pci/device.cc -> RISCV/dev/pci/device.os
 [   SHCXX] RISCV/python/_m5/param_PciMemUpperBar.cc -> .os
 [   SHCXX] RISCV/debug/PciDevice.cc -> .os
 [   SHCXX] RISCV/python/_m5/param_PciDevice.cc -> .os
 [   SHCXX] RISCV/dev/pci/PciHost.py.cc -> .os
 [SO Param] m5.objects.PciHost, PciHost -> RISCV/python/_m5/param_PciHost.cc
 [SO Param] m5.objects.PciHost, GenericPciHost ->

[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Add "--no-duplicate-sources" option to SConstruct in util/

2023-04-13 Thread Hoa Nguyen (Gerrit) via gem5-dev 
Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69797?usp=email )



Change subject: scons: Add "--no-duplicate-sources" option to SConstruct in  
util/

..

scons: Add "--no-duplicate-sources" option to SConstruct in util/

Patch [1] caused building util/m5 to fail due to the flag was not
an option in the SConstruct file. It is apparently the case for other
programs in util/ relying on scons.

This patch fixes the above problem, and also adheres to the default
behavior introduced by [2].

[1] This patch introduced the "--no-duplicate-sources" flag to the
scons build in util/
https://gem5-review.googlesource.com/c/public/gem5/+/68518

[2] This patch enabled this flag by default,
https://gem5-review.googlesource.com/c/public/gem5/+/69717

Change-Id: I51376f7b3bf06438b7bc7ff84bc599deecac5bd1
Signed-off-by: Hoa Nguyen 
---
M util/m5/SConstruct
M util/statetrace/SConstruct
M util/tlm/SConstruct
3 files changed, 15 insertions(+), 0 deletions(-)



diff --git a/util/m5/SConstruct b/util/m5/SConstruct
index c2c4a50..7f07b94 100644
--- a/util/m5/SConstruct
+++ b/util/m5/SConstruct
@@ -49,6 +49,9 @@
 AddOption('--run-tests', dest='run_tests', action='store_true',
   help='Enable test output xml files as build targets.')
 AddOption('--verbose', dest='verbose', action='store_true')
+AddOption('--no-duplicate-sources', action='store_false', default=True,
+  dest='duplicate_sources',
+  help='Do not create symlinks to sources in the build directory')

 # Universal settings.
 if GetOption('debug_build'):
diff --git a/util/statetrace/SConstruct b/util/statetrace/SConstruct
index 945976e..2e1a631 100644
--- a/util/statetrace/SConstruct
+++ b/util/statetrace/SConstruct
@@ -57,6 +57,12 @@

 main['CXX'] = ARGUMENTS.get('CXX', main['CXX'])

+# An option not to link source files in the build directory.
+# Not enabled by default.
+AddOption('--no-duplicate-sources', action='store_false', default=True,
+  dest='duplicate_sources',
+  help='Do not create symlinks to sources in the build directory')
+
 for arch in arches:
 env = main.Clone()
 env['CXX'] = ARGUMENTS.get(arch.upper() + 'CXX', env['CXX'])
diff --git a/util/tlm/SConstruct b/util/tlm/SConstruct
index 6c65cfd..3f4abf8 100644
--- a/util/tlm/SConstruct
+++ b/util/tlm/SConstruct
@@ -80,6 +80,12 @@
 AddOption('--no-colors', dest='use_colors', action='store_false',
   help="Don't add color to abbreviated scons output")

+# An option not to link source files in the build directory.
+# Not enabled by default.
+AddOption('--no-duplicate-sources', action='store_false', default=True,
+  dest='duplicate_sources',
+  help='Do not create symlinks to sources in the build directory')
+
 env.SConsignFile('build/systemc/sconsign')
 SConscript(gem5_root + '/ext/systemc/SConscript',
variant_dir='build/systemc',

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I51376f7b3bf06438b7bc7ff84bc599deecac5bd1
Gerrit-Change-Number: 69797
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
Gerrit-MessageType: newchange
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[gem5-dev] [S] Change in gem5/gem5[develop]: configs: Add --exit-on-uart-eot flag to Arm baremetal.py config

2023-04-13 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69688?usp=email )


Change subject: configs: Add --exit-on-uart-eot flag to Arm baremetal.py  
config

..

configs: Add --exit-on-uart-eot flag to Arm baremetal.py config

Many benchmarks signal their termination by writing an EOT character
to the UART. This change adds an option to the Arm `baremetal.py`
example script to exit the simulation when an EOT character is
detected on any of the UARTs.

Change-Id: Ibfce9800c47090714258dbdbc5d6cee5ee6fb952
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69688
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M configs/example/arm/baremetal.py
1 file changed, 11 insertions(+), 1 deletion(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index ab24fd3..8ffd2b4 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2017,2019-2022 Arm Limited
+# Copyright (c) 2016-2017,2019-2023 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -157,6 +157,10 @@
 workload_class = workloads.workload_list.get(args.workload)
 system.workload = workload_class(object_file, system)

+if args.exit_on_uart_eot:
+for uart in system.realview.uart:
+uart.end_on_eot = True
+
 return system


@@ -254,6 +258,12 @@
 help="Destination for the Tarmac trace output. [Default:  
stdoutput]",

 )
 parser.add_argument(
+"--exit-on-uart-eot",
+action="store_true",
+help="Exit simulation if any of the UARTs receive an EOT. Many "
+"workloads signal termination by sending an EOT character.",
+)
+parser.add_argument(
 "--dtb-gen",
 action="store_true",
 help="Doesn't run simulation, it generates a DTB only",

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibfce9800c47090714258dbdbc5d6cee5ee6fb952
Gerrit-Change-Number: 69688
Gerrit-PatchSet: 4
Gerrit-Owner: Richard Cooper 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Add more detailed debug messages to GICv2.

2023-04-13 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69681?usp=email )


Change subject: arch-arm: Add more detailed debug messages to GICv2.
..

arch-arm: Add more detailed debug messages to GICv2.

Converted the generic DPRINTF messages for the GICv2 register reads
and writes (showing only the memory mapped address) to finer grained
DPRINTF messages showing the names of the mapped registers being
accessed.

This change is intended to make it easier to debug the GIC setup from
the gem5 debug trace.

Change-Id: Ic418b2ea8438fed6a5a810ebc0b686cd4c891cb0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69681
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
Reviewed-by: Giacomo Travaglini 
---
M src/dev/arm/gic_v2.cc
1 file changed, 80 insertions(+), 16 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc
index 7dc001e..e60daf0 100644
--- a/src/dev/arm/gic_v2.cc
+++ b/src/dev/arm/gic_v2.cc
@@ -199,8 +199,6 @@
 const Addr daddr = pkt->getAddr() - distRange.start();
 const ContextID ctx = pkt->req->contextId();

-DPRINTF(GIC, "gic distributor read register %#x\n", daddr);
-
 const uint32_t resp = readDistributor(ctx, daddr, pkt->getSize());

 switch (pkt->getSize()) {
@@ -228,50 +226,61 @@
 if (GICD_IGROUPR.contains(daddr)) {
 uint32_t ix = (daddr - GICD_IGROUPR.start()) >> 2;
 assert(ix < 32);
+DPRINTF(GIC, "gic distributor read GICD_IGROUPR%d (%#x)\n", ix,  
daddr);

 return getIntGroup(ctx, ix);
 }

 if (GICD_ISENABLER.contains(daddr)) {
 uint32_t ix = (daddr - GICD_ISENABLER.start()) >> 2;
 assert(ix < 32);
+DPRINTF(GIC, "gic distributor read GICD_ISENABLER%d (%#x)\n",
+ix, daddr);
 return getIntEnabled(ctx, ix);
 }

 if (GICD_ICENABLER.contains(daddr)) {
 uint32_t ix = (daddr - GICD_ICENABLER.start()) >> 2;
 assert(ix < 32);
+DPRINTF(GIC, "gic distributor read GICD_ICENABLER%d (%#x)\n",
+ix, daddr);
 return getIntEnabled(ctx, ix);
 }

 if (GICD_ISPENDR.contains(daddr)) {
 uint32_t ix = (daddr - GICD_ISPENDR.start()) >> 2;
 assert(ix < 32);
+DPRINTF(GIC, "gic distributor read GICD_ISPENDR%d (%#x)\n", ix,  
daddr);

 return getPendingInt(ctx, ix);
 }

 if (GICD_ICPENDR.contains(daddr)) {
 uint32_t ix = (daddr - GICD_ICPENDR.start()) >> 2;
 assert(ix < 32);
+DPRINTF(GIC, "gic distributor read GICD_ICPENDR%d (%#x)\n", ix,  
daddr);

 return getPendingInt(ctx, ix);
 }

 if (GICD_ISACTIVER.contains(daddr)) {
 uint32_t ix = (daddr - GICD_ISACTIVER.start()) >> 2;
 assert(ix < 32);
+DPRINTF(GIC, "gic distributor read GICD_ISACTIVER%d (%#x)\n",
+ix, daddr);
 return getActiveInt(ctx, ix);
 }

 if (GICD_ICACTIVER.contains(daddr)) {
 uint32_t ix = (daddr - GICD_ICACTIVER.start()) >> 2;
 assert(ix < 32);
+DPRINTF(GIC, "gic distributor read GICD_ICACTIVER%d (%#x)\n",
+ix, daddr);
 return getActiveInt(ctx, ix);
 }

 if (GICD_IPRIORITYR.contains(daddr)) {
 Addr int_num = daddr - GICD_IPRIORITYR.start();
 assert(int_num < INT_LINES_MAX);
-DPRINTF(Interrupt, "Reading interrupt priority at int# %#x \n",
-int_num);
+DPRINTF(GIC, "gic distributor read GICD_IPRIORITYR%d (%#x)\n",
+int_num, daddr);

 switch (resp_sz) {
   default: // will panic() after return to caller anyway
@@ -292,8 +301,8 @@

 if (GICD_ITARGETSR.contains(daddr)) {
 Addr int_num = daddr - GICD_ITARGETSR.start();
-DPRINTF(GIC, "Reading processor target register for int# %#x \n",
- int_num);
+DPRINTF(GIC, "gic distributor read GICD_ITARGETSR%d (%#x)\n",
+int_num, daddr);
 assert(int_num < INT_LINES_MAX);

 if (resp_sz == 1) {
@@ -310,30 +319,38 @@

 if (GICD_ICFGR.contains(daddr)) {
 uint32_t ix = (daddr - GICD_ICFGR.start()) >> 2;
+DPRINTF(GIC, "gic distributor read GICD_ICFGR%d (%#x)\n", ix,  
daddr);

 return getIntConfig(ctx, ix);
 }

 switch(daddr) {
   case GICD_CTLR:
+DPRINTF(GIC, "gic distributor read GICD_CTLR (%#x)\n", daddr);
 return enabled;
   case GICD_TYPER:
 /* The 0x100 is a made-up flag to show that gem5 extensions
  * are available,
  * write 0x200 to this register to enable it.  */
+DPRINTF(GIC, "gic distributor read GICD_TYPER (%#x)\n", daddr);
 return (((sys->threads.numRunning() - 1) << 5) |
 (itLines/INT_BITS_MAX -1) |

[gem5-dev] [M] Change in gem5/gem5[develop]: configs: Add Tarmac tracing option to the simple Arm configs

2023-04-13 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69684?usp=email )


 (

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: configs: Add Tarmac tracing option to the simple Arm  
configs

..

configs: Add Tarmac tracing option to the simple Arm configs

gem5 supports Tarmac trace generation for Arm simulations, but there
are no examples of how to use this feature.

This patch adds a `--tarmac-gen` option to three of the simple Arm
configs. Tarmac generation is useful for out-of-the-box users, and
this patch also provides an example of how to use the Tarmac
generation feature.

Change-Id: I0d3c523b5c0bb6d94de93bc502e4451622fb635d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69684
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M configs/example/arm/baremetal.py
M configs/example/arm/devices.py
M configs/example/arm/starter_fs.py
M configs/example/arm/starter_se.py
4 files changed, 106 insertions(+), 16 deletions(-)

Approvals:
  kokoro: Regressions pass
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved




diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index 0072c1d..4af1ff1 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2017,2019-2021 ARM Limited
+# Copyright (c) 2016-2017,2019-2022 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -123,7 +123,13 @@
 # Add CPU clusters to the system
 system.cpu_cluster = [
 devices.ArmCpuCluster(
-system, args.num_cores, args.cpu_freq, "1.0V",  
*cpu_types[args.cpu]

+system,
+args.num_cores,
+args.cpu_freq,
+"1.0V",
+*cpu_types[args.cpu],
+tarmac_gen=args.tarmac_gen,
+tarmac_dest=args.tarmac_dest,
 )
 ]

@@ -231,6 +237,17 @@
 parser.add_argument("--checkpoint", action="store_true")
 parser.add_argument("--restore", type=str, default=None)
 parser.add_argument(
+"--tarmac-gen",
+action="store_true",
+help="Write a Tarmac trace.",
+)
+parser.add_argument(
+"--tarmac-dest",
+choices=TarmacDump.vals,
+default="stdoutput",
+help="Destination for the Tarmac trace output. [Default:  
stdoutput]",

+)
+parser.add_argument(
 "--dtb-gen",
 action="store_true",
 help="Doesn't run simulation, it generates a DTB only",
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index 3f005a4..02574d2 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -106,6 +106,8 @@
 l1i_type,
 l1d_type,
 l2_type,
+tarmac_gen=False,
+tarmac_dest=None,
 ):
 super().__init__()
 self._cpu_type = cpu_type
@@ -122,6 +124,12 @@

 self.generate_cpus(cpu_type, num_cpus)

+for cpu in self.cpus:
+if tarmac_gen:
+cpu.tracer = TarmacTracer()
+if tarmac_dest is not None:
+cpu.tracer.outfile = tarmac_dest
+
 system.addCpuCluster(self)

 def addL1(self):
@@ -177,23 +185,54 @@


 class AtomicCluster(ArmCpuCluster):
-def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
-cpu_config = [
-ObjectList.cpu_list.get("AtomicSimpleCPU"),
-None,
-None,
-None,
-]
-super().__init__(system, num_cpus, cpu_clock, cpu_voltage,  
*cpu_config)

+def __init__(
+self,
+system,
+num_cpus,
+cpu_clock,
+cpu_voltage="1.0V",
+tarmac_gen=False,
+tarmac_dest=None,
+):
+super().__init__(
+system,
+num_cpus,
+cpu_clock,
+cpu_voltage,
+cpu_type=ObjectList.cpu_list.get("AtomicSimpleCPU"),
+l1i_type=None,
+l1d_type=None,
+l2_type=None,
+tarmac_gen=tarmac_gen,
+tarmac_dest=tarmac_dest,
+)

 def addL1(self):
 pass


 class KvmCluster(ArmCpuCluster):
-def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
-cpu_config = [ObjectList.cpu_list.get("ArmV8KvmCPU"), None, None,  
None]
-super().__init__(system, num_cpus, cpu_clock, cpu_voltage,  
*cpu_config)

+def __init__(
+self,
+system,
+num_cpus,
+cpu_clock,
+cpu_voltage="1.0V",
+tarmac_gen=False,
+tarmac_dest=None,
+):
+super().__init__(
+system,
+num_cpus,
+cpu_clock,
+

[gem5-dev] [S] Change in gem5/gem5[develop]: configs: Update Arm starter_se.py for new CpuCluster abstraction

2023-04-13 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69679?usp=email )


Change subject: configs: Update Arm starter_se.py for new CpuCluster  
abstraction

..

configs: Update Arm starter_se.py for new CpuCluster abstraction

Changeset [1] introduced a new CpuCluster abstraction. This requires
some changes to the Arm `starter_se.py` and `devices.py`
configurations to accommodate the new structure.

[1] https://gem5-review.googlesource.com/c/public/gem5/+/65891

Change-Id: I55fdd383c96286d179724e0f50771e2b5daaa6d7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69679
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M configs/example/arm/starter_se.py
1 file changed, 5 insertions(+), 5 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/arm/starter_se.py  
b/configs/example/arm/starter_se.py

index ccdbe4f..6b4dce9 100644
--- a/configs/example/arm/starter_se.py
+++ b/configs/example/arm/starter_se.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2017 ARM Limited
+# Copyright (c) 2016-2017, 2023 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -95,7 +95,7 @@

 # Add CPUs to the system. A cluster of CPUs typically have
 # private L1 caches and a shared L2 cache.
-self.cpu_cluster = devices.CpuCluster(
+self.cpu_cluster = devices.ArmCpuCluster(
 self, args.num_cores, args.cpu_freq, "1.2V",  
*cpu_types[args.cpu]

 )

@@ -114,11 +114,11 @@
 def numCpuClusters(self):
 return len(self._clusters)

-def addCpuCluster(self, cpu_cluster, num_cpus):
+def addCpuCluster(self, cpu_cluster):
 assert cpu_cluster not in self._clusters
-assert num_cpus > 0
+assert len(cpu_cluster) > 0
 self._clusters.append(cpu_cluster)
-self._num_cpus += num_cpus
+self._num_cpus += len(cpu_cluster)

 def numCpus(self):
 return self._num_cpus

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I55fdd383c96286d179724e0f50771e2b5daaa6d7
Gerrit-Change-Number: 69679
Gerrit-PatchSet: 2
Gerrit-Owner: Richard Cooper 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Add an option to use 64-bit PMU counters

2023-04-13 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69683?usp=email )


Change subject: arch-arm: Add an option to use 64-bit PMU counters
..

arch-arm: Add an option to use 64-bit PMU counters

Add support for 64-bit PMU counter registers (PMEVCNTR_EL0), as
specified in Armv8-A.

The counter registers are 32-bit by default, but 64-bit counters can
be chosen using the `ArmPMU.use64bitCounters` parameter.

Change-Id: Idb838a7438c7711438a7e078278bed21710049af
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69683
Reviewed-by: Giacomo Travaglini 
Tested-by: kokoro 
Maintainer: Giacomo Travaglini 
---
M src/arch/arm/ArmPMU.py
M src/arch/arm/pmu.cc
M src/arch/arm/pmu.hh
3 files changed, 22 insertions(+), 7 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/ArmPMU.py b/src/arch/arm/ArmPMU.py
index f21aaff..3eaed07 100644
--- a/src/arch/arm/ArmPMU.py
+++ b/src/arch/arm/ArmPMU.py
@@ -1,5 +1,5 @@
 # -*- mode:python -*-
-# Copyright (c) 2009-2014, 2017, 2020 ARM Limited
+# Copyright (c) 2009-2014, 2017, 2020, 2022 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -215,3 +215,11 @@
 platform = Param.Platform(Parent.any, "Platform this device is part  
of.")

 eventCounters = Param.Int(31, "Number of supported PMU counters")
 interrupt = Param.ArmInterruptPin("PMU interrupt")
+
+# 64-bit PMU event counters are officially supported when
+# Armv8.5-A FEAT_PMUv3p5 is implemented. This parameter is not a
+# full implementation of FEAT_PMUv3p5.
+use64bitCounters = Param.Bool(
+False,
+"Choose whether to use 64-bit or " "32-bit PMEVCNTR_EL0  
registers.",

+)
diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc
index f0ab978..89dc2c8 100644
--- a/src/arch/arm/pmu.cc
+++ b/src/arch/arm/pmu.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2014, 2017-2019 ARM Limited
+ * Copyright (c) 2011-2014, 2017-2019, 2022 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -56,12 +56,13 @@

 PMU::PMU(const ArmPMUParams )
 : SimObject(p), BaseISADevice(),
+  use64bitCounters(p.use64bitCounters),
   reg_pmcnten(0), reg_pmcr(0),
   reg_pmselr(0), reg_pminten(0), reg_pmovsr(0),
   reg_pmceid0(0),reg_pmceid1(0),
   clock_remainder(0),
   maximumCounterCount(p.eventCounters),
-  cycleCounter(*this, maximumCounterCount),
+  cycleCounter(*this, maximumCounterCount, p.use64bitCounters),
   cycleCounterEventId(p.cycleEventId),
   swIncrementEvent(nullptr),
   reg_pmcr_conf(0),
@@ -175,7 +176,7 @@
 // at this stage all probe configurations are done
 // counters can be configured
 for (uint32_t index = 0; index < maximumCounterCount-1; index++) {
-counters.emplace_back(*this, index);
+counters.emplace_back(*this, index, use64bitCounters);
 }

 std::shared_ptr event = getEvent(cycleCounterEventId);
@@ -685,6 +686,7 @@
 {
 DPRINTF(Checkpoint, "Serializing Arm PMU\n");

+SERIALIZE_SCALAR(use64bitCounters);
 SERIALIZE_SCALAR(reg_pmcr);
 SERIALIZE_SCALAR(reg_pmcnten);
 SERIALIZE_SCALAR(reg_pmselr);
@@ -705,6 +707,7 @@
 {
 DPRINTF(Checkpoint, "Unserializing Arm PMU\n");

+UNSERIALIZE_SCALAR(use64bitCounters);
 UNSERIALIZE_SCALAR(reg_pmcr);
 UNSERIALIZE_SCALAR(reg_pmcnten);
 UNSERIALIZE_SCALAR(reg_pmselr);
diff --git a/src/arch/arm/pmu.hh b/src/arch/arm/pmu.hh
index 46b10d0..ec60c6b 100644
--- a/src/arch/arm/pmu.hh
+++ b/src/arch/arm/pmu.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2014, 2017-2018 ARM Limited
+ * Copyright (c) 2011-2014, 2017-2018, 2022 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -413,9 +413,10 @@
 /** State of a counter within the PMU. **/
 struct CounterState : public Serializable
 {
-CounterState(PMU , uint64_t counter_id)
+CounterState(PMU , uint64_t counter_id,
+ const bool is_64_bit)
 : eventId(0), filter(0), enabled(false),
-  overflow64(false), sourceEvent(nullptr),
+  overflow64(is_64_bit), sourceEvent(nullptr),
   counterId(counter_id), value(0), resetValue(false),
   pmu(pmuReference) {}

@@ -572,6 +573,9 @@
 void updateAllCounters();

   protected: /* State that needs to be serialized */
+/** Determine whether to use 64-bit or 32-bit counters. */
+bool use64bitCounters;
+
 /** Performance Monitor Count Enable Register */
 RegVal reg_pmcnten;


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[gem5-dev] [XS] Change in gem5/gem5[develop]: dev-arm: Fix writes to Arm GICv2 GICD_IGROUPRn

2023-04-13 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69682?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: dev-arm: Fix writes to Arm GICv2 GICD_IGROUPRn
..

dev-arm: Fix writes to Arm GICv2 GICD_IGROUPRn

Writes to the GICD_IGROUPRn registers are currently applied using the
`|=` operator, allowing bits to be set but not cleared. According to
the specification [1] this register should allow direct writes.

This patch changes the logic to write the new value directly to the
register.

[1] https://developer.arm.com/documentation/ihi0048/latest/

Change-Id: Ia5f17d05530263d7e918ff33576daaf8165c25c2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69682
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/dev/arm/gic_v2.cc
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc
index e60daf0..b42b49c 100644
--- a/src/dev/arm/gic_v2.cc
+++ b/src/dev/arm/gic_v2.cc
@@ -509,7 +509,7 @@
 DPRINTF(GIC,
 "gic distributor write GICD_IGROUPR%d (%#x) size %#x value %#x  
\n",

 ix, daddr, data_sz, data);
-getIntGroup(ctx, ix) |= data;
+getIntGroup(ctx, ix) = data;
 return;
 }


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia5f17d05530263d7e918ff33576daaf8165c25c2
Gerrit-Change-Number: 69682
Gerrit-PatchSet: 3
Gerrit-Owner: Richard Cooper 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [XS] Change in gem5/gem5[develop]: configs: Add the O3 CPU as an option to baremetal.py

2023-04-13 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69686?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: configs: Add the O3 CPU as an option to baremetal.py
..

configs: Add the O3 CPU as an option to baremetal.py

Adds the O3_ARM_v7a CPU model as an extra option for the `--cpu-type`
to `configs/example/arm/baremetal.py`.

Change-Id: I717b168945bec22fb5ae17e37c2854df844bcb4f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69686
Tested-by: kokoro 
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
---
M configs/example/arm/baremetal.py
1 file changed, 7 insertions(+), 0 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index 345596d..9caab9d 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -52,6 +52,7 @@
 from common import MemConfig
 from common import ObjectList
 from common.cores.arm import HPI
+from common.cores.arm import O3_ARM_v7a

 import devices
 import workloads
@@ -63,6 +64,12 @@
 "atomic": (AtomicSimpleCPU, None, None, None),
 "minor": (MinorCPU, devices.L1I, devices.L1D, devices.L2),
 "hpi": (HPI.HPI, HPI.HPI_ICache, HPI.HPI_DCache, HPI.HPI_L2),
+"o3": (
+O3_ARM_v7a.O3_ARM_v7a_3,
+O3_ARM_v7a.O3_ARM_v7a_ICache,
+O3_ARM_v7a.O3_ARM_v7a_DCache,
+O3_ARM_v7a.O3_ARM_v7aL2,
+),
 }



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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I717b168945bec22fb5ae17e37c2854df844bcb4f
Gerrit-Change-Number: 69686
Gerrit-PatchSet: 4
Gerrit-Owner: Richard Cooper 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Fix formatting of v8 Tarmac Register records

2023-04-13 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69680?usp=email )


Change subject: arch-arm: Fix formatting of v8 Tarmac Register records
..

arch-arm: Fix formatting of v8 Tarmac Register records

The Tarmac v8 Register ("R") record serialisation formats the
underlying 64-bit storage using a format string field width specifier.
This sets a minimum number of hex characters for the value, rather
than a maximum number of characters.

Because of this, when formatting a narrowed view of a larger
register (e.g. the 32-bit w0 view of the 64-bit x0 register), if any
of the upper bits in the underlying storage are set, then the number
of hex characters used will be the minimum number required to
represent the full value. This could result in irregular formatting,
for example an odd number of hex characters.

This irregular formatting can cause parsing warnings or failures in
some Tarmac tools, for example the Arm Tarmac Trace Utilities [1].

This patch modifies the "R" record formatting to first mask off the
upper bits of the value in the underlying storage to ensure that the
correct number of hex characters are used for the size of the register
being serialised.

[1] https://github.com/ARM-software/tarmac-trace-utilities

Change-Id: Idbd80553d3bcdb56fa9e48440ab7d4dff073
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69680
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/tracers/tarmac_record_v8.cc
1 file changed, 4 insertions(+), 3 deletions(-)

Approvals:
  kokoro: Regressions pass
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved




diff --git a/src/arch/arm/tracers/tarmac_record_v8.cc  
b/src/arch/arm/tracers/tarmac_record_v8.cc

index 29606c3..a3850b3 100644
--- a/src/arch/arm/tracers/tarmac_record_v8.cc
+++ b/src/arch/arm/tracers/tarmac_record_v8.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2019 ARM Limited
+ * Copyright (c) 2017-2019, 2022 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -293,8 +293,9 @@
 TarmacTracerRecordV8::TraceRegEntryV8::formatReg() const
 {
 if (regWidth <= 64) {
-// Register width is < 64 bit (scalar register).
-return csprintf("%0*x", regWidth / 4, values[Lo]);
+// Register width is <= 64 bit (scalar register).
+const auto regValue = values[Lo] & mask(regWidth);
+return csprintf("%0*x", regWidth / 4, regValue);
 } else {

 // Register width is > 64 bit (vector).  Iterate over every vector

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idbd80553d3bcdb56fa9e48440ab7d4dff073
Gerrit-Change-Number: 69680
Gerrit-PatchSet: 2
Gerrit-Owner: Richard Cooper 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [XS] Change in gem5/gem5[develop]: configs: Make the configuration of the gicv4 parameter robust

2023-04-13 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69685?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: configs: Make the configuration of the gicv4 parameter  
robust

..

configs: Make the configuration of the gicv4 parameter robust

Only the GICv3 model has a `gicv4` parameter, causing the current
`baremetal.py` config to throw an exception when used with the
VExpress_GEM5_V1 platform containing a GICv2.

This patch checks for the existence of the `gicv4` parameter, allowing
all VExpress platforms to be used.

Change-Id: I72667a9caee64fa497bda516217cd424050eb242
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69685
Tested-by: kokoro 
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
---
M configs/example/arm/baremetal.py
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index 4af1ff1..345596d 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -142,7 +142,8 @@
 system.auto_reset_addr = True

 # Using GICv3
-system.realview.gic.gicv4 = False
+if hasattr(system.realview.gic, "gicv4"):
+system.realview.gic.gicv4 = False

 system.highest_el_is_64 = True


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I72667a9caee64fa497bda516217cd424050eb242
Gerrit-Change-Number: 69685
Gerrit-PatchSet: 4
Gerrit-Owner: Richard Cooper 
Gerrit-Reviewer: Giacomo Travaglini 
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[gem5-dev] [S] Change in gem5/gem5[develop]: configs: Update Arm simple configs to enable --interactive option

2023-04-13 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69687?usp=email )


 (

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.
 )Change subject: configs: Update Arm simple configs to enable  
--interactive option

..

configs: Update Arm simple configs to enable --interactive option

Removed the calls to `sys.exit()` from the Arm simple configs. These
calls terminate gem5's embedded Python interpreter and gem5 at the end
of the config script, preventing gem5 from dropping into the
interactive IPython shell when the `--interactive` option has been
specified.

Change-Id: I0c350b0d107f297691255361d25c566c889f9469
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69687
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M configs/example/arm/baremetal.py
M configs/example/arm/starter_fs.py
M configs/example/arm/starter_se.py
3 files changed, 3 insertions(+), 8 deletions(-)

Approvals:
  kokoro: Regressions pass
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved




diff --git a/configs/example/arm/baremetal.py  
b/configs/example/arm/baremetal.py

index 9caab9d..ab24fd3 100644
--- a/configs/example/arm/baremetal.py
+++ b/configs/example/arm/baremetal.py
@@ -174,11 +174,9 @@
 m5.checkpoint(os.path.join(cpt_dir))
 print("Checkpoint done.")
 else:
-print(exit_msg, " @ ", m5.curTick())
+print(f"{exit_msg} ({event.getCode()}) @ {m5.curTick()}")
 break

-sys.exit(event.getCode())
-

 def main():
 parser = argparse.ArgumentParser(epilog=__doc__)
diff --git a/configs/example/arm/starter_fs.py  
b/configs/example/arm/starter_fs.py

index cc5f63f..ebed188 100644
--- a/configs/example/arm/starter_fs.py
+++ b/configs/example/arm/starter_fs.py
@@ -194,11 +194,9 @@
 m5.checkpoint(os.path.join(cpt_dir))
 print("Checkpoint done.")
 else:
-print(exit_msg, " @ ", m5.curTick())
+print(f"{exit_msg} ({event.getCode()}) @ {m5.curTick()}")
 break

-sys.exit(event.getCode())
-

 def main():
 parser = argparse.ArgumentParser(epilog=__doc__)
diff --git a/configs/example/arm/starter_se.py  
b/configs/example/arm/starter_se.py

index 33514c7..f21f399 100644
--- a/configs/example/arm/starter_se.py
+++ b/configs/example/arm/starter_se.py
@@ -257,8 +257,7 @@
 # Print the reason for the simulation exit. Some exit codes are
 # requests for service (e.g., checkpoints) from the simulation
 # script. We'll just ignore them here and exit.
-print(event.getCause(), " @ ", m5.curTick())
-sys.exit(event.getCode())
+print(f"{event.getCause()} ({event.getCode()}) @ {m5.curTick()}")


 if __name__ == "__m5_main__":

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Gerrit-Change-Number: 69687
Gerrit-PatchSet: 4
Gerrit-Owner: Richard Cooper 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
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Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [XS] Change in gem5/gem5[develop]: cpu: Add CpuCluster method to allow querying the number of CPUs.

2023-04-13 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69678?usp=email )


Change subject: cpu: Add CpuCluster method to allow querying the number of  
CPUs.

..

cpu: Add CpuCluster method to allow querying the number of CPUs.

Add a `__len__` method to `CpuCluster` to allow clients to query the
number of CPUs.

Change-Id: I6fe680423ed6fc301faaf75b8685b080a4774fef
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69678
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M src/cpu/CpuCluster.py
1 file changed, 4 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/cpu/CpuCluster.py b/src/cpu/CpuCluster.py
index 31fdc49..42a7112 100644
--- a/src/cpu/CpuCluster.py
+++ b/src/cpu/CpuCluster.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2022 Arm Limited
+# Copyright (c) 2022-2023 Arm Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -51,6 +51,9 @@
 def __iter__(self):
 return iter(self.cpus)

+def __len__(self):
+return len(self.cpus)
+
 def generate_cpus(self, cpu_type: "BaseCPU", num_cpus: int):
 """
 Instantiates the cpus within the cluster provided

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Gerrit-Owner: Richard Cooper 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Daniel Carvalho 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Build failed in Jenkins: compiler-checks #574

2023-04-13 Thread jenkins-no-reply--- via gem5-dev 
See 


Changes:

[gabe.black] base: fatal() if a socket path doesn't fit in sockaddr_un.sun_path.

[rogerycchang] arch-riscv: Insert symbol table of bootloader into debug symbol 
table


--
[...truncated 1.03 KB...]
 > git checkout -f 6c4f405669cf1f8289d7f86284ba66e8371de68d # timeout=10
Commit message: "arch-riscv: Insert symbol table of bootloader into debug 
symbol table in bare metal workload"
 > git rev-list --no-walk 716c154b51a24c7af0ad2334c9337d9fc7f8a5c0 # timeout=10
[Checks API] No suitable checks publisher found.
[compiler-checks] $ /bin/sh -xe /tmp/jenkins7581752882131052549.sh
+ ./tests/compiler-tests.sh -j 16
Starting build tests with 'gcc-version-12'...
'gcc-version-12' was found in the comprehensive tests. All ISAs will be built.
  * Building target 'X86.opt' with 'gcc-version-12'...
Done.
  * Building target 'X86.fast' with 'gcc-version-12'...
Done.
  * Building target 'X86_MI_example.opt' with 'gcc-version-12'...
Done.
  * Building target 'X86_MI_example.fast' with 'gcc-version-12'...
Done.
  * Building target 'ALL.opt' with 'gcc-version-12'...
Done.
  * Building target 'ALL.fast' with 'gcc-version-12'...
Done.
  * Building target 'ARM_MESI_Three_Level_HTM.opt' with 'gcc-version-12'...
Done.
  * Building target 'ARM_MESI_Three_Level_HTM.fast' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MOESI_hammer.opt' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MOESI_hammer.fast' with 'gcc-version-12'...
Done.
  * Building target 'GCN3_X86.opt' with 'gcc-version-12'...
Done.
  * Building target 'GCN3_X86.fast' with 'gcc-version-12'...
Done.
  * Building target 'NULL.opt' with 'gcc-version-12'...
Done.
  * Building target 'NULL.fast' with 'gcc-version-12'...
Done.
  * Building target 'MIPS.opt' with 'gcc-version-12'...
Done.
  * Building target 'MIPS.fast' with 'gcc-version-12'...
Done.
  * Building target 'ARM.opt' with 'gcc-version-12'...
Done.
  * Building target 'ARM.fast' with 'gcc-version-12'...
Done.
  * Building target 'X86_MOESI_AMD_Base.opt' with 'gcc-version-12'...
Done.
  * Building target 'X86_MOESI_AMD_Base.fast' with 'gcc-version-12'...
Done.
  * Building target 'RISCV.opt' with 'gcc-version-12'...
Done.
  * Building target 'RISCV.fast' with 'gcc-version-12'...
Done.
  * Building target 'Garnet_standalone.opt' with 'gcc-version-12'...
Done.
  * Building target 'Garnet_standalone.fast' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MESI_Two_Level.opt' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MESI_Two_Level.fast' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MOESI_CMP_directory.opt' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MOESI_CMP_directory.fast' with 'gcc-version-12'...
Done.
  * Building target 'SPARC.opt' with 'gcc-version-12'...
Done.
  * Building target 'SPARC.fast' with 'gcc-version-12'...
Done.
  * Building target 'ARM_MOESI_hammer.opt' with 'gcc-version-12'...
Done.
  * Building target 'ARM_MOESI_hammer.fast' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MOESI_CMP_token.opt' with 'gcc-version-12'...
Done.
  * Building target 'NULL_MOESI_CMP_token.fast' with 'gcc-version-12'...
Done.
  * Building target 'POWER.opt' with 'gcc-version-12'...
Done.
  * Building target 'POWER.fast' with 'gcc-version-12'...
Done.
  * Building target 'ARM_MESI_Three_Level.opt' with 'gcc-version-12'...
Done.
  * Building target 'ARM_MESI_Three_Level.fast' with 'gcc-version-12'...
Done.
Starting build tests with 'gcc-version-11'...
  * Building target 'ARM_MESI_Three_Level.opt' with 'gcc-version-11'...
Done.
  * Building target 'ARM_MESI_Three_Level.fast' with 'gcc-version-11'...
Done.
Starting build tests with 'gcc-version-10'...
  * Building target 'X86_MOESI_AMD_Base.opt' with 'gcc-version-10'...
Done.
  * Building target 'X86_MOESI_AMD_Base.fast' with 'gcc-version-10'...
Done.
Starting build tests with 'gcc-version-9'...
  * Building target 'ARM_MOESI_hammer.opt' with 'gcc-version-9'...
Done.
  * Building target 'ARM_MOESI_hammer.fast' with 'gcc-version-9'...
Done.
Starting build tests with 'gcc-version-8'...
  * Building target 'SPARC.opt' with 'gcc-version-8'...
Done.
  * Building target 'SPARC.fast' with 'gcc-version-8'...
Done.
Starting build tests with 'gcc-version-7'...
  * Building target 'ARM.opt' with 'gcc-version-7'...
  ! Failed with exit code 2.
  * Building target 'ARM.fast' with 'gcc-version-7'...
  ! Failed with exit code 2.
Starting build tests with 'clang-version-14'...
'clang-version-14' was found in the comprehensive tests. All ISAs will be built.
  * Building target 'ARM_MOESI_hammer.opt' with 'clang-version-14'...
Done.
  * Building target 'ARM_MOESI_hammer.fast' with 'clang-version-14'...

[gem5-dev] [S] Change in gem5/gem5[develop]: base: Use include for clang 6-9

2023-04-13 Thread Melissa Jost (Gerrit) via gem5-dev 
Melissa Jost has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69778?usp=email )



Change subject: base: Use  include for clang 6-9
..

base: Use  include for clang 6-9

This change addresses an error in the compiler tests:
https://jenkins.gem5.org/job/compiler-checks/573/

For clang versions 6 through 9, in order to use the
"filesystem" module, you must include the experimental
namespace.  In all newer versions, you can use the
"filesystem" module as is.

Because of this, include guards to handle this. They include
"" for the older clang versions and
the "" for all other versions.

Change-Id: I8fb8d4eaa33f3edc29b7626f44b82ee66ffe72be
---
M src/base/socket.cc
M src/mem/shared_memory_server.cc
2 files changed, 23 insertions(+), 6 deletions(-)



diff --git a/src/base/socket.cc b/src/base/socket.cc
index 62f2071..8243bc0 100644
--- a/src/base/socket.cc
+++ b/src/base/socket.cc
@@ -40,13 +40,16 @@

 #include 

-#if (defined(__GNUC__) && (__GNUC__ >= 8)) || defined(__clang__)
+#if (defined(__GNUC__) && (__GNUC__ >= 8)) || \
+(defined(__clang__) && (__GNUC__ >= 9))
 #include 
 #else
-// This is only reachable if we're using GCC 7 (note: gem5 does not  
support

-// GCC versions older than GCC 7 as they do not support the C++17
-// standard).
-// If we're using GCC 7, we need to use .
+// This is only reachable if we're using GCC 7 or clang versions 6
+// through 9 (note: gem5 does not support GCC versions older than
+// GCC 7 or clang versions older than clang 6.0 as they do not
+// support the C++17 standard).
+// If we're using GCC 7 or clang versions 6 through 9, we need to use
+// .
 #include 
 namespace std {
 namespace filesystem = experimental::filesystem;
diff --git a/src/mem/shared_memory_server.cc  
b/src/mem/shared_memory_server.cc

index 3e49164..8f66217 100644
--- a/src/mem/shared_memory_server.cc
+++ b/src/mem/shared_memory_server.cc
@@ -39,7 +39,21 @@
 #include 
 #include 
 #include 
-#include 
+#if (defined(__GNUC__) && (__GNUC__ >= 8)) || \
+(defined(__clang__) && (__GNUC__ >= 9))
+#include 
+#else
+// This is only reachable if we're using GCC 7 or clang versions 6
+// through 9 (note: gem5 does not support GCC versions older than
+// GCC 7 or clang versions older than clang 6.0 as they do not
+// support the C++17 standard).
+// If we're using GCC 7 or clang versions 6 through 9, we need to use
+// .
+#include 
+namespace std {
+namespace filesystem = experimental::filesystem;
+}
+#endif

 #include "base/logging.hh"
 #include "base/output.hh"

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[gem5-dev] [S] Change in gem5/gem5[develop]: scons: Add stdc++fs and libc++experimental for clang LIBS env

2023-04-13 Thread Melissa Jost (Gerrit) via gem5-dev 
Melissa Jost has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69777?usp=email )



Change subject: scons: Add stdc++fs and libc++experimental for clang LIBS  
env

..

scons: Add stdc++fs and libc++experimental for clang LIBS env

This change fixes a failure in the compiler tests:
https://jenkins.gem5.org/job/compiler-checks/573/

These tests were failing due to the use of `std::filesystem`, which
requires 'libc++experimental' to be linked for versions of clang
6 and older, and 'stdc++fs' to be linked for clang versions 7
through 9.

Change-Id: I4fa03923e8dc616046dead939c77d49b301de36b
---
M SConstruct
1 file changed, 17 insertions(+), 0 deletions(-)



diff --git a/SConstruct b/SConstruct
index e91e700..55d36ec 100755
--- a/SConstruct
+++ b/SConstruct
@@ -511,6 +511,23 @@

 env.Append(TCMALLOC_CCFLAGS=['-fno-builtin'])

+if compareVersions(env['CXXVERSION'], "10") < 0:
+# `libstdc++fs`` must be explicitly linked for  
`std::filesystem``

+# in clang versions 7 through 9. For clang version 6,
+# `libc++experimental`` must be explicitly linked instead.
+# As of clang version 10, this is not required.
+#
+# In addition, for clang versions 6 through 9,  the
+# `std::filesystem` is under the `experimental`
+# namespace(`std::experimental::filesystem`).
+#
+# Note: gem5 does not support clang versions < 6.
+if compareVersions(env['CXXVERSION'], "6") < 0:
+env.Append(LIBS=['libc++experimental'])
+else:
+env.Append(LIBS=['stdc++fs'])
+
+
 # On Mac OS X/Darwin we need to also use libc++ (part of XCode) as
 # opposed to libstdc++, as the later is dated.
 if sys.platform == "darwin":

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[gem5-dev] [XS] Change in gem5/gem5[develop]: scons: Fix "no-duplicate-sources" to include .hh when not set

2023-04-13 Thread Bobby Bruce (Gerrit) via gem5-dev 
Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/69717?usp=email )


Change subject: scons: Fix "no-duplicate-sources" to include .hh when not  
set

..

scons: Fix "no-duplicate-sources" to include .hh when not set

A flag, introduced in this patch:
https://gem5-review.googlesource.com/c/public/gem5/+/68518
allowed users to pass "no-duplicate-sources" to a gem5 compilation to
not symlink sources in the build directory.

In this patch "src" was added as a shared top-level header directory.
This means that the header files are not copied to the "build" directory
whether or not "no-duplicate-sources" is set.

This patch ensures the "src" directory is only added as a shared
top-level headers directory in the case where "no-duplicate-sources" is
set.

In addition, the "duplicate_sources" parameter (the destination for the
"no-duplicate-sources") was "None" by default, and only set to False
when the flag was used. `default=True` has been added so
"duplicate_sources" can be used as a boolean.

This bug was a cause of a Nightly build error:
https://jenkins.gem5.org/job/nightly/570

In this error, building ext/sst resulted in an error as the Makefile
depends on adding "build/RISCV" to the include path. Without the header
files in the "build" directory, building SST failed. Though, ext/stt
should probably not be using header files in the "build/RISCV"
directory. This will be fixed in another change.

Change-Id: I786486a177fe17a67f3b939c539eecdcbfcaeaf2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69717
Reviewed-by: Bobby Bruce 
Maintainer: Bobby Bruce 
Tested-by: kokoro 
---
M SConstruct
1 file changed, 3 insertions(+), 2 deletions(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/SConstruct b/SConstruct
index e91e700..7e8f177 100755
--- a/SConstruct
+++ b/SConstruct
@@ -145,7 +145,7 @@
   help='Enable support for the gprof profiler')
 AddOption('--pprof', action='store_true',
   help='Enable support for the pprof profiler')
-AddOption('--no-duplicate-sources', action='store_false',
+AddOption('--no-duplicate-sources', action='store_false', default=True,
   dest='duplicate_sources',
   help='Do not create symlinks to sources in the build directory')

@@ -267,7 +267,8 @@

 # Add shared top-level headers
 main.Prepend(CPPPATH=Dir('include'))
-main.Prepend(CPPPATH=Dir('src'))
+if not GetOption('duplicate_sources'):
+main.Prepend(CPPPATH=Dir('src'))


 

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Gerrit-Change-Id: I786486a177fe17a67f3b939c539eecdcbfcaeaf2
Gerrit-Change-Number: 69717
Gerrit-PatchSet: 4
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Alex Richardson 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Build failed in Jenkins: weekly #117

2023-04-13 Thread jenkins-no-reply--- via gem5-dev 
See 

Changes:

[vramadas] dev-amdgpu: Added PM4MapQueues to GPUFS checkpoint

[vramadas] dev-amdgpu: Add GART translations to GPUFS checkpoint

[Bobby R. Bruce] arch-sparc: Rewrite unused array in tgt_stat64 for mac

[humzajahangirikram] stdlib: Small fix in stdlib spec2006 script

[mattdsinclair] mem-ruby: fix whitespacing errors in RubySystem

[gabe.black] base: Abstract the AF_INET-ness out of ListenSocket.

[alexrichardson] scons: allow building without duplicating source files

[gabe.black] util: Make m5term able to connect to unix domain sockets.


--
[...truncated 331.15 KB...]
 [ CXX] ALL/python/_m5/param_PciMemUpperBar.cc -> .o
 [ CXX] ALL/python/_m5/param_PciDevice.cc -> .o
 [ TRACING]  -> ALL/debug/PciDevice.hh
 [ TRACING]  -> ALL/debug/PciDevice.cc
 [ CXX] ALL/dev/pci/PciHost.py.cc -> .o
 [ CXX] ALL/debug/PciDevice.cc -> .o
 [ CXX] src/dev/pci/device.cc -> ALL/dev/pci/device.o
 [SO Param] m5.objects.PciHost, PciHost -> ALL/python/_m5/param_PciHost.cc
 [ CXX] ALL/python/_m5/param_PciHost.cc -> .o
 [SO Param] m5.objects.PciHost, GenericPciHost -> 
ALL/python/_m5/param_GenericPciHost.cc
 [ CXX] ALL/python/_m5/param_GenericPciHost.cc -> .o
 [ TRACING]  -> ALL/debug/PciHost.hh
 [ CXX] src/dev/pci/host.cc -> ALL/dev/pci/host.o
 [ TRACING]  -> ALL/debug/PciHost.cc
 [ CXX] ALL/debug/PciHost.cc -> .o
 [ CXX] ALL/dev/pci/CopyEngine.py.cc -> .o
 [SO Param] m5.objects.CopyEngine, CopyEngine -> 
ALL/python/_m5/param_CopyEngine.cc
 [SO Param] m5.objects.CopyEngine, CopyEngine -> ALL/params/CopyEngine.hh
 [ TRACING]  -> ALL/debug/DMACopyEngine.hh
 [ TRACING]  -> ALL/debug/DMACopyEngine.cc
 [ CXX] ALL/dev/lupio/LupioBLK.py.cc -> .o
 [ CXX] ALL/debug/DMACopyEngine.cc -> .o
 [ CXX] src/dev/pci/copy_engine.cc -> ALL/dev/pci/copy_engine.o
 [ CXX] ALL/python/_m5/param_CopyEngine.cc -> .o
 [SO Param] m5.objects.LupioBLK, LupioBLK -> ALL/python/_m5/param_LupioBLK.cc
 [ CXX] ALL/dev/lupio/LupioIPI.py.cc -> .o
 [SO Param] m5.objects.LupioBLK, LupioBLK -> ALL/params/LupioBLK.hh
 [ TRACING]  -> ALL/debug/LupioBLK.hh
 [ CXX] ALL/python/_m5/param_LupioBLK.cc -> .o
 [SO Param] m5.objects.LupioIPI, LupioIPI -> ALL/python/_m5/param_LupioIPI.cc
 [SO Param] m5.objects.LupioIPI, LupioIPI -> ALL/params/LupioIPI.hh
 [ CXX] ALL/python/_m5/param_LupioIPI.cc -> .o
 [ CXX] ALL/dev/lupio/LupioPIC.py.cc -> .o
 [SO Param] m5.objects.LupioPIC, LupioPIC -> ALL/python/_m5/param_LupioPIC.cc
 [ CXX] ALL/dev/lupio/LupioRNG.py.cc -> .o
 [ CXX] ALL/python/_m5/param_LupioPIC.cc -> .o
 [SO Param] m5.objects.LupioRNG, LupioRNG -> ALL/python/_m5/param_LupioRNG.cc
 [SO Param] m5.objects.LupioRNG, LupioRNG -> ALL/params/LupioRNG.hh
 [ TRACING]  -> ALL/debug/LupioRNG.hh
 [ CXX] ALL/python/_m5/param_LupioRNG.cc -> .o
 [ CXX] ALL/dev/lupio/LupioRTC.py.cc -> .o
 [SO Param] m5.objects.LupioRTC, LupioRTC -> ALL/python/_m5/param_LupioRTC.cc
 [ CXX] ALL/dev/lupio/LupioTMR.py.cc -> .o
 [SO Param] m5.objects.LupioRTC, LupioRTC -> ALL/params/LupioRTC.hh
 [ TRACING]  -> ALL/debug/LupioRTC.hh
 [SO Param] m5.objects.LupioTMR, LupioTMR -> ALL/python/_m5/param_LupioTMR.cc
 [ CXX] ALL/python/_m5/param_LupioRTC.cc -> .o
 [SO Param] m5.objects.LupioTMR, LupioTMR -> ALL/params/LupioTMR.hh
 [ CXX] ALL/python/_m5/param_LupioTMR.cc -> .o
 [ CXX] ALL/dev/lupio/LupioTTY.py.cc -> .o
 [SO Param] m5.objects.LupioTTY, LupioTTY -> ALL/python/_m5/param_LupioTTY.cc
 [ CXX] ALL/dev/lupio/LupioSYS.py.cc -> .o
 [SO Param] m5.objects.LupioTTY, LupioTTY -> ALL/params/LupioTTY.hh
 [ CXX] ALL/python/_m5/param_LupioTTY.cc -> .o
 [SO Param] m5.objects.LupioSYS, LupioSYS -> ALL/python/_m5/param_LupioSYS.cc
 [SO Param] m5.objects.LupioSYS, LupioSYS -> ALL/params/LupioSYS.hh
 [ TRACING]  -> ALL/debug/LupioSYS.hh
 [ TRACING]  -> ALL/debug/LupioBLK.cc
 [ CXX] ALL/debug/LupioBLK.cc -> .o
 [ CXX] ALL/python/_m5/param_LupioSYS.cc -> .o
 [ TRACING]  -> ALL/debug/LupioIPI.cc
 [ TRACING]  -> ALL/debug/LupioIPI.hh
 [ CXX] ALL/debug/LupioIPI.cc -> .o
 [ TRACING]  -> ALL/debug/LupioPIC.cc
 [ TRACING]  -> ALL/debug/LupioPIC.hh
 [ CXX] ALL/debug/LupioPIC.cc -> .o
 [ TRACING]  -> ALL/debug/LupioRNG.cc
 [ CXX] ALL/debug/LupioRNG.cc -> .o
 [ TRACING]  -> ALL/debug/LupioRTC.cc
 [ CXX] ALL/debug/LupioRTC.cc -> .o
 [ TRACING]  -> ALL/debug/LupioTMR.cc
 [ TRACING]  -> ALL/debug/LupioTMR.hh
 [ CXX] ALL/debug/LupioTMR.cc -> .o
 [ TRACING]  -> ALL/debug/LupioTTY.cc
 [ TRACING]  -> ALL/debug/LupioTTY.hh
 [ CXX] ALL/debug/LupioTTY.cc -> .o
 [ TRACING]  -> ALL/debug/LupioSYS.cc
 [ CXX] ALL/debug/LupioSYS.cc -> .o
 [ CXX] src/dev/lupio/lupio_blk.cc -> ALL/dev/lupio/lupio_blk.o
 [ CXX] src/dev/lupio/lupio_ipi.cc -> ALL/dev/lupio/lupio_ipi.o
 [ CXX] src/dev/lupio/lupio_pic.cc -> ALL/dev/lupio/lupio_pic.o
 [ CXX] src/dev/lupio/lupio_rng.cc ->

[gem5-dev] [XS] Change in gem5/gem5[develop]: python: Fix broken call to m5.fatal in _check_tracing()

2023-04-13 Thread Richard Cooper (Gerrit) via gem5-dev 
Richard Cooper has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/50447?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: python: Fix broken call to m5.fatal in _check_tracing()
..

python: Fix broken call to m5.fatal in _check_tracing()

The call to m5.fatal in _check_tracing() fails because it has not been
imported at this point.

Change-Id: I60b1de6128d0ffc29e03e9ed98a8f9f679ef0ff9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50447
Maintainer: Bobby Bruce 
Reviewed-by: Bobby Bruce 
Tested-by: kokoro 
---
M src/python/m5/main.py
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  Bobby Bruce: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index d8c9951..b4a3472 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -334,12 +334,13 @@


 def _check_tracing():
+import m5
 import _m5.core

 if _m5.core.TRACING_ON:
 return

-fatal("Tracing is not enabled.  Compile with TRACING_ON")
+m5.fatal("Tracing is not enabled.  Compile with TRACING_ON")


 def main():

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I60b1de6128d0ffc29e03e9ed98a8f9f679ef0ff9
Gerrit-Change-Number: 50447
Gerrit-PatchSet: 3
Gerrit-Owner: Richard Cooper 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Jason Lowe-Power 
Gerrit-MessageType: merged
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