[gem5-dev] [S] Change in gem5/gem5[develop]: dev-amdgpu: Fix nbio psp ring assert

2023-05-22 Thread Matthew Poremba (Gerrit) via gem5-dev 
Matthew Poremba has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70677?usp=email )


Change subject: dev-amdgpu: Fix nbio psp ring assert
..

dev-amdgpu: Fix nbio psp ring assert

The size of the packet changes between ROCm 4.x and ROCm 5.x. Change how
the address is set based on the incoming packet size so that both
versions continue to work for now.

Change-Id: I91694e4760198fd9129e60140df4e863666be2e2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70677
Tested-by: kokoro 
Reviewed-by: Matt Sinclair 
Maintainer: Matt Sinclair 
---
M src/dev/amdgpu/amdgpu_nbio.cc
1 file changed, 17 insertions(+), 3 deletions(-)

Approvals:
  kokoro: Regressions pass
  Matt Sinclair: Looks good to me, approved; Looks good to me, approved




diff --git a/src/dev/amdgpu/amdgpu_nbio.cc b/src/dev/amdgpu/amdgpu_nbio.cc
index 8064fd2..69e4373 100644
--- a/src/dev/amdgpu/amdgpu_nbio.cc
+++ b/src/dev/amdgpu/amdgpu_nbio.cc
@@ -162,9 +162,23 @@
 AMDGPUNbio::writeFrame(PacketPtr pkt, Addr offset)
 {
 if (offset == psp_ring_listen_addr) {
-assert(pkt->getSize() == 8);
-psp_ring_dev_addr = pkt->getLE()
-  - gpuDevice->getVM().getSysAddrRangeLow();
+DPRINTF(AMDGPUDevice, "Saw psp_ring_listen_addr with size %ld  
value "

+"%ld\n", pkt->getSize(), pkt->getUintX(ByteOrder::little));
+
+/*
+ * In ROCm versions 4.x this packet is a 4 byte value. In ROCm 5.x
+ * the packet is 8 bytes and mapped as a system address which needs
+ * to be subtracted out to get the framebuffer address.
+ */
+if (pkt->getSize() == 4) {
+psp_ring_dev_addr = pkt->getLE();
+} else if (pkt->getSize() == 8) {
+psp_ring_dev_addr = pkt->getUintX(ByteOrder::little)
+  - gpuDevice->getVM().getSysAddrRangeLow();
+} else {
+panic("Invalid write size to psp_ring_listen_addr\n");
+}
+
 DPRINTF(AMDGPUDevice, "Setting PSP ring device address to %#lx\n",
 psp_ring_dev_addr);
 }

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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I91694e4760198fd9129e60140df4e863666be2e2
Gerrit-Change-Number: 70677
Gerrit-PatchSet: 3
Gerrit-Owner: Matthew Poremba 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: VISHNU RAMADAS 
Gerrit-Reviewer: kokoro 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: resources, tests, configs: Introduce gem5 Vision to resources

2023-05-22 Thread Kunal Pai (Gerrit) via gem5-dev 
Kunal Pai has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70859?usp=email )



Change subject: resources, tests, configs: Introduce gem5 Vision to  
resources

..

resources, tests, configs: Introduce gem5 Vision to resources

This patch makes changes to resources based on the gem5 Vision project.
Firstly, a MongoDB database is supported.
A JSON database's support is continued.
The data for these databases is stored in src/python
under "gem5-config.json".

An AbstractClient is an abstract class that implements
searching and sorting relevant to the databases.

Databases is an optional list that can be passed
while defining any Resource class and obtain_resource.
These databases can be defined in the config JSON.

Resource version is a new feature introduced.
It is a string and decouples a resource from the gem5 Version.
Example of a version is "1.0.0".
It is an optional field that can be passed while
defining any Resource class and obtain_resource.
By default, it picks the latest version compatible
with the gem5 Version of the user.

A gem5 resource schema now has additional fields.
These are:
- source_url: Stores URL of GitHub Source of the resource.
- license: License information of the resource.
- tags: Words to identify a resource better,
  like hello for hello-world.
- example_usage: How to use the resource in a simulation.
- gem5_versions: List of gem5 versions that resource is
  compatible with.
- resource_version: The version of the resource itself.
- size: The load size of the resource, if it exists.
- code_examples: List of objects.
These objects contain the path to where a resource is
used in gem5 example config scripts,
and if the resource itself is used in tests or not.

Some fields have been renamed:
- "name" is changed to "id"
- "documentation" is changed to "description"

Besides these, the schema also supports
resource specialization.

It adds fields revant to a specific resource as specified in
src/python/gem5/resources/resource.py

These changes have been made to better present information
on the new gem5 Resources website.

But, they do not affect the way resources are used in gem5.

Also, refs in the tests have been changed to match this new schema.
Tests have been changed to work with the two clients.

Change-Id: I19d4fecd5bb68eb6ac851ea9584276ee328e8bd8
Co-authored-by: Parth Shah 
Co-authored-by: Harshil Patel 
Co-authored-by: aarsli 
---
1 file changed, 3 insertions(+), 0 deletions(-)




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Gerrit-Owner: Kunal Pai 
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[gem5-dev] [S] Change in gem5/gem5[develop]: tests,systemc: Fix nightly systemc test

2023-05-22 Thread Bobby Bruce (Gerrit) via gem5-dev 
Bobby Bruce has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70860?usp=email )



Change subject: tests,systemc: Fix nightly systemc test
..

tests,systemc: Fix nightly systemc test

This fixes these nightly failing tests:
https://jenkins.gem5.org/job/nightly/609/

Due to this commit:
https://gem5-review.googlesource.com/c/public/gem5/+/68758
The source files are not copied to the "build" directory by default.
This caused the systemc tests to fail as the
"util/systemc/gem5_within_systemc/Makefile" depends on generated source
files in the "build" directory.

This patch adds the "--duplicate-sources" flag to the building of the
ARM binaries necessisary for running systemc. The README has been
updated to reflect this.

Change-Id: I3006005e43276097be98f7d4685f3d98c180d3f9
---
M tests/nightly.sh
M util/systemc/gem5_within_systemc/README
2 files changed, 12 insertions(+), 6 deletions(-)



diff --git a/tests/nightly.sh b/tests/nightly.sh
index 9286c54..cea1ad0 100755
--- a/tests/nightly.sh
+++ b/tests/nightly.sh
@@ -173,9 +173,11 @@
 docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \
 "${gem5_root}" --memory="${docker_mem_limit}" --rm \
 gcr.io/gem5-test/ubuntu-22.04_min-dependencies:${tag} bash -c "\
-scons -j${compile_threads} --ignore-style build/ARM/gem5.opt && \
-scons --with-cxx-config --without-python --without-tcmalloc USE_SYSTEMC=0 \
--j${compile_threads} build/ARM/libgem5_opt.so \
+scons -j${compile_threads} --ignore-style --duplicate-sources \
+build/ARM/gem5.opt && \
+scons --with-cxx-config --without-python --without-tcmalloc \
+--duplicate-sources USE_SYSTEMC=0  \
+-j${compile_threads} build/ARM/libgem5_opt.so \
 "

 docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \
diff --git a/util/systemc/gem5_within_systemc/README  
b/util/systemc/gem5_within_systemc/README

index b50ed71..bcaacee 100644
--- a/util/systemc/gem5_within_systemc/README
+++ b/util/systemc/gem5_within_systemc/README
@@ -28,17 +28,21 @@
 First build gem5 as a library with cxx-config support and (optionally)
 without python.  When building the library, disable gem5's native SystemC
 API support, as that will conflict with the external version.  Also build a
-normal gem5 (cxx-config not needed, Python needed):
+normal gem5 (cxx-config not needed, Python needed)
+
+Note: The `--duplicate-source` option is also needed as
+"util/systemc/gem5_within_systemc" depends on generated source files to be
+present in the "build" directory.

 > cd ../../..
 > scons build/ARM/gem5.opt
 > scons --with-cxx-config --without-python --without-tcmalloc  
USE_SYSTEMC=0 \

->   build/ARM/libgem5_opt.so
+>   --duplicate-source build/ARM/libgem5_opt.so
 > cd util/systemc

 Note: For MAC / OSX this command should be used:
 > scons --with-cxx-config --without-python --without-tcmalloc  
USE_SYSTEMC=0 \

->   build/ARM/libgem5_opt.dylib
+>   --duplicate-sources build/ARM/libgem5_opt.dylib

 Set a proper LD_LIBRARY_PATH e.g. for bash:
 > export LD_LIBRARY_PATH="$LD_LIBRARY_PATH:/path/to/gem5/build/ARM/"

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[gem5-dev] [XS] Change in gem5/gem5[develop]: dev-amdgpu: Update SDMA checkpointing

2023-05-22 Thread Matthew Poremba (Gerrit) via gem5-dev 
Matthew Poremba has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70878?usp=email )



Change subject: dev-amdgpu: Update SDMA checkpointing
..

dev-amdgpu: Update SDMA checkpointing

Patch https://gem5-review.googlesource.com/c/public/gem5/+/70040 added
support for a variable number of SDMA engines to support newer GPU
models. As part of this an SDMA IDs map was added to map from SDMA ID
number to the SDMA SimObject pointer. In order to get the correct
pointer in unserialize now, we need to store the ID in the checkpoint
and use that to index the new map. We can't simply assign using the loop
variable as the SDMAs might not be in order in the checkpoint and
additionally the checkpoint contains both the gfx and page offset for
the SDMA engines, so each SDMA is inserted into the SDMA offset map
(sdmaEngs) twice.

Change-Id: I08e9a8d785f467b6eebff8ab0a9336851c87258d
---
M src/dev/amdgpu/amdgpu_device.cc
M src/dev/amdgpu/sdma_engine.hh
2 files changed, 5 insertions(+), 3 deletions(-)



diff --git a/src/dev/amdgpu/amdgpu_device.cc  
b/src/dev/amdgpu/amdgpu_device.cc

index f58d1f7..7037e6f 100644
--- a/src/dev/amdgpu/amdgpu_device.cc
+++ b/src/dev/amdgpu/amdgpu_device.cc
@@ -604,7 +604,7 @@
 idx = 0;
 for (auto & it : sdmaEngs) {
 sdma_engs_offset[idx] = it.first;
-sdma_engs[idx] = idx;
+sdma_engs[idx] = it.second->getId();
 ++idx;
 }

@@ -675,8 +675,9 @@
 UNSERIALIZE_ARRAY(sdma_engs,  
sizeof(sdma_engs)/sizeof(sdma_engs[0]));


 for (int idx = 0; idx < sdma_engs_size; ++idx) {
-assert(sdmaIds.count(idx));
-SDMAEngine *sdma = sdmaIds[idx];
+int sdma_id = sdma_engs[idx];
+assert(sdmaIds.count(sdma_id));
+SDMAEngine *sdma = sdmaIds[sdma_id];
 sdmaEngs.insert(std::make_pair(sdma_engs_offset[idx], sdma));
 }
 }
diff --git a/src/dev/amdgpu/sdma_engine.hh b/src/dev/amdgpu/sdma_engine.hh
index 1e4f965..bcbd497 100644
--- a/src/dev/amdgpu/sdma_engine.hh
+++ b/src/dev/amdgpu/sdma_engine.hh
@@ -165,6 +165,7 @@
 void setGPUDevice(AMDGPUDevice *gpu_device);

 void setId(int _id) { id = _id; }
+int getId() const { return id; }
 /**
  * Returns the client id for the Interrupt Handler.
  */

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[gem5-dev] Re: Build failed in Jenkins: nightly #612

2023-05-22 Thread Bobby Bruce via gem5-dev 
I’ve fixed the nightly failures with this patch: 
https://gem5-review.googlesource.com/c/public/gem5/+/70860

--
Dr. Bobby R. Bruce
Room 3050,
Kemper Hall, UC Davis
Davis,
CA, 95616
 
web: https://www.bobbybruce.net

> On May 21, 2023, at 5:04 PM, jenkins-no-reply--- via gem5-dev 
>  wrote:
> 
> See 
> 
> Changes:
> 
> 
> --
> [...truncated 4.93 MB...]
> [   SHCXX] ARM/python/_m5/param_PerfectCompressor.cc -> .os
> [SO Param] m5.objects.BloomFilters, BloomFilterBase -> 
> ARM/python/_m5/param_BloomFilterBase.cc
> [SO Param] m5.objects.FuncUnit, FUDesc -> ARM/python/_m5/param_FUDesc.cc
> [SO Param] m5.objects.QemuFwCfg, QemuFwCfgItemBytes -> 
> ARM/params/QemuFwCfgItemBytes.hh
> [CXXCPRCC] m5.objects.Device, PioDevice -> ARM/cxx_config/PioDevice.cc
> [SO Param] m5.objects.DRAMInterface, DRAMInterface -> 
> ARM/python/_m5/param_DRAMInterface.cc
> [SO Param] m5.objects.ClockedObject, ClockedObject -> 
> ARM/python/_m5/param_ClockedObject.cc
> [   SHCXX] ARM/python/_m5/param_QemuFwCfgItemFile.cc -> .os
> [   SHCXX] ARM/cxx_config/QemuFwCfg.cc -> .os
> [CXXCPRHH] m5.objects.Device, PioDevice -> ARM/cxx_config/PioDevice.hh
> [   SHCXX] src/dev/qemu/fw_cfg.cc -> ARM/dev/qemu/fw_cfg.os
> [   SHCXX] ARM/python/_m5/param_ClockedObject.cc -> .os
> [   SHCXX] ARM/cxx_config/QemuFwCfgItemBytes.cc -> .os
> [   SHCXX] ARM/cxx_config/PioDevice.cc -> .os
> [   SHCXX] ARM/python/_m5/param_QemuFwCfg.cc -> .os
> [   SHCXX] ARM/cxx_config/QemuFwCfgMmio.cc -> .os
> [   SHCXX] ARM/python/_m5/param_QemuFwCfgItemBytes.cc -> .os
> [   SHCXX] ARM/cxx_config/QemuFwCfgItemString.cc -> .os
> [   SHCXX] ARM/python/_m5/param_QemuFwCfgMmio.cc -> .os
> [   SHCXX] ARM/cxx_config/QemuFwCfgItem.cc -> .os
> [   SHCXX] ARM/python/_m5/param_QemuFwCfgItemString.cc -> .os
> [   SHCXX] ARM/cxx_config/QemuFwCfgIo.cc -> .os
> [   SHCXX] ARM/python/_m5/param_QemuFwCfgItem.cc -> .os
> [   SHCXX] ARM/cxx_config/QemuFwCfgItemFile.cc -> .os
> [   SHCXX] ARM/python/_m5/param_QemuFwCfgIo.cc -> .os
> [SO Param] m5.objects.TimingExpr, TimingExprRef -> 
> ARM/python/_m5/param_TimingExprRef.cc
> [CXXCPRCC] m5.objects.VirtIORng, VirtIORng -> ARM/cxx_config/VirtIORng.cc
> [SO Param] m5.objects.SerialLink, SerialLink -> ARM/params/SerialLink.hh
> [SO Param] m5.objects.ArmNativeTrace, ArmNativeTrace -> 
> ARM/params/ArmNativeTrace.hh
> [CXXCPRHH] m5.objects.VirtIORng, VirtIORng -> ARM/cxx_config/VirtIORng.hh
> [SO Param] m5.objects.FuncUnit, FUDesc -> ARM/params/FUDesc.hh
> [   SHCXX] src/mem/serial_link.cc -> ARM/mem/serial_link.os
> [   SHCXX] ARM/python/_m5/param_ArmNativeTrace.cc -> .os
> [   SHCXX] ARM/cxx_config/ArmNativeTrace.cc -> .os
> [   SHCXX] ARM/cxx_config/VirtIORng.cc -> .os
> [   SHCXX] src/arch/arm/nativetrace.cc -> ARM/arch/arm/nativetrace.os
> [   SHCXX] ARM/cxx_config/FUPool.cc -> .os
> [   SHCXX] src/cpu/o3/fetch.cc -> ARM/cpu/o3/fetch.os
> [   SHCXX] src/cpu/o3/rename_map.cc -> ARM/cpu/o3/rename_map.os
> [   SHCXX] ARM/python/_m5/param_OpDesc.cc -> .os
> [   SHCXX] src/cpu/o3/checker.cc -> ARM/cpu/o3/checker.os
> [   SHCXX] src/cpu/o3/iew.cc -> ARM/cpu/o3/iew.os
> [   SHCXX] src/cpu/o3/commit.cc -> ARM/cpu/o3/commit.os
> [   SHCXX] src/cpu/o3/lsq_unit.cc -> ARM/cpu/o3/lsq_unit.os
> [   SHCXX] ARM/python/_m5/param_FUPool.cc -> .os
> [   SHCXX] src/cpu/o3/dyn_inst.cc -> ARM/cpu/o3/dyn_inst.os
> [   SHCXX] src/cpu/o3/rename.cc -> ARM/cpu/o3/rename.os
> [   SHCXX] ARM/cxx_config/BaseO3Checker.cc -> .os
> [   SHCXX] src/cpu/o3/probe/simple_trace.cc -> 
> ARM/cpu/o3/probe/simple_trace.os
> [   SHCXX] ARM/cxx_config/BaseO3CPU.cc -> .os
> [   SHCXX] src/cpu/o3/fu_pool.cc -> ARM/cpu/o3/fu_pool.os
> [   SHCXX] ARM/python/_m5/param_FUDesc.cc -> .os
> [   SHCXX] src/cpu/o3/lsq.cc -> ARM/cpu/o3/lsq.os
> [   SHCXX] src/cpu/o3/thread_state.cc -> ARM/cpu/o3/thread_state.os
> [   SHCXX] src/cpu/o3/decode.cc -> ARM/cpu/o3/decode.os
> [   SHCXX] ARM/python/_m5/param_BaseO3Checker.cc -> .os
> [   SHCXX] ARM/python/_m5/param_BaseO3CPU.cc -> .os
> [   SHCXX] ARM/cxx_config/OpDesc.cc -> .os
> [   SHCXX] src/cpu/o3/rob.cc -> ARM/cpu/o3/rob.os
> [   SHCXX] src/cpu/func_unit.cc -> ARM/cpu/func_unit.os
> [   SHCXX] src/cpu/o3/inst_queue.cc -> ARM/cpu/o3/inst_queue.os
> [   SHCXX] src/cpu/o3/thread_context.cc -> ARM/cpu/o3/thread_context.os
> [   SHCXX] src/cpu/o3/cpu.cc -> ARM/cpu/o3/cpu.os
> [   SHCXX] src/cpu/o3/mem_dep_unit.cc -> ARM/cpu/o3/mem_dep_unit.os
> [   SHCXX] ARM/cxx_config/FUDesc.cc -> .os
> [   SHCXX] ARM/python/_m5/param_SerialLink.cc -> .os
> [   SHCXX] ARM/cxx_config/SerialLink.cc -> .os
> [SO Param] m5.objects.BranchPredictor, TournamentBP -> 
> ARM/python/_m5/param_TournamentBP.cc
> [SO Param] m5.objects.TimingExpr, TimingExprRef -> ARM/params/TimingExprRef.hh
> [SO Param] m5.objects.PcCountTracker, PcCountTrackerManager -> 
> ARM/params/PcCountTrackerManager.hh
> [   SHCXX] ARM/cxx_config/TimingExprSrcReg.cc -> .os
> [   SHCXX] src/cpu/probes/pc_count_

[gem5-dev] Build failed in Jenkins: nightly #613

2023-05-22 Thread jenkins-no-reply--- via gem5-dev 
See 

Changes:

[rogerycchang] configs: Update riscv/fs_linux.py script


--
[...truncated 4.92 MB...]
 [   SHCXX] ARM/arch/arm/generated/generic_cpu_exec_2.cc -> .os
 [   SHCXX] src/arch/arm/regs/misc.cc -> ARM/arch/arm/regs/misc.os
 [   SHCXX] src/arch/arm/insts/branch.cc -> ARM/arch/arm/insts/branch.os
 [   SHCXX] ARM/cxx_config/ArmMMU.cc -> .os
 [   SHCXX] src/arch/arm/insts/sve.cc -> ARM/arch/arm/insts/sve.os
 [   SHCXX] ARM/arch/arm/generated/generic_cpu_exec_5.cc -> .os
 [   SHCXX] src/arch/arm/tlbi_op.cc -> ARM/arch/arm/tlbi_op.os
 [   SHCXX] src/arch/arm/insts/sme.cc -> ARM/arch/arm/insts/sme.os
 [   SHCXX] src/arch/arm/insts/macromem.cc -> ARM/arch/arm/insts/macromem.os
 [   SHCXX] ARM/python/_m5/param_ArmTLB.cc -> .os
 [   SHCXX] ARM/arch/arm/generated/inst-constrs-1.cc -> .os
 [   SHCXX] src/arch/arm/isa.cc -> ARM/arch/arm/isa.os
 [   SHCXX] src/arch/arm/insts/misc.cc -> ARM/arch/arm/insts/misc.os
 [   SHCXX] ARM/arch/arm/generated/generic_cpu_exec_1.cc -> .os
 [   SHCXX] src/arch/arm/table_walker.cc -> ARM/arch/arm/table_walker.os
 [   SHCXX] src/arch/arm/insts/tme64classic.cc -> 
ARM/arch/arm/insts/tme64classic.os
 [   SHCXX] ARM/python/_m5/param_ArmMMU.cc -> .os
 [   SHCXX] src/arch/arm/pmu.cc -> ARM/arch/arm/pmu.os
 [   SHCXX] src/arch/arm/insts/static_inst.cc -> 
ARM/arch/arm/insts/static_inst.os
 [   SHCXX] ARM/arch/arm/generated/generic_cpu_exec_4.cc -> .os
 [   SHCXX] src/arch/arm/tracers/tarmac_parser.cc -> 
ARM/arch/arm/tracers/tarmac_parser.os
 [   SHCXX] src/arch/arm/tlb.cc -> ARM/arch/arm/tlb.os
 [   SHCXX] src/arch/arm/insts/data64.cc -> ARM/arch/arm/insts/data64.os
 [   SHCXX] ARM/arch/arm/generated/decoder.cc -> .os
 [   SHCXX] src/arch/arm/insts/vfp.cc -> ARM/arch/arm/insts/vfp.os
 [   SHCXX] src/arch/arm/tracers/tarmac_record_v8.cc -> 
ARM/arch/arm/tracers/tarmac_record_v8.os
 [   SHCXX] src/arch/arm/insts/mem64.cc -> ARM/arch/arm/insts/mem64.os
 [   SHCXX] ARM/cxx_config/ArmISA.cc -> .os
 [   SHCXX] ARM/arch/arm/generated/inst-constrs-3.cc -> .os
 [   SHCXX] src/arch/arm/insts/tme64.cc -> ARM/arch/arm/insts/tme64.os
 [   SHCXX] src/arch/arm/regs/int.cc -> ARM/arch/arm/regs/int.os
 [   SHCXX] src/arch/arm/faults.cc -> ARM/arch/arm/faults.os
 [   SHCXX] src/dev/arm/gic_v3_cpu_interface.cc -> 
ARM/dev/arm/gic_v3_cpu_interface.os
 [   SHCXX] ARM/cxx_config/ArmTableWalker.cc -> .os
 [   SHCXX] ARM/arch/arm/generated/generic_cpu_exec_3.cc -> .os
 [   SHCXX] src/arch/arm/stage2_lookup.cc -> ARM/arch/arm/stage2_lookup.os
 [   SHCXX] src/arch/arm/mmu.cc -> ARM/arch/arm/mmu.os
 [   SHCXX] ARM/python/_m5/param_MPP_LoopPredictor.cc -> .os
 [   SHCXX] ARM/python/_m5/param_MultiperspectivePerceptronTAGE.cc -> .os
 [   SHCXX] ARM/python/_m5/param_MPP_StatisticalCorrector_8KB.cc -> .os
 [   SHCXX] ARM/cxx_config/MPP_StatisticalCorrector.cc -> .os
 [   SHCXX] ARM/python/_m5/param_MPP_TAGE.cc -> .os
 [   SHCXX] src/cpu/pred/multiperspective_perceptron_tage.cc -> 
ARM/cpu/pred/multiperspective_perceptron_tage.os
 [   SHCXX] ARM/cxx_config/MPP_StatisticalCorrector_64KB.cc -> .os
 [   SHCXX] ARM/cxx_config/MultiperspectivePerceptronTAGE8KB.cc -> .os
 [   SHCXX] ARM/python/_m5/param_MPP_TAGE_8KB.cc -> .os
 [   SHCXX] ARM/cxx_config/MPP_TAGE.cc -> .os
 [   SHCXX] ARM/cxx_config/MPP_LoopPredictor_8KB.cc -> .os
 [   SHCXX] ARM/python/_m5/param_MPP_StatisticalCorrector.cc -> .os
 [   SHCXX] ARM/python/_m5/param_MPP_StatisticalCorrector_64KB.cc -> .os
 [   SHCXX] ARM/python/_m5/param_MultiperspectivePerceptronTAGE8KB.cc -> .os
 [   SHCXX] src/cpu/pred/multiperspective_perceptron_tage_64KB.cc -> 
ARM/cpu/pred/multiperspective_perceptron_tage_64KB.os
 [   SHCXX] ARM/cxx_config/MultiperspectivePerceptronTAGE64KB.cc -> .os
 [   SHCXX] ARM/python/_m5/param_MPP_LoopPredictor_8KB.cc -> .os
 [   SHCXX] ARM/cxx_config/MPP_LoopPredictor.cc -> .os
 [   SHCXX] ARM/cxx_config/MultiperspectivePerceptronTAGE.cc -> .os
 [   SHCXX] ARM/cxx_config/MPP_StatisticalCorrector_8KB.cc -> .os
 [   SHCXX] src/cpu/pred/multiperspective_perceptron_tage_8KB.cc -> 
ARM/cpu/pred/multiperspective_perceptron_tage_8KB.os
 [   SHCXX] ARM/python/_m5/param_MultiperspectivePerceptronTAGE64KB.cc -> .os
 [   SHCXX] src/mem/ruby/network/garnet/NetworkLink.cc -> 
ARM/mem/ruby/network/garnet/NetworkLink.os
 [   SHCXX] ARM/python/_m5/param_NetworkLink.cc -> .os
 [   SHCXX] ARM/cxx_config/CreditLink.cc -> .os
 [   SHCXX] ARM/python/_m5/param_CreditLink.cc -> .os
 [   SHCXX] src/cpu/minor/func_unit.cc -> ARM/cpu/minor/func_unit.os
 [   SHCXX] ARM/cxx_config/MinorFUTiming.cc -> .os
 [   SHCXX] src/cpu/minor/pipeline.cc -> ARM/cpu/minor/pipeline.os
 [   SHCXX] ARM/cxx_config/BaseMinorCPU.cc -> .os
 [   SHCXX] ARM/cxx_config/MinorOpClass.cc -> .os
 [   SHCXX] src/cpu/minor/fetch2.cc -> ARM/cpu/minor/fetch2.os
 [   SHCXX] src/cpu/minor/cpu.cc -> ARM/cpu/minor/cpu.os
 [   SHCXX] ARM/python/_m5/param_MinorFUTiming.cc -> .os
 [   SHCXX] ARM/cxx

[gem5-dev] [L] Change in gem5/gem5[develop]: arch-riscv: Simplify amd merge RV32/RV64 the RVM instructions

2023-05-22 Thread Roger Chang (Gerrit) via gem5-dev 
Roger Chang has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70597?usp=email )


Change subject: arch-riscv: Simplify amd merge RV32/RV64 the RVM  
instructions

..

arch-riscv: Simplify amd merge RV32/RV64 the RVM instructions

The change move the details implementation to utility.hh and merge
the RV32 and RV64 versions into one.

Change-Id: I438bfb0fc511f0f27e83f247d386c58493db65b4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70597
Tested-by: kokoro 
Reviewed-by: Yu-hsin Wang 
Maintainer: Bobby Bruce 
---
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/utility.hh
2 files changed, 149 insertions(+), 183 deletions(-)

Approvals:
  kokoro: Regressions pass
  Yu-hsin Wang: Looks good to me, approved
  Bobby Bruce: Looks good to me, approved




diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 3acd80e..47519ee 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1084,34 +1084,13 @@
 0x0: sll({{
 Rd = rvSext(Rs1 << rvSelect(Rs2<4:0>, Rs2<5:0>));
 }});
-0x1: decode RVTYPE {
-0x0: rv32_mulh({{
-Rd_sw = ((int64_t)Rs1_sw * Rs2_sw) >> 32;
-}}, IntMultOp);
-0x1: mulh({{
-bool negate = (Rs1_sd < 0) != (Rs2_sd < 0);
-
-uint64_t Rs1_lo = (uint32_t)std::abs(Rs1_sd);
-uint64_t Rs1_hi = (uint64_t)std::abs(Rs1_sd)  

32;

-uint64_t Rs2_lo = (uint32_t)std::abs(Rs2_sd);
-uint64_t Rs2_hi = (uint64_t)std::abs(Rs2_sd)  

32;

-
-uint64_t hi = Rs1_hi*Rs2_hi;
-uint64_t mid1 = Rs1_hi*Rs2_lo;
-uint64_t mid2 = Rs1_lo*Rs2_hi;
-uint64_t lo = Rs2_lo*Rs1_lo;
-uint64_t carry = ((uint64_t)(uint32_t)mid1
-+ (uint64_t)(uint32_t)mid2
-+ (lo >> 32)) >> 32;
-
-uint64_t res = hi +
-  (mid1 >> 32) +
-  (mid2 >> 32) +
-  carry;
-Rd = negate ? ~res + (Rs1_sd*Rs2_sd == 0 ? 1 :  
0)

-: res;
-}}, IntMultOp);
-}
+0x1: mulh({{
+if (machInst.rv_type == RV32) {
+Rd_sd = mulh_32(Rs1_sd, Rs2_sd);
+} else {
+Rd_sd = mulh_64(Rs1_sd, Rs2_sd);
+}
+}}, IntMultOp);
 0x5: clmul({{
 uint64_t result = 0;
 for (int i = 0; i < rvSelect(32, 64); i++) {
@@ -1144,32 +1123,13 @@
 0x0: slt({{
 Rd = (rvSext(Rs1_sd) < rvSext(Rs2_sd)) ? 1 : 0;
 }});
-0x1: decode RVTYPE {
-0x0: rv32_mulhsu({{
-Rd_sw = ((int64_t)Rs1_sw * Rs2_uw) >> 32;
-}}, IntMultOp);
-0x1: mulhsu({{
-bool negate = Rs1_sd < 0;
-uint64_t Rs1_lo = (uint32_t)std::abs(Rs1_sd);
-uint64_t Rs1_hi = (uint64_t)std::abs(Rs1_sd)  

32;

-uint64_t Rs2_lo = (uint32_t)Rs2;
-uint64_t Rs2_hi = Rs2 >> 32;
-
-uint64_t hi = Rs1_hi*Rs2_hi;
-uint64_t mid1 = Rs1_hi*Rs2_lo;
-uint64_t mid2 = Rs1_lo*Rs2_hi;
-uint64_t lo = Rs1_lo*Rs2_lo;
-uint64_t carry = ((uint64_t)(uint32_t)mid1
-+ (uint64_t)(uint32_t)mid2
-+ (lo >> 32)) >> 32;
-
-uint64_t res = hi +
-  (mid1 >> 32) +
-  (mid2 >> 32) +
-  carry;
-Rd = negate ? ~res + (Rs1_sd*Rs2 == 0 ? 1 :  
0) : res;

-}}, IntMultOp);
-}
+0x1: mulhsu({{
+if (machInst.rv_type == RV32) {
+Rd_sd = mulhsu_32(Rs1_sd, Rs2);
+} else {
+Rd_sd = mulhsu_64(Rs1_sd, Rs2);
+}
+}}, IntMultOp);

[gem5-dev] [S] Change in gem5/gem5[develop]: tests,systemc: Fix nightly systemc test

2023-05-22 Thread Bobby Bruce (Gerrit) via gem5-dev 
Bobby Bruce has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70860?usp=email )


Change subject: tests,systemc: Fix nightly systemc test
..

tests,systemc: Fix nightly systemc test

This fixes these nightly failing tests:
https://jenkins.gem5.org/job/nightly/609/

Due to this commit:
https://gem5-review.googlesource.com/c/public/gem5/+/68758
The source files are not copied to the "build" directory by default.
This caused the systemc tests to fail as the
"util/systemc/gem5_within_systemc/Makefile" depends on generated source
files in the "build" directory.

This patch adds the "--duplicate-sources" flag to the building of the
ARM binaries necessisary for running systemc. The README has been
updated to reflect this.

Change-Id: I3006005e43276097be98f7d4685f3d98c180d3f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70860
Tested-by: kokoro 
Maintainer: Bobby Bruce 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M tests/nightly.sh
M util/systemc/gem5_within_systemc/README
2 files changed, 12 insertions(+), 6 deletions(-)

Approvals:
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Bobby Bruce: Looks good to me, approved




diff --git a/tests/nightly.sh b/tests/nightly.sh
index 9286c54..cea1ad0 100755
--- a/tests/nightly.sh
+++ b/tests/nightly.sh
@@ -173,9 +173,11 @@
 docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \
 "${gem5_root}" --memory="${docker_mem_limit}" --rm \
 gcr.io/gem5-test/ubuntu-22.04_min-dependencies:${tag} bash -c "\
-scons -j${compile_threads} --ignore-style build/ARM/gem5.opt && \
-scons --with-cxx-config --without-python --without-tcmalloc USE_SYSTEMC=0 \
--j${compile_threads} build/ARM/libgem5_opt.so \
+scons -j${compile_threads} --ignore-style --duplicate-sources \
+build/ARM/gem5.opt && \
+scons --with-cxx-config --without-python --without-tcmalloc \
+--duplicate-sources USE_SYSTEMC=0  \
+-j${compile_threads} build/ARM/libgem5_opt.so \
 "

 docker run -u $UID:$GID --volume "${gem5_root}":"${gem5_root}" -w \
diff --git a/util/systemc/gem5_within_systemc/README  
b/util/systemc/gem5_within_systemc/README

index b50ed71..bcaacee 100644
--- a/util/systemc/gem5_within_systemc/README
+++ b/util/systemc/gem5_within_systemc/README
@@ -28,17 +28,21 @@
 First build gem5 as a library with cxx-config support and (optionally)
 without python.  When building the library, disable gem5's native SystemC
 API support, as that will conflict with the external version.  Also build a
-normal gem5 (cxx-config not needed, Python needed):
+normal gem5 (cxx-config not needed, Python needed)
+
+Note: The `--duplicate-source` option is also needed as
+"util/systemc/gem5_within_systemc" depends on generated source files to be
+present in the "build" directory.

 > cd ../../..
 > scons build/ARM/gem5.opt
 > scons --with-cxx-config --without-python --without-tcmalloc  
USE_SYSTEMC=0 \

->   build/ARM/libgem5_opt.so
+>   --duplicate-source build/ARM/libgem5_opt.so
 > cd util/systemc

 Note: For MAC / OSX this command should be used:
 > scons --with-cxx-config --without-python --without-tcmalloc  
USE_SYSTEMC=0 \

->   build/ARM/libgem5_opt.dylib
+>   --duplicate-sources build/ARM/libgem5_opt.dylib

 Set a proper LD_LIBRARY_PATH e.g. for bash:
 > export LD_LIBRARY_PATH="$LD_LIBRARY_PATH:/path/to/gem5/build/ARM/"

--
To view, visit  
https://gem5-review.googlesource.com/c/public/gem5/+/70860?usp=email
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings?usp=email


Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3006005e43276097be98f7d4685f3d98c180d3f9
Gerrit-Change-Number: 70860
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby Bruce 
Gerrit-Reviewer: Bobby Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_RNG

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70721?usp=email )


Change subject: arch-arm: Implement FEAT_RNG
..

arch-arm: Implement FEAT_RNG

Change-Id: I9d60d249172ef4bbaf5d9b38ef279eff344b80d8
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70721
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/isa.cc
M src/arch/arm/process.cc
M src/arch/arm/regs/misc.cc
M src/arch/arm/regs/misc.hh
M src/arch/arm/regs/misc_types.hh
6 files changed, 64 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index e08108f..c3b3cf6 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -88,6 +88,8 @@
 "FEAT_FLAGM",
 # Armv8.5
 "FEAT_FLAGM2",
+"FEAT_RNG",
+"FEAT_RNG_TRAP",
 # Armv9.2
 "FEAT_SME",  # Optional in Armv9.2
 # Others
@@ -204,7 +206,11 @@


 class Armv85(Armv84):
-extensions = Armv84.extensions + ["FEAT_FLAGM2"]
+extensions = Armv84.extensions + [
+"FEAT_FLAGM2",
+"FEAT_RNG",
+"FEAT_RNG_TRAP",
+]


 class Armv92(Armv85):
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 9c8e282..0212926 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -49,6 +49,7 @@
 #include "arch/arm/utility.hh"
 #include "arch/generic/decoder.hh"
 #include "base/cprintf.hh"
+#include "base/random.hh"
 #include "cpu/base.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/reg_class.hh"
@@ -596,6 +597,21 @@
   case MISCREG_HIFAR: // alias for secure IFAR
 return readMiscRegNoEffect(MISCREG_IFAR_S);

+  case MISCREG_RNDR:
+tc->setReg(cc_reg::Nz, (RegVal)0);
+tc->setReg(cc_reg::C, (RegVal)0);
+tc->setReg(cc_reg::V, (RegVal)0);
+return random_mt.random();
+  case MISCREG_RNDRRS:
+tc->setReg(cc_reg::Nz, (RegVal)0);
+tc->setReg(cc_reg::C, (RegVal)0);
+tc->setReg(cc_reg::V, (RegVal)0);
+// Note: we are not reseeding
+// The random number generator already has an hardcoded
+// seed for the sake of determinism. There is no point
+// in simulating non-determinism here
+return random_mt.random();
+
   // Generic Timer registers
   case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
   case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index b2378cc..fda9415 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -318,6 +318,7 @@

 const AA64ISAR0 isa_r0 = tc->readMiscReg(MISCREG_ID_AA64ISAR0_EL1);
 hwcap |= (isa_r0.ts >= 2) ? Arm_Flagm2 : Arm_None;
+hwcap |= (isa_r0.rndr >= 1) ? Arm_Rng : Arm_None;

 return hwcap;
 }
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 9e633c0..0e92e3d 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -1057,6 +1057,8 @@
 { MiscRegNum64(3, 2, 0, 0, 0), MISCREG_CSSELR_EL1 },
 { MiscRegNum64(3, 3, 0, 0, 1), MISCREG_CTR_EL0 },
 { MiscRegNum64(3, 3, 0, 0, 7), MISCREG_DCZID_EL0 },
+{ MiscRegNum64(3, 3, 2, 4, 0), MISCREG_RNDR },
+{ MiscRegNum64(3, 3, 2, 4, 1), MISCREG_RNDRRS },
 { MiscRegNum64(3, 3, 4, 2, 0), MISCREG_NZCV },
 { MiscRegNum64(3, 3, 4, 2, 1), MISCREG_DAIF },
 { MiscRegNum64(3, 3, 4, 2, 2), MISCREG_SVCR },
@@ -1999,6 +2001,20 @@
 }
 }

+Fault
+faultRng(const MiscRegLUTEntry &entry,
+ThreadContext *tc, const MiscRegOp64 &inst)
+{
+const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+if (HaveExt(tc, ArmExtension::FEAT_RNG_TRAP) && scr.trndr) {
+return inst.generateTrap(EL3);
+} else if (!HaveExt(tc, ArmExtension::FEAT_RNG)) {
+return inst.undefined();
+} else {
+return NoFault;
+}
+}
+
 }

 MiscRegIndex
@@ -3894,6 +3910,7 @@
   isar0_el1.ts = release->has(ArmExtension::FEAT_FLAGM2) ?
   0x2 : release->has(ArmExtension::FEAT_FLAGM) ?
   0x1 : 0x0;
+  isar0_el1.rndr = release->has(ArmExtension::FEAT_RNG) ? 0x1 :  
0x0;

   return isar0_el1;
   }())
   .faultRead(EL1, HCR_TRAP(tid3))
@@ -5400,6 +5417,21 @@
 InitReg(MISCREG_MPAMSM_EL1)
 .allPrivileges().exceptUserMode();

+InitReg(MISCREG_RNDR)
+.faultRead(EL0, faultRng)
+.faultRead(EL1, faultRng)
+.faultRead(EL2, faultRng)
+.faultRead(EL3, faultRng)
+.unverifiable()
+.allPrivileges().writes(0);
+InitReg(MISCREG_RNDRRS)
+.faultRead(EL0, faultRng)
+.faultRead(EL1, faultRng)
+.faultRead(EL2, faultRng)
+.faultRead(E

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_IDST

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70723?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Implement FEAT_IDST
..

arch-arm: Implement FEAT_IDST

Change-Id: I3cabcfdb10f4eefaf2ab039376d840cc4c54609a
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70723
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/regs/misc.cc
2 files changed, 59 insertions(+), 17 deletions(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index c3b3cf6..b826f0d 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -86,6 +86,7 @@
 "FEAT_SEL2",
 "FEAT_TLBIOS",
 "FEAT_FLAGM",
+"FEAT_IDST",
 # Armv8.5
 "FEAT_FLAGM2",
 "FEAT_RNG",
@@ -170,6 +171,7 @@
 "FEAT_SEL2",
 "FEAT_TLBIOS",
 "FEAT_FLAGM",
+"FEAT_IDST",
 # Armv8.5
 "FEAT_FLAGM2",
 # Armv9.2
@@ -202,7 +204,12 @@


 class Armv84(Armv83):
-extensions = Armv83.extensions +  
["FEAT_SEL2", "FEAT_TLBIOS", "FEAT_FLAGM"]

+extensions = Armv83.extensions + [
+"FEAT_SEL2",
+"FEAT_TLBIOS",
+"FEAT_FLAGM",
+"FEAT_IDST",
+]


 class Armv85(Armv84):
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 56644e9..53e9268 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2077,6 +2077,22 @@
 }
 }

+Fault
+faultIdst(const MiscRegLUTEntry &entry,
+ThreadContext *tc, const MiscRegOp64 &inst)
+{
+if (HaveExt(tc, ArmExtension::FEAT_IDST)) {
+const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
+if (EL2Enabled(tc) && hcr.tge) {
+return inst.generateTrap(EL2);
+} else {
+return inst.generateTrap(EL1);
+}
+} else {
+return inst.undefined();
+}
+}
+
 }

 MiscRegIndex
@@ -3828,6 +3844,7 @@
 // AArch64 registers (Op0=1,3);
 InitReg(MISCREG_MIDR_EL1)
   .allPrivileges().exceptUserMode().writes(0)
+  .faultRead(EL0, faultIdst)
   .mapsTo(MISCREG_MIDR);
 InitReg(MISCREG_MPIDR_EL1)
   .allPrivileges().exceptUserMode().writes(0)
@@ -3923,34 +3940,40 @@
   return pfr0_el1;
   }())
   .unserialize(0)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_ID_AA64PFR1_EL1)
   .reset(release->has(ArmExtension::FEAT_SME) ?
   0x1 << 24 : 0)
   .unserialize(0)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_ID_AA64DFR0_EL1)
   .reset([p](){
   AA64DFR0 dfr0_el1 = p.id_aa64dfr0_el1;
   dfr0_el1.pmuver = p.pmu ? 1 : 0; // Enable PMUv3
   return dfr0_el1;
   }())
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_ID_AA64DFR1_EL1)
   .reset(p.id_aa64dfr1_el1)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_ID_AA64AFR0_EL1)
   .reset(p.id_aa64afr0_el1)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_ID_AA64AFR1_EL1)
   .reset(p.id_aa64afr1_el1)
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_ID_AA64ISAR0_EL1)
   .reset([p,release=release](){
   AA64ISAR0 isar0_el1 = p.id_aa64isar0_el1;
@@ -3975,8 +3998,9 @@
   isar0_el1.rndr = release->has(ArmExtension::FEAT_RNG) ? 0x1 :  
0x0;

   return isar0_el1;
   }())
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3))
-  .allPrivileges().exceptUserMode().writes(0);
+  .allPrivileges().writes(0);
 InitReg(MISCREG_ID_AA64ISAR1_EL1)
   .reset([p,release=release](){
   AA64ISAR1 isar1_el1 = p.id_aa64isar1_el1;
@@ -3986,8 +4010,9 @@
   isar1_el1.gpa = release->has(ArmExtension::FEAT_PAuth) ? 0x1 :  
0x0;

   return isar1_el1;
   }())
+  .faultRead(EL0, faultIdst)
   .faultRead(EL1, HCR_TRAP(tid3)

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement trapping of SME registers

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70722?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Implement trapping of SME registers
..

arch-arm: Implement trapping of SME registers

Change-Id: Ic5bcc79a535c928265fbc1db1cd0c85ba1a1b152
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70722
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/arch/arm/regs/misc.cc
1 file changed, 80 insertions(+), 1 deletion(-)

Approvals:
  kokoro: Regressions pass
  Richard Cooper: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved




diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 0e92e3d..56644e9 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2002,6 +2002,68 @@
 }

 Fault
+faultEsm(const MiscRegLUTEntry &entry,
+ThreadContext *tc, const MiscRegOp64 &inst)
+{
+const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
+if (ArmSystem::haveEL(tc, EL3) && !cptr_el3.esm) {
+return inst.generateTrap(EL3, ExceptionClass::TRAPPED_SME, 0);
+} else {
+return NoFault;
+}
+}
+
+Fault
+faultTsmSmen(const MiscRegLUTEntry &entry,
+ThreadContext *tc, const MiscRegOp64 &inst)
+{
+const HCR hcr_el2 = tc->readMiscReg(MISCREG_HCR_EL2);
+const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
+const bool el2_enabled = EL2Enabled(tc);
+if (el2_enabled && !hcr_el2.e2h && cptr_el2.tsm) {
+return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0);
+} else if (el2_enabled && hcr_el2.e2h && !(cptr_el2.smen & 0b1)) {
+return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0);
+} else {
+return faultEsm(entry, tc, inst);
+}
+}
+
+Fault
+faultSmenEL1(const MiscRegLUTEntry &entry,
+ThreadContext *tc, const MiscRegOp64 &inst)
+{
+const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
+if (!(cpacr.smen & 0b1)) {
+return inst.generateTrap(EL1, ExceptionClass::TRAPPED_SME, 0);
+} else {
+return faultTsmSmen(entry, tc, inst);
+}
+}
+
+Fault
+faultSmenEL0(const MiscRegLUTEntry &entry,
+ThreadContext *tc, const MiscRegOp64 &inst)
+{
+const bool el2_enabled = EL2Enabled(tc);
+const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+const bool in_host = hcr.e2h && hcr.tge;
+
+const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
+const CPTR cptr_el2 = tc->readMiscReg(MISCREG_CPTR_EL2);
+if (!(el2_enabled && in_host) && cpacr.smen != 0b11) {
+if (el2_enabled && hcr.tge)
+return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0);
+else
+return inst.generateTrap(EL1, ExceptionClass::TRAPPED_SME, 0);
+} else if (el2_enabled && in_host && cptr_el2.smen != 0b11) {
+return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SME, 0);
+} else {
+return faultTsmSmen(entry, tc, inst);
+}
+}
+
+Fault
 faultRng(const MiscRegLUTEntry &entry,
 ThreadContext *tc, const MiscRegOp64 &inst)
 {
@@ -5348,6 +5410,7 @@
 smfr0_el1.fa64 = 0x1;
 return smfr0_el1;
 }())
+.faultRead(EL1, HCR_TRAP(tid3))
 .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_SVCR)
 .res0([](){
@@ -5356,6 +5419,10 @@
 svcr_mask.za = 1;
 return ~svcr_mask;
 }())
+.fault(EL0, faultSmenEL0)
+.fault(EL1, faultSmenEL1)
+.fault(EL2, faultTsmSmen)
+.fault(EL3, faultEsm)
 .allPrivileges();
 InitReg(MISCREG_SMIDR_EL1)
 .reset([](){
@@ -5365,11 +5432,17 @@
 smidr_el1.implementer = 0x41;
 return smidr_el1;
 }())
+.faultRead(EL1, HCR_TRAP(tid1))
 .allPrivileges().exceptUserMode().writes(0);
 InitReg(MISCREG_SMPRI_EL1)
 .res0(mask(63, 4))
-.allPrivileges().exceptUserMode().reads(1);
+.fault(EL1, faultEsm)
+.fault(EL2, faultEsm)
+.fault(EL3, faultEsm)
+.allPrivileges().exceptUserMode();
 InitReg(MISCREG_SMPRIMAP_EL2)
+.fault(EL2, faultEsm)
+.fault(EL3, faultEsm)
 .hyp().mon();
 InitReg(MISCREG_SMCR_EL3)
 .reset([this](){
@@ -5383,6 +5456,7 @@
 smcr_el3.len = smeVL - 1;
 return smcr_el3;
 }())
+.fault(EL3, faultEsm)
 .mon();
 InitReg(MISCREG_SMCR_EL2)
 .reset([this](){
@@ -5396,6 +5470,8 @@
 smcr_el2.len = smeVL - 1;
 return smcr_el2;
 }())
+.fault(EL2, faultTsmSmen)
+.fault(EL3, faultEsm)
 .hyp().mon();
 InitReg(MISCREG_SMCR_EL12)
 .allPrivileges().exceptUserMode();
@

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_FLAGM(2)

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70719?usp=email )


Change subject: arch-arm: Implement FEAT_FLAGM(2)
..

arch-arm: Implement FEAT_FLAGM(2)

Change-Id: I21f1eb91ad9acb019a776a7d5edd38754571a62e
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70719
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/ArmISA.py
M src/arch/arm/ArmSystem.py
M src/arch/arm/insts/misc64.cc
M src/arch/arm/insts/misc64.hh
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/insts/misc64.isa
M src/arch/arm/isa/templates/misc64.isa
M src/arch/arm/process.cc
M src/arch/arm/regs/misc.cc
9 files changed, 244 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index e73046d..37970dc 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -58,6 +58,10 @@
 "FEAT_FCMA",
 "FEAT_JSCVT",
 "FEAT_PAuth",
+# Armv8.4
+"FEAT_FLAGM",
+# Armv8.5
+"FEAT_FLAGM2",
 # Armv9.2
 "FEAT_SME",
 # Other
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 9e2da8e..e08108f 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -85,6 +85,9 @@
 # Armv8.4
 "FEAT_SEL2",
 "FEAT_TLBIOS",
+"FEAT_FLAGM",
+# Armv8.5
+"FEAT_FLAGM2",
 # Armv9.2
 "FEAT_SME",  # Optional in Armv9.2
 # Others
@@ -164,6 +167,9 @@
 # Armv8.4
 "FEAT_SEL2",
 "FEAT_TLBIOS",
+"FEAT_FLAGM",
+# Armv8.5
+"FEAT_FLAGM2",
 # Armv9.2
 "FEAT_SME",
 ]
@@ -194,11 +200,15 @@


 class Armv84(Armv83):
-extensions = Armv83.extensions + ["FEAT_SEL2", "FEAT_TLBIOS"]
+extensions = Armv83.extensions +  
["FEAT_SEL2", "FEAT_TLBIOS", "FEAT_FLAGM"]



-class Armv92(Armv84):
-extensions = Armv84.extensions + ["FEAT_SME"]
+class Armv85(Armv84):
+extensions = Armv84.extensions + ["FEAT_FLAGM2"]
+
+
+class Armv92(Armv85):
+extensions = Armv85.extensions + ["FEAT_SME"]


 class ArmSystem(System):
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index c7423d9..4f573fc 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -55,6 +55,27 @@
 }

 std::string
+RegOp64::generateDisassembly(Addr pc, const loader::SymbolTable *symtab)  
const

+{
+std::stringstream ss;
+printMnemonic(ss, "", false);
+printIntReg(ss, op1);
+return ss.str();
+}
+
+std::string
+RegImmImmOp64::generateDisassembly(Addr pc, const loader::SymbolTable  
*symtab) const

+{
+std::stringstream ss;
+printMnemonic(ss, "", false);
+printIntReg(ss, op1);
+ccprintf(ss, "#0x%x", imm1);
+ss << ", ";
+ccprintf(ss, "#0x%x", imm2);
+return ss.str();
+}
+
+std::string
 RegRegImmImmOp64::generateDisassembly(
 Addr pc, const loader::SymbolTable *symtab) const
 {
diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index b7b66c2..3a67210 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -57,6 +57,38 @@
 Addr pc, const loader::SymbolTable *symtab) const override;
 };

+class RegOp64 : public ArmISA::ArmStaticInst
+{
+  protected:
+RegIndex op1;
+
+RegOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
+OpClass __opClass, RegIndex _op1) :
+ArmISA::ArmStaticInst(mnem, _machInst, __opClass), op1(_op1)
+{}
+
+std::string generateDisassembly(
+Addr pc, const loader::SymbolTable *symtab) const override;
+};
+
+class RegImmImmOp64 : public ArmISA::ArmStaticInst
+{
+  protected:
+RegIndex op1;
+uint64_t imm1;
+uint64_t imm2;
+
+RegImmImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
+  OpClass __opClass, RegIndex _op1,
+  uint64_t _imm1, uint64_t _imm2) :
+ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
+op1(_op1), imm1(_imm1), imm2(_imm2)
+{}
+
+std::string generateDisassembly(
+Addr pc, const loader::SymbolTable *symtab) const override;
+};
+
 class RegRegImmImmOp64 : public ArmISA::ArmStaticInst
 {
   protected:
diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index 0aafa9e..9ad2de2 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -424,6 +424,15 @@
 // MSR immediate: moving immediate value to  
selected

 // bits of the PSTATE
 switch (op1 << 3 | op2) {
+  case 0x0:
+

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Enable FEAT_PAuth in SE mode

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70759?usp=email )


Change subject: arch-arm: Enable FEAT_PAuth in SE mode
..

arch-arm: Enable FEAT_PAuth in SE mode

It was in theory already possible to use FEAT_PAuth instructions in
SE mode, however its presence was hidden to userspace code as
the cpu feature was not listed in the auxiliary vectors

Change-Id: I6da5da0878dde56c22ffdba25eff15e36f5022fe
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70759
Reviewed-by: Richard Cooper 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/process.cc
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 6b5f69e..02771ae 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -251,6 +251,8 @@
 hwcap |= (isa_r1.fcma >= 1) ? Arm_Fcma : 0;
 hwcap |= (isa_r1.lrcpc >= 1) ? Arm_Lrcpc : 0;
 hwcap |= (isa_r1.lrcpc >= 2) ? Arm_Ilrcpc : 0;
+hwcap |= (isa_r1.apa >= 1 || isa_r1.api >= 1) ? Arm_Paca : 0;
+hwcap |= (isa_r1.gpa >= 1 || isa_r1.gpi >= 1) ? Arm_Pacg : 0;

 const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1);


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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6da5da0878dde56c22ffdba25eff15e36f5022fe
Gerrit-Change-Number: 70759
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Extend SCR to be 64-bit wide

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70720?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Extend SCR to be 64-bit wide
..

arch-arm: Extend SCR to be 64-bit wide

Change-Id: I9928de3db61957404269d189a15a951fd6707c8a
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70720
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/arch/arm/regs/misc_types.hh
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/regs/misc_types.hh  
b/src/arch/arm/regs/misc_types.hh

index c139f1a..71fdd60 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -345,7 +345,7 @@
 Bitfield<0>  cp0;
 EndBitUnion(NSACR)

-BitUnion32(SCR)
+BitUnion64(SCR)
 Bitfield<21> fien;
 Bitfield<20> nmea;
 Bitfield<19> ease;

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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9928de3db61957404269d189a15a951fd6707c8a
Gerrit-Change-Number: 70720
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
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[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Extend auxiliary vector with AT_HWCAP2 entry

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70760?usp=email )


Change subject: arch-arm: Extend auxiliary vector with AT_HWCAP2 entry
..

arch-arm: Extend auxiliary vector with AT_HWCAP2 entry

The presence of some of the new extensions is reported via
the AT_HWCAP2 entry

Change-Id: I7a2d813ea84bf528b1f9df09121f9e97456a11c0
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70760
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/process.cc
M src/arch/arm/process.hh
2 files changed, 69 insertions(+), 4 deletions(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 02771ae..9b0f3b2 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -261,6 +261,62 @@
 return hwcap;
 }

+uint64_t
+ArmProcess64::armHwcapImpl2() const
+{
+enum ArmCpuFeature : uint64_t
+{
+Arm_None = 0,
+Arm_Dcpodp = 1ULL << 0,
+Arm_Sve2 = 1ULL<< 1,
+Arm_Sveaes = 1ULL << 2,
+Arm_Svepmull = 1ULL << 3,
+Arm_Svebitperm = 1ULL << 4,
+Arm_Svesha3 = 1ULL << 5,
+Arm_Svesm4 = 1ULL << 6,
+Arm_Flagm2 = 1ULL << 7,
+Arm_Frint = 1ULL << 8,
+Arm_Svei8mm = 1ULL << 9,
+Arm_Svef32mm = 1ULL << 10,
+Arm_Svef64mm = 1ULL << 11,
+Arm_Svebf16 = 1ULL << 12,
+Arm_I8mm = 1ULL << 13,
+Arm_Bf16 = 1ULL << 14,
+Arm_Dgh = 1ULL << 15,
+Arm_Rng = 1ULL << 16,
+Arm_Bti = 1ULL << 17,
+Arm_Mte = 1ULL << 18,
+Arm_Ecv = 1ULL << 19,
+Arm_Afp = 1ULL << 20,
+Arm_Rpres = 1ULL << 21,
+Arm_Mte3 = 1ULL << 22,
+Arm_Sme = 1ULL << 23,
+Arm_Sme_I16i64 = 1ULL << 24,
+Arm_Sme_F64f64 = 1ULL << 25,
+Arm_Sme_I8i32 = 1ULL << 26,
+Arm_Sme_F16f32 = 1ULL << 27,
+Arm_Sme_B16f32 = 1ULL << 28,
+Arm_Sme_F32f32 = 1ULL << 29,
+Arm_Sme_Fa64 = 1ULL << 30,
+Arm_Wfxt = 1ULL << 31,
+Arm_Ebf16 = 1ULL << 32,
+Arm_Sve_Ebf16 = 1ULL << 33,
+Arm_Cssc = 1ULL << 34,
+Arm_Rprfm = 1ULL << 35,
+Arm_Sve2p1 = 1ULL << 36,
+Arm_Sme2 = 1ULL << 37,
+Arm_Sme2p1 = 1ULL << 38,
+Arm_Sme_I16i32 = 1ULL << 39,
+Arm_Sme_Bi32i32 = 1ULL << 40,
+Arm_Sme_B16b16 = 1ULL << 41,
+Arm_Sme_F16f16 = 1ULL << 42
+};
+
+uint64_t hwcap = 0;
+
+return hwcap;
+}
+
 template 
 void
 ArmProcess::argsInit(int pageSize, const RegId &spId)
@@ -284,11 +340,10 @@
 if (elfObject) {

 if (objFile->getOpSys() == loader::Linux) {
-IntType features = armHwcap();
-
 //Bits which describe the system hardware capabilities
 //XXX Figure out what these should be
-auxv.emplace_back(gem5::auxv::Hwcap, features);
+auxv.emplace_back(gem5::auxv::Hwcap, armHwcap());
+auxv.emplace_back(gem5::auxv::Hwcap2, armHwcap2());
 //Frequency at which times() increments
 auxv.emplace_back(gem5::auxv::Clktck, 0x64);
 //Whether to enable "secure mode" in the executable
diff --git a/src/arch/arm/process.hh b/src/arch/arm/process.hh
index 6bdabef..0aee6dc 100644
--- a/src/arch/arm/process.hh
+++ b/src/arch/arm/process.hh
@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2012, 2018 ARM Limited
+* Copyright (c) 2012, 2018, 2023 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -69,10 +69,18 @@
 return static_cast(armHwcapImpl());
 }

+template
+IntType
+armHwcap2() const
+{
+return static_cast(armHwcapImpl2());
+}
+
 /**
  * AT_HWCAP is 32-bit wide on AArch64 as well so we can
  * safely return an uint32_t */
 virtual uint32_t armHwcapImpl() const = 0;
+virtual uint64_t armHwcapImpl2() const = 0;
 };

 class ArmProcess32 : public ArmProcess
@@ -86,6 +94,7 @@

 /** AArch32 AT_HWCAP */
 uint32_t armHwcapImpl() const override;
+uint64_t armHwcapImpl2() const override { return 0; }
 };

 class ArmProcess64 : public ArmProcess
@@ -99,6 +108,7 @@

 /** AArch64 AT_HWCAP */
 uint32_t armHwcapImpl() const override;
+uint64_t armHwcapImpl2() const override;
 };

 } // namespace gem5

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Gerrit-Change-Number: 70760
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Trava

[gem5-dev] [L] Change in gem5/gem5[develop]: arch-arm: Split decodeDataProcReg into subfunctions

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70717?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Split decodeDataProcReg into subfunctions
..

arch-arm: Split decodeDataProcReg into subfunctions

This will increase readibility, it will make it easier
for devs to add new instructions, and it removes some
duplication (some register indexes were read more than
once)

Change-Id: Ifa03a93cb73de0b2dc93d7784f9011e0e55dfc1e
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70717
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/isa/formats/aarch64.isa
1 file changed, 361 insertions(+), 309 deletions(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved




diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index 2fd28f8..0aafa9e 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -1958,6 +1958,359 @@
 output decoder {{
 namespace Aarch64
 {
+
+StaticInstPtr
+decodeLogical(ExtMachInst machInst)
+{
+uint8_t imm6 = bits(machInst, 15, 10);
+bool sf = bits(machInst, 31);
+if (!sf && (imm6 & 0x20))
+return new Unknown64(machInst);
+
+RegIndex rd = (RegIndex)(uint8_t)bits(machInst, 4, 0);
+RegIndex rdzr = makeZero(rd);
+RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5);
+RegIndex rm = (RegIndex)(uint8_t)bits(machInst, 20, 16);
+ArmShiftType type = (ArmShiftType)(uint8_t)bits(machInst, 23, 22);
+
+uint8_t switch_val = (bits(machInst, 21) << 0) |
+(bits(machInst, 30, 29) << 1);
+
+switch (switch_val) {
+  case 0x0:
+return new AndXSReg(machInst, rdzr, rn, rm, imm6, type);
+  case 0x1:
+return new BicXSReg(machInst, rdzr, rn, rm, imm6, type);
+  case 0x2:
+return new OrrXSReg(machInst, rdzr, rn, rm, imm6, type);
+  case 0x3:
+return new OrnXSReg(machInst, rdzr, rn, rm, imm6, type);
+  case 0x4:
+return new EorXSReg(machInst, rdzr, rn, rm, imm6, type);
+  case 0x5:
+return new EonXSReg(machInst, rdzr, rn, rm, imm6, type);
+  case 0x6:
+return new AndXSRegCc(machInst, rdzr, rn, rm, imm6, type);
+  case 0x7:
+return new BicXSRegCc(machInst, rdzr, rn, rm, imm6, type);
+  default:
+GEM5_UNREACHABLE;
+}
+}
+
+StaticInstPtr
+decodeAddSub(ExtMachInst machInst)
+{
+uint8_t switch_val = bits(machInst, 30, 29);
+if (bits(machInst, 21) == 0) {
+ArmShiftType type =
+(ArmShiftType)(uint8_t)bits(machInst, 23, 22);
+if (type == ROR)
+return new Unknown64(machInst);
+uint8_t imm6 = bits(machInst, 15, 10);
+if (!bits(machInst, 31) && bits(imm6, 5))
+return new Unknown64(machInst);
+RegIndex rd = (RegIndex)(uint8_t)bits(machInst, 4, 0);
+RegIndex rdzr = makeZero(rd);
+RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5);
+RegIndex rm = (RegIndex)(uint8_t)bits(machInst, 20, 16);
+switch (switch_val) {
+  case 0x0:
+return new AddXSReg(machInst, rdzr, rn, rm, imm6, type);
+  case 0x1:
+return new AddXSRegCc(machInst, rdzr, rn, rm, imm6, type);
+  case 0x2:
+return new SubXSReg(machInst, rdzr, rn, rm, imm6, type);
+  case 0x3:
+return new SubXSRegCc(machInst, rdzr, rn, rm, imm6, type);
+  default:
+GEM5_UNREACHABLE;
+}
+} else {
+if (bits(machInst, 23, 22) != 0 || bits(machInst, 12, 10) >  
0x4)

+   return new Unknown64(machInst);
+ArmExtendType type =
+(ArmExtendType)(uint8_t)bits(machInst, 15, 13);
+uint8_t imm3 = bits(machInst, 12, 10);
+RegIndex rd = (RegIndex)(uint8_t)bits(machInst, 4, 0);
+RegIndex rdsp = makeSP(rd);
+RegIndex rdzr = makeZero(rd);
+RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5);
+RegIndex rnsp = makeSP(rn);
+RegIndex rm = (RegIndex)(uint8_t)bits(machInst, 20, 16);
+
+switch (switch_val) {
+  case 0x0:
+return new AddXEReg(machInst, rdsp, rnsp, rm, type, imm3);
+  case 0x1:
+return new AddXERegCc(machInst, rdzr, rnsp, rm, type,  
imm3);

+  ca

[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Define remaining fields of the arm64 AT_HWCAP entry

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70758?usp=email )


Change subject: arch-arm: Define remaining fields of the arm64 AT_HWCAP  
entry

..

arch-arm: Define remaining fields of the arm64 AT_HWCAP entry

Change-Id: I4db4884d677f6d25417ae6edceb7f1e8dfad36cb
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70758
Reviewed-by: Richard Cooper 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/process.cc
1 file changed, 6 insertions(+), 2 deletions(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 9770ea6..6b5f69e 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012, 2017-2018 ARM Limited
+ * Copyright (c) 2010, 2012, 2017-2018, 2023 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -207,7 +207,11 @@
 Arm_Dit = 1 << 24,
 Arm_Uscat = 1 << 25,
 Arm_Ilrcpc = 1 << 26,
-Arm_Flagm = 1 << 27
+Arm_Flagm = 1 << 27,
+Arm_Sbss = 1 << 28,
+Arm_Sb = 1 << 29,
+Arm_Paca = 1 << 30,
+Arm_Pacg = 1 << 31
 };

 uint32_t hwcap = 0;

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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
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Gerrit-Change-Id: I4db4884d677f6d25417ae6edceb7f1e8dfad36cb
Gerrit-Change-Number: 70758
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Define a AA64ZFR0 data type

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70725?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Define a AA64ZFR0 data type
..

arch-arm: Define a AA64ZFR0 data type

Change-Id: I6b0dcf0c1882f356783934f625c2bc3a25fbb885
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70725
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/arch/arm/regs/misc_types.hh
1 file changed, 13 insertions(+), 0 deletions(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  kokoro: Regressions pass
  Jason Lowe-Power: Looks good to me, approved




diff --git a/src/arch/arm/regs/misc_types.hh  
b/src/arch/arm/regs/misc_types.hh

index 214d418..b7a1207 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -203,6 +203,19 @@
 Bitfield<3, 0> el0;
 EndBitUnion(AA64PFR0)

+BitUnion64(AA64ZFR0)
+Bitfield<59, 56> f64mm;
+Bitfield<55, 52> f32mm;
+Bitfield<47, 44> i8mm;
+Bitfield<43, 40> sm4;
+Bitfield<35, 32> sha3;
+Bitfield<27, 24> b16b16;
+Bitfield<23, 20> bf16;
+Bitfield<19, 16> bitPerm;
+Bitfield<7, 4> aes;
+Bitfield<3, 0> sveVer;
+EndBitUnion(AA64ZFR0)
+
 BitUnion64(AA64SMFR0)
 Bitfield<63> fa64;
 Bitfield<59, 56> smEver;

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Gerrit-MessageType: merged
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Gerrit-Change-Number: 70725
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
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Gerrit-Reviewer: kokoro 
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-arm: Improve debugging of CC regs accesses

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70718?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Improve debugging of CC regs accesses
..

arch-arm: Improve debugging of CC regs accesses

As of now we are simply printing the CC reg index which is
not particularly helpful. With this patch we actually print
the (NZ|C|V) reg name.

Change-Id: Ib4b56a372b25e5bc2b6b762d2ef3ff2084097cce
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70718
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/arm/regs/cc.hh
1 file changed, 23 insertions(+), 11 deletions(-)

Approvals:
  Richard Cooper: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/regs/cc.hh b/src/arch/arm/regs/cc.hh
index ba75527..474e48e 100644
--- a/src/arch/arm/regs/cc.hh
+++ b/src/arch/arm/regs/cc.hh
@@ -61,10 +61,31 @@
 NumRegs
 };

+const char * const RegName[NumRegs] = {
+"nz",
+"c",
+"v",
+"ge",
+"fp",
+"zero"
+};
+
 } // namespace cc_reg

-inline constexpr RegClass ccRegClass(CCRegClass, CCRegClassName,
-cc_reg::NumRegs, debug::CCRegs);
+class CCRegClassOps : public RegClassOps
+{
+  public:
+std::string
+regName(const RegId &id) const override
+{
+return cc_reg::RegName[id.index()];
+}
+};
+
+static inline CCRegClassOps ccRegClassOps;
+
+inline constexpr RegClass ccRegClass = RegClass(CCRegClass, CCRegClassName,
+cc_reg::NumRegs, debug::CCRegs).ops(ccRegClassOps);

 namespace cc_reg
 {
@@ -77,15 +98,6 @@
 Fp = ccRegClass[_FpIdx],
 Zero = ccRegClass[_ZeroIdx];

-const char * const RegName[NumRegs] = {
-"nz",
-"c",
-"v",
-"ge",
-"fp",
-"zero"
-};
-
 } // namespace cc_reg

 enum ConditionCode

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Gerrit-MessageType: merged
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Gerrit-Change-Id: Ib4b56a372b25e5bc2b6b762d2ef3ff2084097cce
Gerrit-Change-Number: 70718
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
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Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-arm: Rename AdvSIMD instruction pool

2023-05-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev 
Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70724?usp=email )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: arch-arm: Rename AdvSIMD instruction pool
..

arch-arm: Rename AdvSIMD instruction pool

The decoding function was wrongly named decodeNeon3SameExtra,
referring to the "AdvSIMD three same Extra" instruction pool

This might be an old name as I can only find the
"AdvSIMD *scalar* three same Extra" in the Arm arm. The
encoding space reserved to the pool bears the
"Advanced SIMD three-register extension" name; we
therefore rename the function to decodeNeon3RegExtension

Change-Id: I056da8f0c7808935d12a4b05490d30654178071f
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70724
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
---
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/neon64.isa
2 files changed, 4 insertions(+), 4 deletions(-)

Approvals:
  kokoro: Regressions pass
  Richard Cooper: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved




diff --git a/src/arch/arm/isa/formats/aarch64.isa  
b/src/arch/arm/isa/formats/aarch64.isa

index 9ad2de2..47d509e 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -2461,7 +2461,7 @@
 return new Unknown64(machInst);
 }
 } else if (bits(machInst, 15) == 1) {
-return decodeNeon3SameExtra(machInst);
+return decodeNeon3RegExtension(machInst);
 } else if (bits(machInst, 10) == 1) {
 if (bits(machInst, 23, 22))
 return new Unknown64(machInst);
diff --git a/src/arch/arm/isa/formats/neon64.isa  
b/src/arch/arm/isa/formats/neon64.isa

index 72b7e28..c200da7 100644
--- a/src/arch/arm/isa/formats/neon64.isa
+++ b/src/arch/arm/isa/formats/neon64.isa
@@ -39,9 +39,9 @@
 // AdvSIMD three same
 template 
 StaticInstPtr decodeNeon3Same(ExtMachInst machInst);
-// AdvSIMD three same Extra
+// AdvSIMD three register extension
 template 
-StaticInstPtr decodeNeon3SameExtra(ExtMachInst machInst);
+StaticInstPtr decodeNeon3RegExtension(ExtMachInst machInst);
 // AdvSIMD three different
 inline StaticInstPtr decodeNeon3Diff(ExtMachInst machInst);
 // AdvSIMD two-reg misc
@@ -507,7 +507,7 @@

 template 
 StaticInstPtr
-decodeNeon3SameExtra(ExtMachInst machInst)
+decodeNeon3RegExtension(ExtMachInst machInst)
 {
 uint8_t q  = bits(machInst, 30);
 uint8_t size   = bits(machInst, 23, 22);

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Gerrit-MessageType: merged
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Gerrit-Change-Id: I056da8f0c7808935d12a4b05490d30654178071f
Gerrit-Change-Number: 70724
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Richard Cooper 
Gerrit-Reviewer: kokoro 
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