[gem5-dev] [XS] Change in gem5/gem5[develop]: util: Add 'swapspace' daemon to runner VM.
Bobby Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/71680?usp=email ) Change subject: util: Add 'swapspace' daemon to runner VM. .. util: Add 'swapspace' daemon to runner VM. As these VMs, particularly the runners, don't have much memory, the 'swapspace' daemon allows for dynamic swap spaces to be created for when more memory is required. Change-Id: Ie8e734a8fde54e122df33dda187c6c4aafdcd006 --- M util/github-runners-vagrant/Vagrantfile-builder M util/github-runners-vagrant/Vagrantfile-runner 2 files changed, 6 insertions(+), 0 deletions(-) diff --git a/util/github-runners-vagrant/Vagrantfile-builder b/util/github-runners-vagrant/Vagrantfile-builder index cd36e78..c0c2380 100644 --- a/util/github-runners-vagrant/Vagrantfile-builder +++ b/util/github-runners-vagrant/Vagrantfile-builder @@ -20,6 +20,9 @@ # sets up vm config.vm.provision :shell, path: "provision_root.sh" config.vm.provision :shell, privileged: false, path: "provision_nonroot.sh" + # To ensure we don't run out of memory, we enable dynamic Swap Space. This is + # done via the "swapspace" daemon: https://pqxx.org/development/swapspace/ + config.vm.provision :shell, inline: "sudo apt install swapspace -y" # The provision_root.sh adds the vagrant user to the docker group, so we need to reload the VM. config.vm.provision :reload config.vm.provision :shell, run: 'always', inline: <<-SHELL diff --git a/util/github-runners-vagrant/Vagrantfile-runner b/util/github-runners-vagrant/Vagrantfile-runner index 854e5f5..eb4054e 100644 --- a/util/github-runners-vagrant/Vagrantfile-runner +++ b/util/github-runners-vagrant/Vagrantfile-runner @@ -20,6 +20,9 @@ # sets up vm config.vm.provision :shell, path: "provision_root.sh" config.vm.provision :shell, privileged: false, path: "provision_nonroot.sh" + # To ensure we don't run out of memory, we enable dynamic Swap Space. This is + # done via the "swapspace" daemon: https://pqxx.org/development/swapspace/ + config.vm.provision :shell, inline: "sudo apt install swapspace -y" # The provision_root.sh adds the vagrant user to the docker group, so we need to reload the VM. config.vm.provision :reload config.vm.provision :shell, run: 'always', inline: <<-SHELL -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/71680?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ie8e734a8fde54e122df33dda187c6c4aafdcd006 Gerrit-Change-Number: 71680 Gerrit-PatchSet: 1 Gerrit-Owner: Bobby Bruce ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[release-staging-v23-0]: python: Remove Python 'pipes' module
Bobby Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/71678?usp=email )
Change subject: python: Remove Python 'pipes' module
..
python: Remove Python 'pipes' module
This is scheduled for removal from Python in 3.13:
https://docs.python.org/3/library/pipes.html.
The 'shlex.quote' function can replace the 'pipes.quote' function used
in "main.py". A special wrapper has been made to account for the Windows
case which 'shlex.quote' doesn't handle.
Change-Id: I9c84605f0ccd8468b9cab6cece6248ef8c2107f0
---
M src/python/m5/main.py
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index a68279b..aaef8e1 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -489,10 +489,23 @@
% (socket.gethostname(), os.getpid())
)
-# in Python 3 pipes.quote() is moved to shlex.quote()
-import pipes
+def quote(arg: str) -> str:
+"""Quotes a string for printing in a shell. In addition to
Unix,
+this is designed to handle the problematic Windows cases where
+'shlex.quote' doesn't work"""
-print("command line:", " ".join(map(pipes.quote, sys.argv)))
+if os.name == "nt" and os.sep == "\\":
+# If a Windows machine, we manually quote the string.
+arg = arg.replace('"', '\\"')
+if re.search("\s", args):
+# We quote args which have whitespace.
+arg = '"' + arg + '"'
+return arg
+import shlex
+
+return shlex.quote(arg)
+
+print("command line:", " ".join(map(quote, sys.argv)))
print()
# check to make sure we can find the listed script
--
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[gem5-dev] [S] Change in gem5/gem5[release-staging-v23-0]: scons,stdlib: Remove deprecated 'distutils' module
Bobby Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/71679?usp=email )
Change subject: scons,stdlib: Remove deprecated 'distutils' module
..
scons,stdlib: Remove deprecated 'distutils' module
The Python module 'distutils' will be removed in Python 3.12:
https://docs.python.org/3/library/distutils.html
This patch removed usage of 'distutils' in the gem5 code base.
Change-Id: I1e3a96149f3cd6cbf4211a1565b5f74c85a0
---
M src/SConscript
M src/python/gem5/resources/client_api/client_wrapper.py
2 files changed, 22 insertions(+), 8 deletions(-)
diff --git a/src/SConscript b/src/SConscript
index d26bf49..1b44303 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -39,7 +39,7 @@
import collections
import copy
-import distutils.spawn
+from shutil import which
import itertools
import os
import os.path
@@ -269,7 +269,7 @@
'''Add a Protocol Buffer to build'''
Source(source, tags, add_tags,
append={'CXXFLAGS': '-Wno-array-bounds'})
-env['PROTOC_GRPC'] = distutils.spawn.find_executable('grpc_cpp_plugin')
+env['PROTOC_GRPC'] = which('grpc_cpp_plugin')
if env['PROTOC_GRPC']:
with Configure(env) as conf:
if (not env['HAVE_PKG_CONFIG'] or
diff --git a/src/python/gem5/resources/client_api/client_wrapper.py
b/src/python/gem5/resources/client_api/client_wrapper.py
index ebf1b8e..d2baabc 100644
--- a/src/python/gem5/resources/client_api/client_wrapper.py
+++ b/src/python/gem5/resources/client_api/client_wrapper.py
@@ -27,8 +27,7 @@
from .jsonclient import JSONClient
from .atlasclient import AtlasClient
from _m5 import core
-from typing import Optional, Dict, List
-from distutils.version import StrictVersion
+from typing import Optional, Dict, List, Tuple
import itertools
from m5.util import warn
@@ -247,12 +246,27 @@
:param resources: A list of resources to sort.
:return: A list of sorted resources.
"""
+
+def sort_tuple(resource: Dict) -> Tuple:
+"""This is used for sorting resources by ID and version. First
+the ID is sorted, then the version. In cases where the version
+contains periods, it's assumed this is to separate a
+"major.minor.hotfix" style versioning system. In which case,
the
+value separated in the most-significant position is sorted
before
+those less significant. If the value is a digit it is cast as
an
+int, otherwise, it is cast as a string, to lower-case.
+"""
+to_return = (resource["id"].lower(),)
+for val in resource["resource_version"].split("."):
+if val.isdigit():
+to_return += (int(val),)
+else:
+to_return += (str(val).lower(),)
+return to_return
+
return sorted(
resources,
-key=lambda resource: (
-resource["id"].lower(),
-StrictVersion(resource["resource_version"]),
-),
+key=lambda resource: sort_tuple(resource),
reverse=True,
)
--
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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-riscv: Fix unexpected behavior of float operations in Mac OS
Roger Chang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/71578?usp=email )
Change subject: arch-riscv: Fix unexpected behavior of float operations in
Mac OS
..
arch-riscv: Fix unexpected behavior of float operations in Mac OS
The uint_fast16_t is the integer at least 16 bits size, it can be
32, 64 bits and more. Usually most of the simulations are in the
x86-64 linux host, the size of uint_fast16_t is 64 bits. Therefore,
there is no problem for double precision float operations and it can
pass FloatMM test. However, in the Mac OS, the size of uint_fast16_t
is 16 bits, it will lose the upper bits when converting float
register bits to freg_t and it will generate unexpected results for
FloatMM test.
The change can guarantee that the size of data in freg_t is at least
64 bits and it will not lose any data from floating point to freg_t.
Reference:
https://developer.apple.com/documentation/kernel/uint_fast16_t
https://codebrowser.dev/glibc/glibc/stdlib/stdint.h.html
Change-Id: I3df6610f0903cdee0f56584d6cbdb51ac26c86c8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71578
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/riscv/regs/float.hh
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/regs/float.hh b/src/arch/riscv/regs/float.hh
index 1654bdb..4809372 100644
--- a/src/arch/riscv/regs/float.hh
+++ b/src/arch/riscv/regs/float.hh
@@ -105,7 +105,7 @@
static constexpr freg_t freg(float16_t f) { return {boxF16(f.v)}; }
static constexpr freg_t freg(float32_t f) { return {boxF32(f.v)}; }
static constexpr freg_t freg(float64_t f) { return f; }
-static constexpr freg_t freg(uint_fast16_t f) { return {f}; }
+static constexpr freg_t freg(uint_fast64_t f) { return {f}; }
namespace float_reg
{
--
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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3df6610f0903cdee0f56584d6cbdb51ac26c86c8
Gerrit-Change-Number: 71578
Gerrit-PatchSet: 3
Gerrit-Owner: Roger Chang
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Roger Chang
Gerrit-Reviewer: kokoro
Gerrit-CC: Yu-hsin Wang
Gerrit-CC: kokoro
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[gem5-dev] [XS] Change in gem5/gem5[develop]: python: Ignore -s as gem5 option
Jason Lowe-Power has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/71502?usp=email )
Change subject: python: Ignore -s as gem5 option
..
python: Ignore -s as gem5 option
This enables more compatibility with the normal python binary. This is
needed to get multiprocessing to work on some systems.
Change-Id: Ibb946136d153979bf54a773060010a0ae479a9d1
Signed-off-by: Jason Lowe-Power
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71502
Maintainer: Bobby Bruce
Tested-by: kokoro
Reviewed-by: Bobby Bruce
---
M src/python/m5/main.py
1 file changed, 7 insertions(+), 0 deletions(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index a68279b..4701dfa 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -193,6 +193,13 @@
callback=collect_args,
)
+option(
+"-s",
+action="store_true",
+help="IGNORED, only for compatibility with python. don't"
+"add user site directory to sys.path; also PYTHONNOUSERSITE",
+)
+
# Statistics options
group("Statistics Options")
option(
--
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Gerrit-Project: public/gem5
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Gerrit-Change-Id: Ibb946136d153979bf54a773060010a0ae479a9d1
Gerrit-Change-Number: 71502
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-CC: kokoro
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[gem5-dev] [S] Change in gem5/gem5[develop]: tests: Add OctopiCache to long tests
Hoa Nguyen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/71619?usp=email ) Change subject: tests: Add OctopiCache to long tests .. tests: Add OctopiCache to long tests Change-Id: I40c948023a28f9bf4dde4de214bdd68894050317 Signed-off-by: Hoa Nguyen --- M tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py 1 file changed, 19 insertions(+), 0 deletions(-) diff --git a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py index e43d461..aa8be15 100644 --- a/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py +++ b/tests/gem5/gem5_library_example_tests/test_gem5_library_examples.py @@ -292,6 +292,25 @@ ) gem5_verify_config( +name="test-gem5-library-example-octopi-cache-test", +fixtures=(), +verifiers=(), +config=joinpath( +config.base_dir, +"configs", +"example", +"gem5_library", +"caches", +"octopi-cache-example.py", +), +config_args=[], +protocol="MESI_Three_Level", +valid_isas=(constants.all_compiled_tag,), +valid_hosts=constants.supported_hosts, +length=constants.long_tag, +) + +gem5_verify_config( name="test-gem5-library-example-riscvmatched-hello", fixtures=(), verifiers=(), -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/71619?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I40c948023a28f9bf4dde4de214bdd68894050317 Gerrit-Change-Number: 71619 Gerrit-PatchSet: 1 Gerrit-Owner: Hoa Nguyen ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [M] Change in gem5/gem5[develop]: configs: Add example configuration for OctopiCache
Hoa Nguyen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/71618?usp=email )
Change subject: configs: Add example configuration for OctopiCache
..
configs: Add example configuration for OctopiCache
Change-Id: Ia78dd63e63808ebad40052d2a7cdb67cc7179e44
Signed-off-by: Hoa Nguyen
---
A configs/example/gem5_library/caches/octopi-cache-example.py
1 file changed, 95 insertions(+), 0 deletions(-)
diff --git a/configs/example/gem5_library/caches/octopi-cache-example.py
b/configs/example/gem5_library/caches/octopi-cache-example.py
new file mode 100644
index 000..5bfe536
--- /dev/null
+++ b/configs/example/gem5_library/caches/octopi-cache-example.py
@@ -0,0 +1,95 @@
+# Copyright (c) 2023 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+This script boots Ubuntu 20.04 with 8 timing cores in 1 CCD.
+
+Usage
+-
+
+```
+scons build/ARM_MESI_Three_Level/gem5.opt
+./build/ARM_MESI_Three_Level/gem5.opt
configs/example/gem5_library/caches/octopi-cache-example.py
+```
+"""
+
+
+import m5
+from m5.objects import Root
+
+from gem5.utils.requires import requires
+from gem5.components.boards.arm_board import ArmBoard
+from gem5.components.memory import DualChannelDDR4_2400
+from gem5.components.processors.simple_processor import SimpleProcessor
+from gem5.components.processors.cpu_types import CPUTypes
+from gem5.components.cachehierarchies.ruby.caches.mesi_three_level.Octopi
import (
+OctopiCache,
+)
+from gem5.isas import ISA
+from gem5.coherence_protocol import CoherenceProtocol
+from gem5.resources.resource import Resource, CustomResource,
DiskImageResource
+from gem5.simulate.simulator import Simulator
+from gem5.resources.workload import Workload
+
+num_core_complexes = 1 # CCDs
+num_cores_per_core_complexes = 8 # 8 cores/CCD
+
+# OctopiCache is built on top of the gem5's MESI_Three_Level cache
coherence protocol
+requires(coherence_protocol_required=CoherenceProtocol.MESI_THREE_LEVEL)
+cache_hierarchy = OctopiCache(
+l1i_size="32KiB",
+l1i_assoc=8,
+l1d_size="32KiB",
+l1d_assoc=8,
+l2_size="512KiB",
+l2_assoc=8,
+l3_size="32MiB",
+l3_assoc=16,
+num_core_complexes=1,
+is_fullsystem=True,
+)
+
+memory = DualChannelDDR4_2400(size="16GB")
+
+# The number of cores must be consistent with
+# num_core_complexes and num_cores_per_core_complexes
+processor = SimpleProcessor(
+cpu_type=CPUTypes.TIMING,
+isa=ISA.ARM,
+num_cores=num_core_complexes * num_cores_per_core_complexes,
+)
+
+board = ArmBoard(
+clk_freq="4GHz",
+processor=processor,
+memory=memory,
+cache_hierarchy=cache_hierarchy,
+)
+
+board.set_workload(Workload("arm64-ubuntu-20.04-boot"))
+
+simulator = Simulator(board=board)
+simulator.run()
--
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[gem5-dev] [L] Change in gem5/gem5[develop]: stdlib: Add a prebuilt MESI_Three_Level cache
Hoa Nguyen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/71598?usp=email )
Change subject: stdlib: Add a prebuilt MESI_Three_Level cache
..
stdlib: Add a prebuilt MESI_Three_Level cache
The cache is modeled after an AMD EPYC cache, but not exactly
like AMD EPYC cache.
- K cores per core complex (CCD), each core has one private split L1,
and one private L2.
- K cores in the same CCD share 1 slice of L3 cache, which is not
a victim cache.
- There can be multiple CCDs, which communicate with each other via
Cross-CCD router. The Cross-CCD rounter is also connected to
directory controllers and dma controllers.
- All links latency are set to 1.
Change-Id: Ib64248bed9155b8e48e5158ffdeebf1f2d770754
Signed-off-by: Hoa Nguyen
---
M src/python/SConscript
A
src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/Octopi.py
A
src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/__init__.py
A
src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/core_complex.py
A
src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/octopi_network.py
A
src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/ruby_network_components.py
M
src/python/gem5/components/cachehierarchies/ruby/mesi_three_level_cache_hierarchy.py
7 files changed, 616 insertions(+), 1 deletion(-)
diff --git a/src/python/SConscript b/src/python/SConscript
index f98b570..47901fd 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -154,6 +154,18 @@
PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
'gem5/components/cachehierarchies/ruby/caches/mesi_three_level/'
'l3_cache.py')
+PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
+'gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/'
+'Octopi.py')
+PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
+'gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/'
+'core_complex.py')
+PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
+'gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/'
+'octopi_network.py')
+PySource('gem5.components.cachehierarchies.ruby.caches.mesi_three_level',
+'gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/'
+'ruby_network_components.py')
PySource('gem5.components.cachehierarchies.ruby.caches.mi_example',
'gem5/components/cachehierarchies/ruby/caches/mi_example/__init__.py')
PySource('gem5.components.cachehierarchies.ruby.caches.mi_example',
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/Octopi.py
b/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/Octopi.py
new file mode 100644
index 000..96a68da
--- /dev/null
+++
b/src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/Octopi.py
@@ -0,0 +1,237 @@
+from ...abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy
+from abstract_three_level_cache_hierarchy import (
+AbstractThreeLevelCacheHierarchy,
+)
+from ..coherence_protocol import CoherenceProtocol
+from ..isas import ISA
+from ..components.boards.abstract_board import AbstractBoard
+from ..utils.requires import requires
+
+from ..components.cachehierarchies.ruby.caches.mesi_three_level.directory
import
(
+Directory,
+)
+from ..components.cachehierarchies.ruby.caches.mesi_three_level.dma_controller
import
(
+DMAController,
+)
+
+from m5.objects import RubySystem, DMASequencer, RubyPortProxy
+
+from .core_complex import CoreComplex
+from .octopi_network import OctopiNetwork
+from .ruby_network_components import (
+RubyNetworkComponent,
+RubyRouter,
+RubyExtLink,
+RubyIntLink,
+)
+
+# CoreComplex sub-systems own the L1, L2, L3 controllers
+# OctopiCache owns the directory controllers
+# RubySystem owns the DMA Controllers
+class OctopiCache(
+AbstractRubyCacheHierarchy, AbstractThreeLevelCacheHierarchy
+):
+def __init__(
+self,
+l1i_size: str,
+l1i_assoc: int,
+l1d_size: str,
+l1d_assoc: int,
+l2_size: str,
+l2_assoc: int,
+l3_size: str,
+l3_assoc: int,
+num_core_complexes: int,
+is_fullsystem: bool,
+):
+AbstractRubyCacheHierarchy.__init__(self=self)
+AbstractThreeLevelCacheHierarchy.__init__(
+self=self,
+l1i_size=l1i_size,
+l1i_assoc=l1i_assoc,
+l1d_size=l1d_size,
+l1d_assoc=l1d_assoc,
+l2_size=l2_size,
+l2_assoc=l2_assoc,
+l3_size=l3_size,
+l3_assoc=l3_assoc,
+)
+
+self._directory_controllers = []
+
[gem5-dev] [XS] Change in gem5/gem5[release-staging-v23-0]: python: Ignore -s as gem5 option
Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/71518?usp=email )
Change subject: python: Ignore -s as gem5 option
..
python: Ignore -s as gem5 option
This enables more compatibility with the normal python binary. This is
needed to get multiprocessing to work on some systems.
Change-Id: Ibb946136d153979bf54a773060010a0ae479a9d1
Signed-off-by: Jason Lowe-Power
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71518
Maintainer: Bobby Bruce
Reviewed-by: Bobby Bruce
Tested-by: kokoro
---
M src/python/m5/main.py
1 file changed, 7 insertions(+), 0 deletions(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index a68279b..4701dfa 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -193,6 +193,13 @@
callback=collect_args,
)
+option(
+"-s",
+action="store_true",
+help="IGNORED, only for compatibility with python. don't"
+"add user site directory to sys.path; also PYTHONNOUSERSITE",
+)
+
# Statistics options
group("Statistics Options")
option(
--
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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v23-0
Gerrit-Change-Id: Ibb946136d153979bf54a773060010a0ae479a9d1
Gerrit-Change-Number: 71518
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby Bruce
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: kokoro
Gerrit-CC: kokoro
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[gem5-dev] [S] Change in gem5/gem5[release-staging-v23-0]: arch-riscv: fix load reserved store conditional
Bobby Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/71520?usp=email )
Change subject: arch-riscv: fix load reserved store conditional
..
arch-riscv: fix load reserved store conditional
* According to the manual, load reservations must be cleared on a
failed or a successful SC attempt.
* A load reservation can be arbitrarily large. The current
implementation was reserving something different than cacheBlockSize
which could lead to problems if snoop addresses are cache block
aligned. This patch implementation assumes a cacheBlock granularity.
* Load reservations should also be cleared on faults
Change-Id: I64513534710b5f269260fcb204f717801913e2f5
---
M src/arch/generic/isa.hh
M src/arch/riscv/faults.cc
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
4 files changed, 34 insertions(+), 11 deletions(-)
diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index e9e4d95..2e7e38d 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -70,6 +70,7 @@
public:
virtual PCStateBase *newPCState(Addr new_inst_addr=0) const = 0;
virtual void clear() {}
+virtual void clearLoadReservation(ContextID cid) = 0;
virtual RegVal readMiscRegNoEffect(RegIndex idx) const = 0;
virtual RegVal readMiscReg(RegIndex idx) = 0;
diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 940f710..8fb8f81 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -153,6 +153,9 @@
tc->setMiscReg(MISCREG_NMIE, 0);
}
+// Clear load reservation address
+tc->getIsaPtr()->clearLoadReservation(tc->contextId());
+
// Set PC to fault handler address
Addr addr = mbits(tc->readMiscReg(tvec), 63, 2);
if (isInterrupt() && bits(tc->readMiscReg(tvec), 1, 0) == 1)
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index d744fe36..94a8239 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -672,11 +672,6 @@
UNSERIALIZE_CONTAINER(miscRegFile);
}
-const int WARN_FAILURE = 1;
-
-const Addr INVALID_RESERVATION_ADDR = (Addr) -1;
-std::unordered_map load_reservation_addrs;
-
void
ISA::handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask)
{
@@ -696,9 +691,9 @@
{
Addr& load_reservation_addr = load_reservation_addrs[tc->contextId()];
-load_reservation_addr = req->getPaddr() & ~0xF;
+load_reservation_addr = req->getPaddr();
DPRINTF(LLSC, "[cid:%d]: Reserved address %x.\n",
-req->contextId(), req->getPaddr() & ~0xF);
+req->contextId(), req->getPaddr());
}
bool
@@ -717,12 +712,13 @@
lr_addr_empty ? "yes" : "no");
if (!lr_addr_empty) {
DPRINTF(LLSC, "[cid:%d]: addr = %x.\n", req->contextId(),
-req->getPaddr() & ~0xF);
+req->getPaddr() & cacheBlockMask);
DPRINTF(LLSC, "[cid:%d]: last locked addr = %x.\n",
req->contextId(),
-load_reservation_addr);
+load_reservation_addr & cacheBlockMask);
}
-if (lr_addr_empty
-|| load_reservation_addr != ((req->getPaddr() & ~0xF))) {
+if (lr_addr_empty ||
+(load_reservation_addr & cacheBlockMask)
+!= ((req->getPaddr() & cacheBlockMask))) {
req->setExtraData(0);
int stCondFailures = tc->readStCondFailures();
tc->setStCondFailures(++stCondFailures);
@@ -730,12 +726,21 @@
warn("%i: context %d: %d consecutive SC failures.\n",
curTick(), tc->contextId(), stCondFailures);
}
+
+// Must clear any reservations
+load_reservation_addr = INVALID_RESERVATION_ADDR;
+
return false;
}
if (req->isUncacheable()) {
req->setExtraData(2);
}
+// Must clear any reservations
+load_reservation_addr = INVALID_RESERVATION_ADDR;
+
+DPRINTF(LLSC, "[cid:%d]: SC success! Current locked addr = %x.\n",
+req->contextId(), load_reservation_addr & cacheBlockMask);
return true;
}
@@ -743,6 +748,8 @@
ISA::globalClearExclusive()
{
tc->getCpuPtr()->wakeup(tc->threadId());
+Addr& load_reservation_addr = load_reservation_addrs[tc->contextId()];
+load_reservation_addr = INVALID_RESERVATION_ADDR;
}
void
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 5a2a610..7ef5c52 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -76,6 +76,11 @@
bool hpmCounterEnabled(int counter) const;
+// Load reserve - store conditional monitor
+const int WARN_FAILURE = 1;
+const Addr INVALID_RESERVATION_ADDR = (Addr)-1;
+std::unordered_map load_reservation_addrs;
+
public:
using Params = RiscvISAParams;
@@ -87,6 +92,13 @@
return new PCState(new_inst_addr, rv_type);
}
+void
+clearLoadReservation(ContextID cid) override
+{
+
[gem5-dev] [XS] Change in gem5/gem5[release-staging-v23-0]: arch-riscv: Fix unexpected behavior of float operations in Mac OS
Bobby Bruce has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/71519?usp=email )
Change subject: arch-riscv: Fix unexpected behavior of float operations in
Mac OS
..
arch-riscv: Fix unexpected behavior of float operations in Mac OS
The uint_fast16_t is the integer at least 16 bits size, it can be
32, 64 bits and more. Usually most of the simulations are in the
x86-64 linux host, the size of uint_fast16_t is 64 bits. Therefore,
there is no problem for double precision float operations and it can
pass FloatMM test. However, in the Mac OS, the size of uint_fast16_t
is 16 bits, it will lose the upper bits when converting float
register bits to freg_t and it will generate unexpected results for
FloatMM test.
The change can guarantee that the size of data in freg_t is at least
64 bits and it will not lose any data from floating point to freg_t.
Reference:
https://developer.apple.com/documentation/kernel/uint_fast16_t
https://codebrowser.dev/glibc/glibc/stdlib/stdint.h.html
Change-Id: I3df6610f0903cdee0f56584d6cbdb51ac26c86c8
---
M src/arch/riscv/regs/float.hh
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/arch/riscv/regs/float.hh b/src/arch/riscv/regs/float.hh
index 1654bdb..4809372 100644
--- a/src/arch/riscv/regs/float.hh
+++ b/src/arch/riscv/regs/float.hh
@@ -105,7 +105,7 @@
static constexpr freg_t freg(float16_t f) { return {boxF16(f.v)}; }
static constexpr freg_t freg(float32_t f) { return {boxF32(f.v)}; }
static constexpr freg_t freg(float64_t f) { return f; }
-static constexpr freg_t freg(uint_fast16_t f) { return {f}; }
+static constexpr freg_t freg(uint_fast64_t f) { return {f}; }
namespace float_reg
{
--
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Gerrit-Project: public/gem5
Gerrit-Branch: release-staging-v23-0
Gerrit-Change-Id: I3df6610f0903cdee0f56584d6cbdb51ac26c86c8
Gerrit-Change-Number: 71519
Gerrit-PatchSet: 1
Gerrit-Owner: Bobby Bruce
Gerrit-CC: Roger Chang
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[gem5-dev] [XS] Change in gem5/gem5[stable]: misc: Add 'synchronize' as CI Test action. Remove 'reopen'
Bobby Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/71503?usp=email ) Change subject: misc: Add 'synchronize' as CI Test action. Remove 'reopen' .. misc: Add 'synchronize' as CI Test action. Remove 'reopen' 'synchronize' will re-run the tests everytime the pull-request is updated, inclusive of rebasing. 'reopen' seems pointless as reopening does not change the pull-request functionality. Change-Id: I24c2686e19a8b0901323e9bd794142994dc2a87c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71503 Maintainer: Bobby Bruce Reviewed-by: Jason Lowe-Power Tested-by: kokoro --- M .github/workflows/ci-tests.yaml 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: Jason Lowe-Power: Looks good to me, approved kokoro: Regressions pass Bobby Bruce: Looks good to me, approved diff --git a/.github/workflows/ci-tests.yaml b/.github/workflows/ci-tests.yaml index 16c096d..4c35c1a 100644 --- a/.github/workflows/ci-tests.yaml +++ b/.github/workflows/ci-tests.yaml @@ -5,7 +5,8 @@ on: pull_request: -types: [opened, reopened, edited] +types: [opened, edited, synchronize] + jobs: pre-commit: -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/71503?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: public/gem5 Gerrit-Branch: stable Gerrit-Change-Id: I24c2686e19a8b0901323e9bd794142994dc2a87c Gerrit-Change-Number: 71503 Gerrit-PatchSet: 2 Gerrit-Owner: Bobby Bruce Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Melissa Jost Gerrit-Reviewer: kokoro Gerrit-CC: kokoro ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [XS] Change in gem5/gem5[stable]: misc: Remove 'run-name' from workflow yaml files
Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/71505?usp=email )
Change subject: misc: Remove 'run-name' from workflow yaml files
..
misc: Remove 'run-name' from workflow yaml files
This field is not necessary and was not a helpful description of the
run.
Change-Id: I078481920833fb36099e6c30295c0b60ac0ee3a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71505
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Maintainer: Bobby Bruce
---
M .github/workflows/ci-tests.yaml
M .github/workflows/daily-tests.yaml
M .github/workflows/weekly-tests.yaml
3 files changed, 0 insertions(+), 5 deletions(-)
Approvals:
Bobby Bruce: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/.github/workflows/ci-tests.yaml
b/.github/workflows/ci-tests.yaml
index 4c35c1a..b1c5a1a 100644
--- a/.github/workflows/ci-tests.yaml
+++ b/.github/workflows/ci-tests.yaml
@@ -1,7 +1,6 @@
# This workflow runs after a pull-request has been approved by a reviewer.
name: CI Tests
-run-name: ${{ github.actor }} is running the pull-request continuous
integration tests
on:
pull_request:
diff --git a/.github/workflows/daily-tests.yaml
b/.github/workflows/daily-tests.yaml
index 2b8a15f..5fab058 100644
--- a/.github/workflows/daily-tests.yaml
+++ b/.github/workflows/daily-tests.yaml
@@ -1,8 +1,6 @@
# This workflow runs all of the long tests within main.py, extra tests in
nightly.sh, and unittests
name: Daily Tests
-run-name: ${{ github.actor }} is running the daily tests
-
on:
# Runs every day from 7AM UTC
diff --git a/.github/workflows/weekly-tests.yaml
b/.github/workflows/weekly-tests.yaml
index 600449e..4c3f6b5 100644
--- a/.github/workflows/weekly-tests.yaml
+++ b/.github/workflows/weekly-tests.yaml
@@ -1,8 +1,6 @@
# This workflow runs all of the very-long tests within main.py
name: Weekly Tests
-run-name: ${{ github.actor }} is running the weekly tests
-
on:
# Runs every Sunday from 7AM UTC
--
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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: stable
Gerrit-Change-Id: I078481920833fb36099e6c30295c0b60ac0ee3a0
Gerrit-Change-Number: 71505
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby Bruce
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Melissa Jost
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[gem5-dev] [XS] Change in gem5/gem5[stable]: misc: Update GitHub Actions Workflow names
Bobby Bruce has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/71504?usp=email )
Change subject: misc: Update GitHub Actions Workflow names
..
misc: Update GitHub Actions Workflow names
Change-Id: Iaf4cbdf7a8edd2b9ae00308ae41f6fa805ab9446
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71504
Maintainer: Bobby Bruce
Tested-by: kokoro
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
---
M .github/workflows/compiler-tests.yaml
M .github/workflows/daily-tests.yaml
M .github/workflows/weekly-tests.yaml
3 files changed, 3 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Bobby Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/.github/workflows/compiler-tests.yaml
b/.github/workflows/compiler-tests.yaml
index 8720e6d..013a710 100644
--- a/.github/workflows/compiler-tests.yaml
+++ b/.github/workflows/compiler-tests.yaml
@@ -1,6 +1,6 @@
# This workflow runs all of the compiler tests
-name: Running main.py
+name: Compiler Tests
run-name: ${{ github.actor }} is running compiler tests
diff --git a/.github/workflows/daily-tests.yaml
b/.github/workflows/daily-tests.yaml
index 97b4164..2b8a15f 100644
--- a/.github/workflows/daily-tests.yaml
+++ b/.github/workflows/daily-tests.yaml
@@ -1,6 +1,6 @@
# This workflow runs all of the long tests within main.py, extra tests in
nightly.sh, and unittests
-name: Running main.py
+name: Daily Tests
run-name: ${{ github.actor }} is running the daily tests
diff --git a/.github/workflows/weekly-tests.yaml
b/.github/workflows/weekly-tests.yaml
index 64ab442..600449e 100644
--- a/.github/workflows/weekly-tests.yaml
+++ b/.github/workflows/weekly-tests.yaml
@@ -1,6 +1,6 @@
# This workflow runs all of the very-long tests within main.py
-name: Running weekly main.py
+name: Weekly Tests
run-name: ${{ github.actor }} is running the weekly tests
--
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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: stable
Gerrit-Change-Id: Iaf4cbdf7a8edd2b9ae00308ae41f6fa805ab9446
Gerrit-Change-Number: 71504
Gerrit-PatchSet: 2
Gerrit-Owner: Bobby Bruce
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Melissa Jost
Gerrit-Reviewer: kokoro
Gerrit-CC: kokoro
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[gem5-dev] [XS] Change in gem5/gem5[develop]: arch-riscv: Fix unexpected behavior of float operations in Mac OS
Roger Chang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/71578?usp=email )
Change subject: arch-riscv: Fix unexpected behavior of float operations in
Mac OS
..
arch-riscv: Fix unexpected behavior of float operations in Mac OS
The uint_fast16_t is the integer at least 16 bits size, it can be
32, 64 bits and more. Usually most of the simulations are in the
x86-64 linux host, the size of uint_fast16_t is 64 bits. Therefore,
there is no problem for double precision float operations and it can
pass FloatMM test. However, in the Mac OS, the size of uint_fast16_t
is 16 bits, it will lose the upper bits when converting float
register bits to freg_t and it will generate unexpected results for
FloatMM test.
The change can guarantee that the size of data in freg_t is at least
64 bits and it will not lose any data from floating point to freg_t.
Reference:
https://developer.apple.com/documentation/kernel/uint_fast16_t
https: //codebrowser.dev/glibc/glibc/stdlib/stdint.h.html
Change-Id: I3df6610f0903cdee0f56584d6cbdb51ac26c86c8
---
M src/arch/riscv/regs/float.hh
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/arch/riscv/regs/float.hh b/src/arch/riscv/regs/float.hh
index 1654bdb..4809372 100644
--- a/src/arch/riscv/regs/float.hh
+++ b/src/arch/riscv/regs/float.hh
@@ -105,7 +105,7 @@
static constexpr freg_t freg(float16_t f) { return {boxF16(f.v)}; }
static constexpr freg_t freg(float32_t f) { return {boxF32(f.v)}; }
static constexpr freg_t freg(float64_t f) { return f; }
-static constexpr freg_t freg(uint_fast16_t f) { return {f}; }
+static constexpr freg_t freg(uint_fast64_t f) { return {f}; }
namespace float_reg
{
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I3df6610f0903cdee0f56584d6cbdb51ac26c86c8
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[gem5-dev] [S] Change in gem5/gem5[develop]: arch-riscv: fix load reserved store conditional
Adrià Armejach has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/71558?usp=email )
Change subject: arch-riscv: fix load reserved store conditional
..
arch-riscv: fix load reserved store conditional
* According to the manual, load reservations must be cleared on a
failed or a successful SC attempt.
* A load reservation can be arbitrarily large. The current
implementation was reserving something different than cacheBlockSize
which could lead to problems if snoop addresses are cache block
aligned. This patch implementation assumes a cacheBlock granularity.
* Load reservations should also be cleared on faults
Change-Id: I64513534710b5f269260fcb204f717801913e2f5
---
M src/arch/generic/isa.hh
M src/arch/riscv/faults.cc
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
4 files changed, 34 insertions(+), 11 deletions(-)
diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index e9e4d95..2e7e38d 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -70,6 +70,7 @@
public:
virtual PCStateBase *newPCState(Addr new_inst_addr=0) const = 0;
virtual void clear() {}
+virtual void clearLoadReservation(ContextID cid) = 0;
virtual RegVal readMiscRegNoEffect(RegIndex idx) const = 0;
virtual RegVal readMiscReg(RegIndex idx) = 0;
diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index 940f710..8fb8f81 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -153,6 +153,9 @@
tc->setMiscReg(MISCREG_NMIE, 0);
}
+// Clear load reservation address
+tc->getIsaPtr()->clearLoadReservation(tc->contextId());
+
// Set PC to fault handler address
Addr addr = mbits(tc->readMiscReg(tvec), 63, 2);
if (isInterrupt() && bits(tc->readMiscReg(tvec), 1, 0) == 1)
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index d744fe36..94a8239 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -672,11 +672,6 @@
UNSERIALIZE_CONTAINER(miscRegFile);
}
-const int WARN_FAILURE = 1;
-
-const Addr INVALID_RESERVATION_ADDR = (Addr) -1;
-std::unordered_map load_reservation_addrs;
-
void
ISA::handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask)
{
@@ -696,9 +691,9 @@
{
Addr& load_reservation_addr = load_reservation_addrs[tc->contextId()];
-load_reservation_addr = req->getPaddr() & ~0xF;
+load_reservation_addr = req->getPaddr();
DPRINTF(LLSC, "[cid:%d]: Reserved address %x.\n",
-req->contextId(), req->getPaddr() & ~0xF);
+req->contextId(), req->getPaddr());
}
bool
@@ -717,12 +712,13 @@
lr_addr_empty ? "yes" : "no");
if (!lr_addr_empty) {
DPRINTF(LLSC, "[cid:%d]: addr = %x.\n", req->contextId(),
-req->getPaddr() & ~0xF);
+req->getPaddr() & cacheBlockMask);
DPRINTF(LLSC, "[cid:%d]: last locked addr = %x.\n",
req->contextId(),
-load_reservation_addr);
+load_reservation_addr & cacheBlockMask);
}
-if (lr_addr_empty
-|| load_reservation_addr != ((req->getPaddr() & ~0xF))) {
+if (lr_addr_empty ||
+(load_reservation_addr & cacheBlockMask)
+!= ((req->getPaddr() & cacheBlockMask))) {
req->setExtraData(0);
int stCondFailures = tc->readStCondFailures();
tc->setStCondFailures(++stCondFailures);
@@ -730,12 +726,21 @@
warn("%i: context %d: %d consecutive SC failures.\n",
curTick(), tc->contextId(), stCondFailures);
}
+
+// Must clear any reservations
+load_reservation_addr = INVALID_RESERVATION_ADDR;
+
return false;
}
if (req->isUncacheable()) {
req->setExtraData(2);
}
+// Must clear any reservations
+load_reservation_addr = INVALID_RESERVATION_ADDR;
+
+DPRINTF(LLSC, "[cid:%d]: SC success! Current locked addr = %x.\n",
+req->contextId(), load_reservation_addr & cacheBlockMask);
return true;
}
@@ -743,6 +748,8 @@
ISA::globalClearExclusive()
{
tc->getCpuPtr()->wakeup(tc->threadId());
+Addr& load_reservation_addr = load_reservation_addrs[tc->contextId()];
+load_reservation_addr = INVALID_RESERVATION_ADDR;
}
void
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 5a2a610..7ef5c52 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -76,6 +76,11 @@
bool hpmCounterEnabled(int counter) const;
+// Load reserve - store conditional monitor
+const int WARN_FAILURE = 1;
+const Addr INVALID_RESERVATION_ADDR = (Addr)-1;
+std::unordered_map load_reservation_addrs;
+
public:
using Params = RiscvISAParams;
@@ -87,6 +92,13 @@
return new PCState(new_inst_addr, rv_type);
}
+void
+clearLoadReservation(ContextID cid) override
+{
+
[gem5-dev] [M] Change in gem5/gem5[develop]: mem: port: add TracingExtension for debug purpose
Yan Lee has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/71538?usp=email )
Change subject: mem: port: add TracingExtension for debug purpose
..
mem: port: add TracingExtension for debug purpose
TracingExtension contains a stack recording the port names
passed through of the Packet. The target receiving the Packet
can dump out the whole path of this Packet for the debug purpose.
This mechanism can be enabled with the debug flag PortTrace.
Change-Id: Ic11e708b35fdddc4f4b786d91b35fd4def08948c
---
M src/mem/SConscript
M src/mem/port.cc
M src/mem/port.hh
3 files changed, 92 insertions(+), 6 deletions(-)
diff --git a/src/mem/SConscript b/src/mem/SConscript
index 351f24e..6e017e0 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -151,6 +151,7 @@
DebugFlag('MMU')
DebugFlag('MemoryAccess')
DebugFlag('PacketQueue')
+DebugFlag("PortTrace")
DebugFlag('ResponsePort')
DebugFlag('StackDist')
DebugFlag("DRAMSim2")
diff --git a/src/mem/port.cc b/src/mem/port.cc
index 2a253b9..2f754c8 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -45,6 +45,7 @@
#include "mem/port.hh"
#include "base/trace.hh"
+#include "debug/PortTrace.hh"
#include "debug/ResponsePort.hh"
#include "sim/sim_object.hh"
@@ -186,6 +187,29 @@
sendFunctional();
}
+void
+RequestPort::addTrace(PacketPtr pkt) const
+{
+if (!gem5::debug::PortTrace || !pkt)
+return;
+auto ext = pkt->getExtension();
+if (!ext) {
+ext = std::make_shared();
+pkt->setExtension(ext);
+}
+ext->add(name(), _responsePort->name());
+}
+
+void
+RequestPort::removeTrace(PacketPtr pkt) const
+{
+if (!gem5::debug::PortTrace || !pkt)
+return;
+auto ext = pkt->getExtension();
+panic_if(!ext, "There is no TracingExtension in the packet.");
+ext->remove();
+}
+
/**
* Response port
*/
diff --git a/src/mem/port.hh b/src/mem/port.hh
index a3acffc..2555706 100644
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -46,6 +46,10 @@
#ifndef __MEM_PORT_HH__
#define __MEM_PORT_HH__
+#include
+#include
+#include
+
#include "base/addr_range.hh"
#include "mem/packet.hh"
#include "mem/protocol/atomic.hh"
@@ -65,6 +69,43 @@
class ResponsePort;
/**
+ * TracingExtension is an Extension of the Packet for recording the trace
+ * of the Packet. The stack in the TracingExtension holds the name of the
+ * ports that the Packet has passed through.
+ */
+class TracingExtension : public gem5::Extension
+{
+ public:
+ TracingExtension() = default;
+ TracingExtension(const std::stack& q) { trace_ = q; }
+
+ std::unique_ptr clone() const override
+ {
+ return std::make_unique(trace_);
+ }
+
+ void
+ add(std::string request_port, std::string response_port)
+ {
+ trace_.push(request_port);
+ trace_.push(response_port);
+ }
+
+ void
+ remove()
+ {
+ trace_.pop(); // Remove the response port name.
+ trace_.pop(); // Remove the request port name.
+ }
+
+ bool empty() { return trace_.empty(); }
+ std::stack& getTrace() { return trace_; }
+
+ private:
+ std::stack trace_;
+};
+
+/**
* A RequestPort is a specialisation of a Port, which
* implements the default protocol for the three different level of
* transport functions. In addition to the basic functionality of
@@ -266,6 +307,10 @@
{
panic("%s was not expecting a snoop retry.\n", name());
}
+
+ private:
+void addTrace(PacketPtr pkt) const;
+void removeTrace(PacketPtr pkt) const;
};
class [[deprecated]] MasterPort : public RequestPort
@@ -393,7 +438,11 @@
sendTimingResp(PacketPtr pkt)
{
try {
-return TimingResponseProtocol::sendResp(_requestPort, pkt);
+_requestPort->removeTrace(pkt);
+bool succ = TimingResponseProtocol::sendResp(_requestPort,
pkt);
+if (!succ)
+_requestPort->addTrace(pkt);
+return succ;
} catch (UnboundPortException) {
reportUnbound();
}
@@ -487,7 +536,10 @@
RequestPort::sendAtomic(PacketPtr pkt)
{
try {
-return AtomicRequestProtocol::send(_responsePort, pkt);
+addTrace(pkt);
+Tick tick = AtomicRequestProtocol::send(_responsePort, pkt);
+removeTrace(pkt);
+return tick;
} catch (UnboundPortException) {
reportUnbound();
}
@@ -497,8 +549,11 @@
RequestPort::sendAtomicBackdoor(PacketPtr pkt, MemBackdoorPtr )
{
try {
-return AtomicRequestProtocol::sendBackdoor(_responsePort,
-pkt, backdoor);
+addTrace(pkt);
+Tick tick = AtomicRequestProtocol::sendBackdoor(_responsePort,
+pkt, backdoor);
+removeTrace(pkt);
+return tick;
} catch (UnboundPortException) {
reportUnbound();
}
@@
