[gem5-dev] [S] Change in gem5/gem5[develop]: configs: bug fix for misc node distribution

2022-09-22 Thread Daecheol You (Gerrit)
Daecheol You has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/63731?usp=email )


Change subject: configs: bug fix for misc node distribution
..

configs: bug fix for misc node distribution

Wrong parameter is removed from the distributeNodes calling

Change-Id: I84cdf3e993d6b7852c4f134441d77a4b295e8574
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63731
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Tiago Muck 
---
M configs/topologies/CustomMesh.py
1 file changed, 17 insertions(+), 1 deletion(-)

Approvals:
  Tiago Muck: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/topologies/CustomMesh.py  
b/configs/topologies/CustomMesh.py

index 2e10fdc..545ba4b 100644
--- a/configs/topologies/CustomMesh.py
+++ b/configs/topologies/CustomMesh.py
@@ -357,7 +357,7 @@
 self.distributeNodes(hnf_params, hnf_nodes)

 # Place CHI_MN on the mesh
-self.distributeNodes(options, mn_params, mn_nodes)
+self.distributeNodes(mn_params, mn_nodes)

 # Place CHI_SNF_MainMem on the mesh
 self.distributeNodes(mem_params, mem_nodes)

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Gerrit-Change-Id: I84cdf3e993d6b7852c4f134441d77a4b295e8574
Gerrit-Change-Number: 63731
Gerrit-PatchSet: 2
Gerrit-Owner: Daecheol You 
Gerrit-Reviewer: Daecheol You 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Tiago Muck 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] [S] Change in gem5/gem5[develop]: configs: bug fix for misc node distribution

2022-09-19 Thread Daecheol You (Gerrit)
Daecheol You has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/63731?usp=email )



Change subject: configs: bug fix for misc node distribution
..

configs: bug fix for misc node distribution

Wrong parameter is removed from the distributeNodes calling

Change-Id: I84cdf3e993d6b7852c4f134441d77a4b295e8574
---
M configs/topologies/CustomMesh.py
1 file changed, 12 insertions(+), 1 deletion(-)



diff --git a/configs/topologies/CustomMesh.py  
b/configs/topologies/CustomMesh.py

index 2e10fdc..545ba4b 100644
--- a/configs/topologies/CustomMesh.py
+++ b/configs/topologies/CustomMesh.py
@@ -357,7 +357,7 @@
 self.distributeNodes(hnf_params, hnf_nodes)

 # Place CHI_MN on the mesh
-self.distributeNodes(options, mn_params, mn_nodes)
+self.distributeNodes(mn_params, mn_nodes)

 # Place CHI_SNF_MainMem on the mesh
 self.distributeNodes(mem_params, mem_nodes)

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[gem5-dev] [S] Change in gem5/gem5[develop]: mem-ruby: bug fix for stale WriteBack

2022-09-18 Thread Daecheol You (Gerrit)
Daecheol You has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/63611?usp=email )


Change subject: mem-ruby: bug fix for stale WriteBack
..

mem-ruby: bug fix for stale WriteBack

Finish_CopyBack_Stale is scheduled only when the requestor is the last
sharer. This prevents the cacahe evicting the line which was already
evicted while the stale WriteBack transaction was stalled.
Wrong condition check in Finish_CopyBack_Stale for eviction is also
removed.

Change-Id: Ib66acc1b9e4a6f7cea373e1fb37375427897d48d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63611
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/ruby/protocol/chi/CHI-cache-actions.sm
1 file changed, 25 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/mem/ruby/protocol/chi/CHI-cache-actions.sm  
b/src/mem/ruby/protocol/chi/CHI-cache-actions.sm

index 2c47ac9..d18c600 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache-actions.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache-actions.sm
@@ -891,7 +891,11 @@

   tbe.actions.pushNB(Event:SendCompDBIDRespStale);
   tbe.actions.pushNB(Event:WriteFEPipe);
-  tbe.actions.push(Event:FinishCopyBack_Stale);
+
+  // eviction condition should be examined if it is the last sharer
+  if (tbe.dir_sharers.count() == 1) {
+tbe.actions.push(Event:FinishCopyBack_Stale);
+  }

   assert((tbe.dir_ownerExists == false) || (tbe.dir_owner !=  
tbe.requestor));

 }
@@ -900,7 +904,7 @@
   // if it was the last known sharer and we don't have the data do the same
   // the Initiate_Evict
   if ((is_HN == false) && (tbe.dir_sharers.count() == 0) &&
-  tbe.dir_sharers.isElement(tbe.requestor) && (tbe.dataValid ==  
false)) {

+  (tbe.dataValid == false)) {
 tbe.actions.push(Event:SendEvict);
   }
 }

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Gerrit-Change-Id: Ib66acc1b9e4a6f7cea373e1fb37375427897d48d
Gerrit-Change-Number: 63611
Gerrit-PatchSet: 2
Gerrit-Owner: Daecheol You 
Gerrit-Reviewer: Daecheol You 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
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Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Fix WriteUnique transition on R* state

2022-03-31 Thread Daecheol You (Gerrit) via gem5-dev
Daecheol You has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58414 )



Change subject: mem-ruby: Fix WriteUnique transition on R* state
..

mem-ruby: Fix WriteUnique transition on R* state

When WriteUnique arrvies at an RNF in RSC, RSD, RUSC, RUSD and RU state,
the existing transition forwards the WriteUnique to downstream.
However, this makes a problem when an RNF is in RSC state.

Let's assume that an RNF is in RSC state and its downstream HNF is in
UC_RSC state. After the RNF forwards the WriteUnique to the HNF, it
receives SnpCleanInvalid from the HNF. Then, the RNF responses with
SnpRespData_I_PD since it holds the non-cobyback data from the original
requestor. This response, however, is not expected because the HNF
recognizes that the data block is not in dirty state in upstream.

Since CHI spec also requires the requestor of WriteUnique to be I state,
following changes are committed:
- For RUSC, RUSD and RU, which has exclusive right, invalidate the
upstream and do local write. This can be done with the existing
LocalWrite action (with a little modification for partial write).
- For RSC and RSD, acquire exclusive right with ReadUnique and do
local write. This can be done with LocalWrite_AfterUpgrade.
- For local write actions, set doCacheFill as true since it is not
set for RU, RSC and RSD state (the default allocation policy).

Change-Id: I453fb0991b49771939bc5ac1b6b782fc39f977b0
---
M src/mem/ruby/protocol/chi/CHI-cache-actions.sm
M src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
2 files changed, 48 insertions(+), 3 deletions(-)



diff --git a/src/mem/ruby/protocol/chi/CHI-cache-actions.sm  
b/src/mem/ruby/protocol/chi/CHI-cache-actions.sm

index 93a97d4..d43d46d 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache-actions.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache-actions.sm
@@ -714,8 +714,14 @@
   // auto-upgrade if hn but state was not unique
   assert(is_HN || tbe.dataUnique);
   tbe.dataUnique := true;
+  tbe.doCacheFill := true;
   if (tbe.dir_sharers.count() > 0) {
-tbe.actions.push(Event:SendSnpCleanInvalid);
+if (tbe.reqType == CHIRequestType:WriteUniquePtl &&
+tbe.dataValid == false) {
+  tbe.actions.push(Event:SendSnpUniqueRetToSrc);
+} else {
+  tbe.actions.push(Event:SendSnpCleanInvalid);
+}
   }
   if (comp_wu) {
 tbe.actions.push(Event:SendDBIDResp_WU);
@@ -732,6 +738,7 @@
 action(Initiate_WriteUnique_LocalWrite_AfterUpgrade, desc="") {
   assert(is_HN == false);
   assert((tbe.dataValid && tbe.dataUnique) == false);
+  tbe.doCacheFill := true;
   tbe.actions.push(Event:SendReadUnique);
   if (comp_wu) {
 tbe.actions.push(Event:SendDBIDResp_WU);
diff --git a/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm  
b/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm

index c4eb8ff..85caab7 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
@@ -365,7 +365,15 @@
   ProcessNextState;
 }

-transition({SD, SD_RSD, SD_RSC, SC, SC_RSC},
+transition({RUSD,RUSC,RU}, WriteUnique, BUSY_BLKD) {
+  Initiate_Request;
+  Initiate_WriteUnique_LocalWrite;
+  Profile_Miss;
+  Pop_ReqRdyQueue;
+  ProcessNextState;
+}
+
+transition({RSC, RSD, SD, SD_RSD, SD_RSC, SC, SC_RSC},
{WriteUnique}, BUSY_BLKD) {
   Initiate_Request;
   Initiate_WriteUnique_LocalWrite_AfterUpgrade;
@@ -390,7 +398,7 @@
   ProcessNextState;
 }

-transition({RSC,RSD,RUSD,RUSC,RU,I}, WriteUnique, BUSY_BLKD) {
+transition(I, WriteUnique, BUSY_BLKD) {
   Initiate_Request;
   Initiate_WriteUnique_Forward;
   Profile_Miss;

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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix sharer update for stale WriteCleanFull

2022-03-31 Thread Daecheol You (Gerrit) via gem5-dev
Daecheol You has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58413 )



Change subject: mem-ruby: fix sharer update for stale WriteCleanFull
..

mem-ruby: fix sharer update for stale WriteCleanFull

Initiate_CopyBack_Stale removes the requestor from the sharer list.
However, if CBWrData_SC is the data response of stale WriteCleanFull,
the requestor should remain in the sharer list.
Thus, whether to send a Evict or not can be decided after the data
response arrives. For this, FinishCopyBack_Stale event was added as the
last event to handle Evict.

Change-Id: Ic3e3a1e4d74b24b9aa328b2ddfa817db44f24e4e
---
M src/mem/ruby/protocol/chi/CHI-cache-actions.sm
M src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
M src/mem/ruby/protocol/chi/CHI-cache.sm
3 files changed, 33 insertions(+), 6 deletions(-)



diff --git a/src/mem/ruby/protocol/chi/CHI-cache-actions.sm  
b/src/mem/ruby/protocol/chi/CHI-cache-actions.sm

index 93a97d4..a181aa0 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache-actions.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache-actions.sm
@@ -835,17 +835,18 @@

   tbe.actions.pushNB(Event:SendCompDBIDRespStale);
   tbe.actions.pushNB(Event:WriteFEPipe);
+  tbe.actions.push(Event:FinishCopyBack_Stale);

+  assert((tbe.dir_ownerExists == false) || (tbe.dir_owner !=  
tbe.requestor));

+}
+
+action(Finish_CopyBack_Stale, desc="") {
   // if it was the last known sharer and we don't have the data do the same
   // the Initiate_Evict
-  if ((is_HN == false) && (tbe.dir_sharers.count() == 1) &&
+  if ((is_HN == false) && (tbe.dir_sharers.count() == 0) &&
   tbe.dir_sharers.isElement(tbe.requestor) && (tbe.dataValid ==  
false)) {

 tbe.actions.push(Event:SendEvict);
   }
-
-  tbe.dir_sharers.remove(tbe.requestor);
-  assert((tbe.dir_ownerExists == false) || (tbe.dir_owner !=  
tbe.requestor));

-
 }

 action(Initiate_Evict, desc="") {
@@ -1681,7 +1682,10 @@

   } else if (in_msg.type == CHIDataType:CBWrData_SC) {
 assert((tbe.dir_ownerExists == false) || (tbe.dir_owner !=  
in_msg.responder));

-tbe.dir_sharers.remove(in_msg.responder);
+// Do not remove the responder in case of stale WriteCleanFull
+if (tbe.reqType != CHIRequestType:WriteCleanFull) {
+  tbe.dir_sharers.remove(in_msg.responder);
+}

   } else if (in_msg.type == CHIDataType:CBWrData_SD_PD) {
 assert(tbe.dir_ownerExists && (tbe.dir_ownerIsExcl == false) &&  
(tbe.dir_owner == in_msg.responder));
diff --git a/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm  
b/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm

index c4eb8ff..e8f4f91 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
@@ -1023,6 +1023,12 @@
   ProcessNextState_ClearPending;
 }

+transition(BUSY_BLKD, FinishCopyBack_Stale) {
+  Pop_TriggerQueue;
+  Finish_CopyBack_Stale;
+  ProcessNextState_ClearPending;
+}
+
 transition(BUSY_BLKD, CheckUpgrade_FromStore) {
   Pop_TriggerQueue;
   Callback_Miss; // note: Callback happens only if tbe.dataValid
diff --git a/src/mem/ruby/protocol/chi/CHI-cache.sm  
b/src/mem/ruby/protocol/chi/CHI-cache.sm

index 5a12575..fb5a31a 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache.sm
@@ -470,6 +470,7 @@
 TX_Data, desc="Transmit pending data messages";
 MaintainCoherence, desc="Queues a WriteBack or Evict before droping  
the only valid copy of the block";
 FinishCleanUnique, desc="Sends acks and perform any writeback after a  
CleanUnique";

+FinishCopyBack_Stale, desc="Check if a Evict needs to be sent";
 ActionStalledOnHazard, desc="Stall a trigger action because until  
finish handling snoop hazard";


 // This is triggered once a transaction doesn't have

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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix the condition for stale WriteCleanFull

2022-03-31 Thread Daecheol You (Gerrit) via gem5-dev
Daecheol You has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58412 )



Change subject: mem-ruby: fix the condition for stale WriteCleanFull
..

mem-ruby: fix the condition for stale WriteCleanFull

WriteCleanFull can be requested for the cache line in SD state (e.g.
Local eviction of a cache line in SD_RSC state). In this case, the
requestor is the owner of the cache line,
but it doesn't have it with exclusive right.
Thus, 'ownerIsExcl == false' should be removed from the stale condition.

Change-Id: I4d34021ac31b2e8600c24689a03a3b8fa18aa1f7
---
M src/mem/ruby/protocol/chi/CHI-cache-ports.sm
1 file changed, 16 insertions(+), 1 deletion(-)



diff --git a/src/mem/ruby/protocol/chi/CHI-cache-ports.sm  
b/src/mem/ruby/protocol/chi/CHI-cache-ports.sm

index d9cb0f1..992f685 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache-ports.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache-ports.sm
@@ -276,7 +276,7 @@
 }
   } else if (in_msg.type == CHIRequestType:WriteCleanFull) {
 if (is_invalid(dir_entry) || (dir_entry.ownerExists == false) ||
-(dir_entry.ownerIsExcl == false) || (dir_entry.owner !=  
in_msg.requestor)) {

+(dir_entry.owner != in_msg.requestor)) {
   trigger(Event:WriteCleanFull_Stale, in_msg.addr, cache_entry,  
tbe);

 }
   } else if (in_msg.type == CHIRequestType:Evict) {

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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix the assert in Finalize_UpdateCacheFromTBE

2022-03-31 Thread Daecheol You (Gerrit) via gem5-dev
Daecheol You has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58411 )



Change subject: mem-ruby: fix the assert in Finalize_UpdateCacheFromTBE
..

mem-ruby: fix the assert in Finalize_UpdateCacheFromTBE

TBE data can be valid when the cache entry invalid.
For example, when HNF receives ReadOnce request for a cache line in RU
state from DMA, its TBE's data is valid since it snoops the line  from the  
upstream,

but the cache entry is invalid.
Thus, 'is_valid(cache_entry) == false' should be ORed to the assert  
condition.


Change-Id: Ie83c511e8d158e18abc5c9c16bc6040ce73587bf
---
M src/mem/ruby/protocol/chi/CHI-cache-actions.sm
1 file changed, 16 insertions(+), 1 deletion(-)



diff --git a/src/mem/ruby/protocol/chi/CHI-cache-actions.sm  
b/src/mem/ruby/protocol/chi/CHI-cache-actions.sm

index 93a97d4..8dea848 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache-actions.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache-actions.sm
@@ -2624,7 +2624,7 @@
 DPRINTF(RubySlicc, "Cached data %s pfb %s\n", tbe.dataBlk,  
cache_entry.HWPrefetched);

   } else {
 // make sure only deallocate the cache entry if data is invalid
-assert(tbe.dataValid == false);
+assert(tbe.dataValid == false || is_valid(cache_entry) == false);
 if (is_valid(cache_entry)) {
   cache.deallocate(address);
   unset_cache_entry();

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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: add missing response for ReadOnce

2022-03-31 Thread Daecheol You (Gerrit) via gem5-dev
Daecheol You has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58410 )



Change subject: mem-ruby: add missing response for ReadOnce
..

mem-ruby: add missing response for ReadOnce

When HNF snoops an RNF with SnpOnce to process
ReadOnce request (e.g. DMA read request),
the RNF can respond with SnpRespData_UC if the cache line is in UC.
Thus, SnpRespData_UC was added to the transition events.

Change-Id: Ife242e75feb9d2451eb99511e21833d9d190a6c3
---
M src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
1 file changed, 15 insertions(+), 1 deletion(-)



diff --git a/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm  
b/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm

index c4eb8ff..2ee61c1 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
@@ -1065,7 +1065,7 @@

 transition(BUSY_BLKD,
{SnpRespData_I_PD,SnpRespData_I,SnpRespData_SC_PD,
-SnpRespData_SC,SnpRespData_SD,SnpRespData_UD,
+SnpRespData_SC,SnpRespData_SD,SnpRespData_UC,SnpRespData_UD,
 SnpRespData_SC_Fwded_SC,SnpRespData_SC_Fwded_SD_PD,
 SnpRespData_SC_PD_Fwded_SC,SnpRespData_I_Fwded_SD_PD,
 SnpRespData_I_PD_Fwded_SC,SnpRespData_I_Fwded_SC}) {

--
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[gem5-dev] Change in gem5/gem5[develop]: configs: Modify createAddrRanges to support NUMA configuration

2022-02-27 Thread Daecheol You (Gerrit) via gem5-dev
Daecheol You has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/56610 )


Change subject: configs: Modify createAddrRanges to support NUMA  
configuration

..

configs: Modify createAddrRanges to support NUMA configuration

When system is configured for NUMA, it has multiple memory ranges,
and each memory range is mapped to a corresponding NUMA node.
For this, the change enables createAddrRanges to map address ranges to
only a given HNFs.

JIRA: https://gem5.atlassian.net/browse/GEM5-1187

Change-Id: If4a8f3ba9aac9f74125970f63410883d2ad32f01
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56610
Reviewed-by: Tiago Muck 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/ruby/CHI.py
M configs/ruby/CHI_config.py
2 files changed, 28 insertions(+), 9 deletions(-)

Approvals:
  Tiago Muck: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/configs/ruby/CHI.py b/configs/ruby/CHI.py
index e4a2477..3fe8b26 100644
--- a/configs/ruby/CHI.py
+++ b/configs/ruby/CHI.py
@@ -156,8 +156,9 @@
 for m in other_memories:
 sysranges.append(m.range)

+hnf_list = [i for i in range(options.num_l3caches)]
 CHI_HNF.createAddrRanges(sysranges, system.cache_line_size.value,
- options.num_l3caches)
+ hnf_list)
 ruby_system.hnf = [ CHI_HNF(i, ruby_system, HNFCache, None)
 for i in range(options.num_l3caches) ]

diff --git a/configs/ruby/CHI_config.py b/configs/ruby/CHI_config.py
index 097f367..b596efa 100644
--- a/configs/ruby/CHI_config.py
+++ b/configs/ruby/CHI_config.py
@@ -486,15 +486,14 @@
 '''HNFs may also define the 'pairing' parameter to allow pairing'''
 pairing = None

-_addr_ranges = []
+_addr_ranges = {}
 @classmethod
-def createAddrRanges(cls, sys_mem_ranges, cache_line_size, num_hnfs):
+def createAddrRanges(cls, sys_mem_ranges, cache_line_size, hnfs):
 # Create the HNFs interleaved addr ranges
 block_size_bits = int(math.log(cache_line_size, 2))
-cls._addr_ranges = []
-llc_bits = int(math.log(num_hnfs, 2))
+llc_bits = int(math.log(len(hnfs), 2))
 numa_bit = block_size_bits + llc_bits - 1
-for i in range(num_hnfs):
+for i, hnf in enumerate(hnfs):
 ranges = []
 for r in sys_mem_ranges:
 addr_range = AddrRange(r.start, size = r.size(),
@@ -502,7 +501,7 @@
 intlvBits = llc_bits,
 intlvMatch = i)
 ranges.append(addr_range)
-cls._addr_ranges.append((ranges, numa_bit, i))
+cls._addr_ranges[hnf] = (ranges, numa_bit)

 @classmethod
 def getAddrRanges(cls, hnf_idx):
@@ -514,10 +513,9 @@
 def __init__(self, hnf_idx, ruby_system, llcache_type, parent):
 super(CHI_HNF, self).__init__(ruby_system)

-addr_ranges,intlvHighBit,intlvMatch = self.getAddrRanges(hnf_idx)
+addr_ranges,intlvHighBit = self.getAddrRanges(hnf_idx)
 # All ranges should have the same interleaving
 assert(len(addr_ranges) >= 1)
-assert(intlvMatch == hnf_idx)

 ll_cache = llcache_type(start_index_bit = intlvHighBit + 1)
 self._cntrl = CHI_HNFController(ruby_system, ll_cache, NULL,

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If4a8f3ba9aac9f74125970f63410883d2ad32f01
Gerrit-Change-Number: 56610
Gerrit-PatchSet: 6
Gerrit-Owner: Daecheol You 
Gerrit-Reviewer: Daecheol You 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Tiago Muck 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Memory range configuration for NUMA system

2022-02-09 Thread Daecheol You (Gerrit) via gem5-dev
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If4a8f3ba9aac9f74125970f63410883d2ad32f01
Gerrit-Change-Number: 56610
Gerrit-PatchSet: 1
Gerrit-Owner: Daecheol You 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Fix message stall time calculation

2022-01-02 Thread Daecheol You (Gerrit) via gem5-dev
e
 statistics::Scalar m_not_avail_count;
+statistics::Scalar m_msg_count;
 statistics::Average m_buf_msgs;
-statistics::Average m_stall_time;
+statistics::Scalar m_stall_time;
 statistics::Scalar m_stall_count;
+statistics::Formula m_avg_stall_time;
 statistics::Formula m_occupancy;
 };


--
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Gerrit-Branch: develop
Gerrit-Change-Id: I090d19828b5c43f0843a8b735d3f00f312c436e9
Gerrit-Change-Number: 54363
Gerrit-PatchSet: 5
Gerrit-Owner: Daecheol You 
Gerrit-Reviewer: Daecheol You 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Matt Sinclair 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Fix message stall time calculation

2021-12-16 Thread Daecheol You (Gerrit) via gem5-dev
Daecheol You has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/54363 )



Change subject: mem-ruby: Fix message stall time calculation
..

mem-ruby: Fix message stall time calculation

Three changes below:
1. The m_stall_time was declared as statistics::Average, but
statistics::Average uses AvgStor as storage and this works as per-tick
average stat. In the case of m_stall_time, Scalar should be used to get
the calculation right.

2. The function used to get a enqueue time was changed since the getTime()
returns the time when the message was created.

3. Record the stall time only when the message is really dequeued
from the buffer (stall time is not evaluated when the message is moved
to stall map).

Change-Id: I090d19828b5c43f0843a8b735d3f00f312c436e9
---
M src/mem/ruby/network/MessageBuffer.cc
M src/mem/ruby/network/MessageBuffer.hh
2 files changed, 41 insertions(+), 5 deletions(-)



diff --git a/src/mem/ruby/network/MessageBuffer.cc  
b/src/mem/ruby/network/MessageBuffer.cc

index f4b2bb5..34f1a3c 100644
--- a/src/mem/ruby/network/MessageBuffer.cc
+++ b/src/mem/ruby/network/MessageBuffer.cc
@@ -66,10 +66,12 @@
 m_allow_zero_latency(p.allow_zero_latency),
 ADD_STAT(m_not_avail_count, "Number of times this buffer did not have "
 "N slots available"),
+ADD_STAT(m_msg_count, "Number of messages passed the buffer"),
 ADD_STAT(m_buf_msgs, "Average number of messages in buffer"),
-ADD_STAT(m_stall_time, "Average number of cycles messages are stalled  
in "

-   "this MB"),
+ADD_STAT(m_stall_time, "Total number of cycles messages are stalled  
in "

+   "this buffer"),
 ADD_STAT(m_stall_count, "Number of times messages were stalled"),
+ADD_STAT(m_avg_stall_time, "Average stall ticks per message"),
 ADD_STAT(m_occupancy, "Average occupancy of buffer capacity")
 {
 m_msg_counter = 0;
@@ -93,12 +95,18 @@
 m_not_avail_count
 .flags(statistics::nozero);

+m_msg_count
+.flags(statistics::nozero);
+
 m_buf_msgs
 .flags(statistics::nozero);

 m_stall_count
 .flags(statistics::nozero);

+m_avg_stall_time
+.flags(statistics::nozero | statistics::nonan);
+
 m_occupancy
 .flags(statistics::nozero);

@@ -110,6 +118,8 @@
 } else {
 m_occupancy = 0;
 }
+
+m_avg_stall_time = m_stall_time / m_msg_count;
 }

 unsigned int
@@ -288,8 +298,6 @@
 message->updateDelayedTicks(current_time);
 Tick delay = message->getDelayedTicks();

-m_stall_time = curTick() - message->getTime();
-
 // record previous size and time so the current buffer size isn't
 // adjusted until schd cycle
 if (m_time_last_time_pop < current_time) {
@@ -301,6 +309,10 @@
 pop_heap(m_prio_heap.begin(), m_prio_heap.end(),  
std::greater());

 m_prio_heap.pop_back();
 if (decrement_messages) {
+// Record how much time is passed since the message was enqueued
+m_stall_time += curTick() - message->getLastEnqueueTime();
+m_msg_count++;
+
 // If the message will be removed from the queue, decrement the
 // number of message in the queue.
 m_buf_msgs--;
diff --git a/src/mem/ruby/network/MessageBuffer.hh  
b/src/mem/ruby/network/MessageBuffer.hh

index ff2a4dd..7a48a1d 100644
--- a/src/mem/ruby/network/MessageBuffer.hh
+++ b/src/mem/ruby/network/MessageBuffer.hh
@@ -264,9 +264,11 @@

 // Count the # of times I didn't have N slots available
 statistics::Scalar m_not_avail_count;
+statistics::Scalar m_msg_count;
 statistics::Average m_buf_msgs;
-statistics::Average m_stall_time;
+statistics::Scalar m_stall_time;
 statistics::Scalar m_stall_count;
+statistics::Formula m_avg_stall_time;
 statistics::Formula m_occupancy;
 };


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[gem5-dev] Change in gem5/gem5[develop]: cpu-minor: Fix for minor CPU scoreboard

2021-09-17 Thread Daecheol You (Gerrit) via gem5-dev
Daecheol You has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/50287 )


Change subject: cpu-minor: Fix for minor CPU scoreboard
..

cpu-minor: Fix for minor CPU scoreboard

When the scoreboard checks RAW dependency, it determines whether
the source registers can be forwarded or not to evaluate
relative latency. To do that, fuIndices[index] should be used
as an index for accessing cant_forward_from_fu_indices, not register
index itself. Moreover, since fuIndices[index] is cleared as -1
by clearInstDests(), the first compare should be fuIndices[index] != -1
instead of 1.

Change-Id: Ic62546855a8ad5365064d2ea2e2a0fbc1ccc6f41
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50287
Reviewed-by: ZHENGRONG WANG 
Maintainer: ZHENGRONG WANG 
Tested-by: kokoro 
---
M src/cpu/minor/scoreboard.cc
M src/cpu/minor/scoreboard.hh
2 files changed, 7 insertions(+), 5 deletions(-)

Approvals:
  ZHENGRONG WANG: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/cpu/minor/scoreboard.cc b/src/cpu/minor/scoreboard.cc
index b957c3d..4637b8d 100644
--- a/src/cpu/minor/scoreboard.cc
+++ b/src/cpu/minor/scoreboard.cc
@@ -195,7 +195,7 @@
 if (numResults[index] == 0) {
 returnCycle[index] = Cycles(0);
 writingInst[index] = 0;
-fuIndices[index] = -1;
+fuIndices[index] = invalidFUIndex;
 }

 DPRINTF(MinorScoreboard, "Clearing inst: %s"
@@ -245,10 +245,11 @@
 unsigned short int index;

 if (findIndex(reg, index)) {
-bool cant_forward = fuIndices[index] != 1 &&
+int src_reg_fu = fuIndices[index];
+bool cant_forward = src_reg_fu != invalidFUIndex &&
 cant_forward_from_fu_indices &&
-index < cant_forward_from_fu_indices->size() &&
-(*cant_forward_from_fu_indices)[index];
+src_reg_fu < cant_forward_from_fu_indices->size() &&
+(*cant_forward_from_fu_indices)[src_reg_fu];

 Cycles relative_latency = (cant_forward ? Cycles(0) :
 (src_index >= num_relative_latencies ?
diff --git a/src/cpu/minor/scoreboard.hh b/src/cpu/minor/scoreboard.hh
index a928444..3ae0b65 100644
--- a/src/cpu/minor/scoreboard.hh
+++ b/src/cpu/minor/scoreboard.hh
@@ -96,6 +96,7 @@

 /** Index of the FU generating this result */
 std::vector fuIndices;
+static constexpr int invalidFUIndex = -1;

 /** The estimated cycle number that the result will be presented.
  *  This can be offset from to allow forwarding to be simulated as
@@ -121,7 +122,7 @@
 zeroReg(reg_classes.at(IntRegClass).zeroReg()),
 numResults(numRegs, 0),
 numUnpredictableResults(numRegs, 0),
-fuIndices(numRegs, 0),
+fuIndices(numRegs, invalidFUIndex),
 returnCycle(numRegs, Cycles(0)),
 writingInst(numRegs, 0)
 { }

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Gerrit-PatchSet: 3
Gerrit-Owner: Daecheol You 
Gerrit-Reviewer: Daecheol You 
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Gerrit-Reviewer: kokoro 
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[gem5-dev] Change in gem5/gem5[develop]: cpu-minor: Fix for minor CPU scoreboard

2021-09-13 Thread Daecheol You (Gerrit) via gem5-dev
Daecheol You has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/50287 )



Change subject: cpu-minor: Fix for minor CPU scoreboard
..

cpu-minor: Fix for minor CPU scoreboard

When the scoreboard checks RAW dependency, it determines whether
the source registers can be forwarded or not to evaluate
relative latency. To do that, fuIndices[index] should be used
as an index for accessing cant_forward_from_fu_indices, not register
index itself. Moreover, since fuIndices[index] is cleared as -1
by clearInstDests(), the first compare should be fuIndices[index] != -1
instead of 1.

Change-Id: Ic62546855a8ad5365064d2ea2e2a0fbc1ccc6f41
---
M src/cpu/minor/scoreboard.cc
1 file changed, 4 insertions(+), 3 deletions(-)



diff --git a/src/cpu/minor/scoreboard.cc b/src/cpu/minor/scoreboard.cc
index b957c3d..373c43e 100644
--- a/src/cpu/minor/scoreboard.cc
+++ b/src/cpu/minor/scoreboard.cc
@@ -245,10 +245,11 @@
 unsigned short int index;

 if (findIndex(reg, index)) {
-bool cant_forward = fuIndices[index] != 1 &&
+int src_reg_fu = fuIndices[index];
+bool cant_forward = src_reg_fu != -1 &&
 cant_forward_from_fu_indices &&
-index < cant_forward_from_fu_indices->size() &&
-(*cant_forward_from_fu_indices)[index];
+src_reg_fu < cant_forward_from_fu_indices->size() &&
+(*cant_forward_from_fu_indices)[src_reg_fu];

 Cycles relative_latency = (cant_forward ? Cycles(0) :
 (src_index >= num_relative_latencies ?

--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Add (RUSC, LocalHN_Eviction) transition

2021-08-23 Thread Daecheol You (Gerrit) via gem5-dev
Daecheol You has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49263 )


Change subject: mem-ruby: Add (RUSC, LocalHN_Eviction) transition
..

mem-ruby: Add (RUSC, LocalHN_Eviction) transition

During full system simulation on CHI, LocalHN_Eviction event on the RUSC
state occured occasionally. Thus, the change adds RUSC state to the  
transition.


Change-Id: Ibff382c38a092895bc03a4a64cf072ae752decf3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49263
Reviewed-by: Tiago Mück 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve; Looks  
good to me, approved

  Tiago Mück: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm  
b/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm

index 0d303fc..da944d5 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
@@ -587,7 +587,7 @@

 // This could happen if enqueued the eviction when the line was busy
 // or couldn't handle it immediately due to no TBE available
-transition({RU,RSC,RSD,RUSD,I}, {Local_Eviction, LocalHN_Eviction}) {
+transition({RU,RSC,RSD,RUSC,RUSD,I}, {Local_Eviction, LocalHN_Eviction}) {
   Pop_ReplTriggerQueue;
 }
 transition(I, Global_Eviction) {

--
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Gerrit-Change-Number: 49263
Gerrit-PatchSet: 2
Gerrit-Owner: Daecheol You 
Gerrit-Reviewer: Daecheol You 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Tiago Mück 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Add (RUSC, LocalHN_Eviction) transition

2021-08-15 Thread Daecheol You (Gerrit) via gem5-dev
Daecheol You has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/49263 )



Change subject: mem-ruby: Add (RUSC, LocalHN_Eviction) transition
..

mem-ruby: Add (RUSC, LocalHN_Eviction) transition

During full system simulation on CHI, LocalHN_Eviction event on the RUSC
state occured occasionally. Thus, the change adds RUSC state to the  
transition.


Change-Id: Ibff382c38a092895bc03a4a64cf072ae752decf3
---
M src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
1 file changed, 1 insertion(+), 1 deletion(-)



diff --git a/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm  
b/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm

index 0d303fc..da944d5 100644
--- a/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
+++ b/src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
@@ -587,7 +587,7 @@

 // This could happen if enqueued the eviction when the line was busy
 // or couldn't handle it immediately due to no TBE available
-transition({RU,RSC,RSD,RUSD,I}, {Local_Eviction, LocalHN_Eviction}) {
+transition({RU,RSC,RSD,RUSC,RUSD,I}, {Local_Eviction, LocalHN_Eviction}) {
   Pop_ReplTriggerQueue;
 }
 transition(I, Global_Eviction) {

--
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Atomic transaction support for CHI protocol

2021-08-04 Thread Daecheol You (Gerrit) via gem5-dev
Daecheol You has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48403 )


Change subject: mem-ruby: Atomic transaction support for CHI protocol
..

mem-ruby: Atomic transaction support for CHI protocol

Ruby assumes protocols use directory controllers as memory interface.
Thus, recvAtomic() uses the machine type of directory when it calls
mapAddressToMachine(). However, it doesn't work for CHI since
CHI does not use directory controllers as memory controller interface.
Therefore, the code was modified to check which controller type is used
for memory interface between MachineType_Directory and
MachineType_Memory, which is used for CHI.

Change-Id: If35a06a8a3772ce5e5b994df05c9d94c7770c90d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48403
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/mem/ruby/system/RubyPort.cc
1 file changed, 20 insertions(+), 9 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/system/RubyPort.cc  
b/src/mem/ruby/system/RubyPort.cc

index d021e4a..ff02fde 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -345,16 +345,27 @@
RubySystem::getBlockSizeBytes());
 }

-// Find appropriate directory for address
-// This assumes that protocols have a Directory machine,
-// which has its memPort hooked up to memory. This can
-// fail for some custom protocols.
-MachineID id = ruby_port->m_controller->mapAddressToMachine(
-pkt->getAddr(), MachineType_Directory);
+// Find the machine type of memory controller interface
 RubySystem *rs = ruby_port->m_ruby_system;
-AbstractController *directory =
-rs->m_abstract_controls[id.getType()][id.getNum()];
-Tick latency = directory->recvAtomic(pkt);
+static int mem_interface_type = -1;
+if (mem_interface_type == -1) {
+if (rs->m_abstract_controls[MachineType_Directory].size() != 0) {
+mem_interface_type = MachineType_Directory;
+}
+else if (rs->m_abstract_controls[MachineType_Memory].size() != 0) {
+mem_interface_type = MachineType_Memory;
+}
+else {
+panic("Can't find the memory controller interface\n");
+}
+}
+
+// Find the controller for the target address
+MachineID id = ruby_port->m_controller->mapAddressToMachine(
+pkt->getAddr(), (MachineType)mem_interface_type);
+AbstractController *mem_interface =
+rs->m_abstract_controls[mem_interface_type][id.getNum()];
+Tick latency = mem_interface->recvAtomic(pkt);
 if (access_backing_store)
 rs->getPhysMem()->access(pkt);
 return latency;

--
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Gerrit-Change-Number: 48403
Gerrit-PatchSet: 5
Gerrit-Owner: Daecheol You 
Gerrit-Reviewer: Daecheol You 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Jason Lowe-Power 
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Atomic transaction support for CHI protocol

2021-07-22 Thread Daecheol You (Gerrit) via gem5-dev
Daecheol You has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/48403 )



Change subject: mem-ruby: Atomic transaction support for CHI protocol
..

mem-ruby: Atomic transaction support for CHI protocol

Ruby assumes protocols use directory controllers as memory interface.
Thus, recvAtomic() uses the machine type of directory when it calls
mapAddressToMachine(). However, it doesn't work for CHI since
CHI does not use directory controllers as memory controller interface.
Therefore, the code was modified to check which controller type is used
for memory interface between MachineType_Directory and
MachineType_Memory, which is used for CHI.

Change-Id: If35a06a8a3772ce5e5b994df05c9d94c7770c90d
---
M src/mem/ruby/system/RubyPort.cc
1 file changed, 17 insertions(+), 9 deletions(-)



diff --git a/src/mem/ruby/system/RubyPort.cc  
b/src/mem/ruby/system/RubyPort.cc

index e2266b6..7127862 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -345,16 +345,24 @@
RubySystem::getBlockSizeBytes());
 }

-// Find appropriate directory for address
-// This assumes that protocols have a Directory machine,
-// which has its memPort hooked up to memory. This can
-// fail for some custom protocols.
-MachineID id = ruby_port->m_controller->mapAddressToMachine(
-pkt->getAddr(), MachineType_Directory);
+// Find the machine type of memory controller interface
 RubySystem *rs = ruby_port->m_ruby_system;
-AbstractController *directory =
-rs->m_abstract_controls[id.getType()][id.getNum()];
-Tick latency = directory->recvAtomic(pkt);
+static int mem_interface_type = -1;
+if (mem_interface_type == -1) {
+if (rs->m_abstract_controls[MachineType_Directory].size() != 0)
+mem_interface_type = MachineType_Directory;
+else if (rs->m_abstract_controls[MachineType_Memory].size() != 0)
+mem_interface_type = MachineType_Memory;
+else
+fatal("The protocol has no memory controller interface");
+}
+
+// Find the controller for the target address
+MachineID id = ruby_port->m_controller->mapAddressToMachine(
+pkt->getAddr(), (MachineType)mem_interface_type);
+AbstractController *mem_interface =
+rs->m_abstract_controls[mem_interface_type][id.getNum()];
+Tick latency = mem_interface->recvAtomic(pkt);
 if (access_backing_store)
 rs->getPhysMem()->access(pkt);
 return latency;

--
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[gem5-dev] Change in gem5/gem5[develop]: mem-garnet: Added packet distribution stats

2021-03-23 Thread Daecheol You (Gerrit) via gem5-dev
Daecheol You has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40275 )


Change subject: mem-garnet: Added packet distribution stats
..

mem-garnet: Added packet distribution stats

Trace data and control traffic between all source-destination pairs.
This is for identifying packet distribution and bottleneck of the
interconnect network.

Change-Id: Iffc9c16fd1e02ab8f7c5382cec822bf57a43a057
JIRA: https://gem5.atlassian.net/browse/GEM5-861
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40275
Reviewed-by: Srikant Bharadwaj 
Maintainer: Srikant Bharadwaj 
Tested-by: kokoro 
---
M src/mem/ruby/network/garnet/GarnetNetwork.cc
M src/mem/ruby/network/garnet/GarnetNetwork.hh
M src/mem/ruby/network/garnet/NetworkInterface.cc
3 files changed, 38 insertions(+), 0 deletions(-)

Approvals:
  Srikant Bharadwaj: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/network/garnet/GarnetNetwork.cc  
b/src/mem/ruby/network/garnet/GarnetNetwork.cc

index 91015ff..c260247 100644
--- a/src/mem/ruby/network/garnet/GarnetNetwork.cc
+++ b/src/mem/ruby/network/garnet/GarnetNetwork.cc
@@ -500,6 +500,25 @@
 .name(name() + ".avg_vc_load")
 .flags(Stats::pdf | Stats::total | Stats::nozero | Stats::oneline)
 ;
+
+// Traffic distribution
+for (int source = 0; source < m_routers.size(); ++source) {
+m_data_traffic_distribution.push_back(std::vector*>());
+m_ctrl_traffic_distribution.push_back(std::vector*>());

+
+for (int dest = 0; dest < m_routers.size(); ++dest) {
+Stats::Scalar *data_packets = new Stats::Scalar();
+Stats::Scalar *ctrl_packets = new Stats::Scalar();
+
+data_packets->name(name() + ".data_traffic_distribution."  
+ "n" +
+std::to_string(source) + "." + "n" +  
std::to_string(dest));

+m_data_traffic_distribution[source].push_back(data_packets);
+
+ctrl_packets->name(name() + ".ctrl_traffic_distribution."  
+ "n" +
+std::to_string(source) + "." + "n" +  
std::to_string(dest));

+m_ctrl_traffic_distribution[source].push_back(ctrl_packets);
+}
+}
 }

 void
@@ -554,6 +573,19 @@
 out << "[GarnetNetwork]";
 }

+void
+GarnetNetwork::update_traffic_distribution(RouteInfo route)
+{
+int src_node = route.src_router;
+int dest_node = route.dest_router;
+int vnet = route.vnet;
+
+if (m_vnet_type[vnet] == DATA_VNET_)
+(*m_data_traffic_distribution[src_node][dest_node])++;
+else
+(*m_ctrl_traffic_distribution[src_node][dest_node])++;
+}
+
 uint32_t
 GarnetNetwork::functionalWrite(Packet *pkt)
 {
diff --git a/src/mem/ruby/network/garnet/GarnetNetwork.hh  
b/src/mem/ruby/network/garnet/GarnetNetwork.hh

index 63c1a2c..294f0f6 100644
--- a/src/mem/ruby/network/garnet/GarnetNetwork.hh
+++ b/src/mem/ruby/network/garnet/GarnetNetwork.hh
@@ -142,6 +142,8 @@
 m_total_hops += hops;
 }

+void update_traffic_distribution(RouteInfo route);
+
   protected:
 // Configuration
 int m_num_rows;
@@ -185,6 +187,9 @@
 Stats::Scalar  m_total_hops;
 Stats::Formula m_avg_hops;

+std::vector> m_data_traffic_distribution;
+std::vector> m_ctrl_traffic_distribution;
+
   private:
 GarnetNetwork(const GarnetNetwork& obj);
 GarnetNetwork& operator=(const GarnetNetwork& obj);
diff --git a/src/mem/ruby/network/garnet/NetworkInterface.cc  
b/src/mem/ruby/network/garnet/NetworkInterface.cc

index dc37159..5c0216a 100644
--- a/src/mem/ruby/network/garnet/NetworkInterface.cc
+++ b/src/mem/ruby/network/garnet/NetworkInterface.cc
@@ -426,6 +426,7 @@
 route.hops_traversed = -1;

 m_net_ptr->increment_injected_packets(vnet);
+m_net_ptr->update_traffic_distribution(route);
 for (int i = 0; i < num_flits; i++) {
 m_net_ptr->increment_injected_flits(vnet);
 flit *fl = new flit(i, vc, vnet, route, num_flits, new_msg_ptr,

--
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Gerrit-Change-Id: Iffc9c16fd1e02ab8f7c5382cec822bf57a43a057
Gerrit-Change-Number: 40275
Gerrit-PatchSet: 5
Gerrit-Owner: Daecheol You 
Gerrit-Reviewer: Daecheol You 
Gerrit-Reviewer: Matthew Poremba 
Gerrit-Reviewer: Srikant Bharadwaj 
Gerrit-Reviewer: kokoro 
Gerrit-CC: Jason Lowe-Power 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: python: Mesh topology with user-defined layout

2021-01-31 Thread Daecheol You (Gerrit) via gem5-dev
tency,
+ weight=2))
+link_count += 1
+
+
+network.int_links = int_links
+
+# Register nodes with filesystem
+def registerTopology(self, options):
+for i in range(options.num_cpus):
+FileSystemConfig.register_node([i],
+MemorySize(options.mem_size) // options.num_cpus, i)
diff --git a/configs/topologies/layout_example.txt  
b/configs/topologies/layout_example.txt

new file mode 100644
index 000..98b5eae
--- /dev/null
+++ b/configs/topologies/layout_example.txt
@@ -0,0 +1,40 @@
+# This is an example of 6x8 mesh layout.
+# The example assumes that MESI_Three_Level protocol is used.
+# 64 CPUs (L0 and L1) shared caches (L2) are connected in 32 router nodes
+# and 8 directories are distributed on each right and left side of the  
mesh.

+# 8 router nodes at four corners have no controllers attached.
+#
+# First two attribute should be number of rows and columns like below.
+#   row: {number of rows}, cols: {number of columns}
+#
+# Then, external controllers attached to each router node are described.
+# The format is like below.
+#   nodes: {row number}/{column number}: {attached controller list},
+# Each controller is separated with space.
+# A cache is described as 'L{cache level}'
+# and a directory is described as 'Dir'.
+# If no controllers are attatched, the controller list is described  
as 'None'.

+#
+# Note that the same controller configuration is applied
+# until the router node of specified column nubmer.
+# For example, the routers in the first row of the example layout
+# have the controllers like below:
+#   0/0, 0/1: No controllers are attched
+#   0/2, 0/3, 0/4, 0/5: L0 L1 L2 L0 L1 L2
+#   0/6, 0/7: No controllers are attched
+#
+# When describing controller list for each router,
+# controller ID can be specified additionally.
+# The format is {controller type}-{controller ID}.
+# For instance, if you want to specify L0 and L1 cache with ID of 1,
+# and a directory with ID of 7, describtion is like below.
+#   0/0: L0-1 L1-1 Dir-7,
+
+rows: 6,
+cols: 8,
+nodes: 0/1: None, 0/5: L0 L1 L2 L0 L1 L2, 0/7: None,
+   1/0: Dir,  1/6: L0 L1 L2 L0 L1 L2, 1/7: Dir,
+   2/0: Dir,  2/6: L0 L1 L2 L0 L1 L2, 2/7: Dir,
+   3/0: Dir,  3/6: L0 L1 L2 L0 L1 L2, 3/7: Dir,
+   4/0: Dir,  4/6: L0 L1 L2 L0 L1 L2, 4/7: Dir,
+   5/1: None, 5/5: L0 L1 L2 L0 L1 L2, 5/7: None,

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[gem5-dev] Change in gem5/gem5[develop]: mem-garnet: Added packet distribution stats

2021-01-31 Thread Daecheol You (Gerrit) via gem5-dev
Daecheol You has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40275 )



Change subject: mem-garnet: Added packet distribution stats
..

mem-garnet: Added packet distribution stats

Trace data and control traffic between all source-destination pairs.
This is for making realistic synthetic traffic based on the real
application execution.

Change-Id: Iffc9c16fd1e02ab8f7c5382cec822bf57a43a057
JIRA: https://gem5.atlassian.net/browse/GEM5-861
---
M src/mem/ruby/network/garnet/GarnetNetwork.cc
M src/mem/ruby/network/garnet/GarnetNetwork.hh
M src/mem/ruby/network/garnet/NetworkInterface.cc
3 files changed, 60 insertions(+), 0 deletions(-)



diff --git a/src/mem/ruby/network/garnet/GarnetNetwork.cc  
b/src/mem/ruby/network/garnet/GarnetNetwork.cc

index 91015ff..9d4d0f0 100644
--- a/src/mem/ruby/network/garnet/GarnetNetwork.cc
+++ b/src/mem/ruby/network/garnet/GarnetNetwork.cc
@@ -500,6 +500,25 @@
 .name(name() + ".avg_vc_load")
 .flags(Stats::pdf | Stats::total | Stats::nozero | Stats::oneline)
 ;
+
+// Traffic distribution
+for (int source = 0; source < m_routers.size(); ++source) {
+m_data_traffic_distribution.push_back(std::vector*>());
+m_ctrl_traffic_distribution.push_back(std::vector*>());

+
+for (int dest = 0; dest < m_routers.size(); ++dest) {
+Stats::Scalar *data_packets = new Stats::Scalar();
+Stats::Scalar *ctrl_packets = new Stats::Scalar();
+
+data_packets->name(name() + ".data_traffic_distribution."  
+ "n" +
+std::to_string(source) + "." + "n" +  
std::to_string(dest));

+m_data_traffic_distribution[source].push_back(data_packets);
+
+ctrl_packets->name(name() + ".ctrl_traffic_distribution."  
+ "n" +
+std::to_string(source) + "." + "n" +  
std::to_string(dest));

+m_ctrl_traffic_distribution[source].push_back(ctrl_packets);
+}
+}
 }

 void
@@ -554,6 +573,39 @@
 out << "[GarnetNetwork]";
 }

+void
+GarnetNetwork::update_traffic_distribution(RouteInfo route,
+   MessageSizeType type)
+{
+int src_node = route.src_router;
+int dest_node = route.dest_router;
+std::vector dest = route.net_dest.getAllDest();
+
+/*
+ * All multicast messages were converted into unicast messages
+ * at flitisizeMessage()
+ */
+assert(dest.size() == 1);
+
+bool is_data_msg = false;
+switch(type) {
+case MessageSizeType_Data:
+case MessageSizeType_Response_Data:
+case MessageSizeType_ResponseLocal_Data:
+case MessageSizeType_ResponseL2hit_Data:
+case MessageSizeType_Writeback_Data:
+is_data_msg = true;
+break;
+default:
+break;
+}
+
+if (is_data_msg)
+(*m_data_traffic_distribution[src_node][dest_node])++;
+else
+(*m_ctrl_traffic_distribution[src_node][dest_node])++;
+}
+
 uint32_t
 GarnetNetwork::functionalWrite(Packet *pkt)
 {
diff --git a/src/mem/ruby/network/garnet/GarnetNetwork.hh  
b/src/mem/ruby/network/garnet/GarnetNetwork.hh

index 63c1a2c..7f39f80 100644
--- a/src/mem/ruby/network/garnet/GarnetNetwork.hh
+++ b/src/mem/ruby/network/garnet/GarnetNetwork.hh
@@ -142,6 +142,9 @@
 m_total_hops += hops;
 }

+void update_traffic_distribution(RouteInfo route,
+ MessageSizeType type);
+
   protected:
 // Configuration
 int m_num_rows;
@@ -185,6 +188,9 @@
 Stats::Scalar  m_total_hops;
 Stats::Formula m_avg_hops;

+std::vector> m_data_traffic_distribution;
+std::vector> m_ctrl_traffic_distribution;
+
   private:
 GarnetNetwork(const GarnetNetwork& obj);
 GarnetNetwork& operator=(const GarnetNetwork& obj);
diff --git a/src/mem/ruby/network/garnet/NetworkInterface.cc  
b/src/mem/ruby/network/garnet/NetworkInterface.cc

index dc37159..d69bdc9 100644
--- a/src/mem/ruby/network/garnet/NetworkInterface.cc
+++ b/src/mem/ruby/network/garnet/NetworkInterface.cc
@@ -426,6 +426,8 @@
 route.hops_traversed = -1;

 m_net_ptr->increment_injected_packets(vnet);
+m_net_ptr->update_traffic_distribution(route,
+new_net_msg_ptr->getMessageSize());
 for (int i = 0; i < num_flits; i++) {
 m_net_ptr->increment_injected_flits(vnet);
 flit *fl = new flit(i, vc, vnet, route, num_flits, new_msg_ptr,

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