[gem5-dev] Change in gem5/gem5[develop]: sim-se: add checks in selectFunc to fix up craches
Luming Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/53143 )
Change subject: sim-se: add checks in selectFunc to fix up craches
..
sim-se: add checks in selectFunc to fix up craches
In selectFunc, FD_ZERO are invoked without checking whether
reinterpret_cast((typename OS::fd_set *)readfds) is NULL.
So does writefds and errorfds.
Change-Id: I175fe1369c85fd8a832a227c3f90f25d772f33e1
---
M src/sim/syscall_emul.hh
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 6cbbf00..d78f4ac 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -2543,9 +2543,15 @@
if (retval == -1)
return -errno;
-FD_ZERO(reinterpret_cast((typename OS::fd_set *)readfds));
-FD_ZERO(reinterpret_cast((typename OS::fd_set *)writefds));
-FD_ZERO(reinterpret_cast((typename OS::fd_set *)errorfds));
+if (readfds) {
+FD_ZERO(reinterpret_cast((typename OS::fd_set
*)readfds));
+}
+if (writefds) {
+FD_ZERO(reinterpret_cast((typename OS::fd_set
*)writefds));
+}
+if (errorfds) {
+FD_ZERO(reinterpret_cast((typename OS::fd_set
*)errorfds));
+}
/**
* We need to translate the host file descriptor set into a target file
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I175fe1369c85fd8a832a227c3f90f25d772f33e1
Gerrit-Change-Number: 53143
Gerrit-PatchSet: 1
Gerrit-Owner: Luming Wang
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim: fix build error when glibc >= 2.34
Luming Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/53183 )
Change subject: sim: fix build error when glibc >= 2.34
..
sim: fix build error when glibc >= 2.34
Since glibc >= 2.34, MINSIGSTKSZ and SIGSTKSZ are no longer
constant on Linux. As a result, the definition
"fatalSigStack[2*SIGSTKSZ]" fails to be compiled.
Thus, we need to dynamically allocate it.
Change-Id: Ibccc367818483b9c94beda871d1d95367d1e8b04
---
M src/sim/init_signals.cc
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/src/sim/init_signals.cc b/src/sim/init_signals.cc
index cac0190..6f1490b 100644
--- a/src/sim/init_signals.cc
+++ b/src/sim/init_signals.cc
@@ -64,18 +64,24 @@
{
// Use an separate stack for fatal signal handlers
-static uint8_t fatalSigStack[2 * SIGSTKSZ];
+#define STKSZ (2 * SIGSTKSZ)
+static uint8_t *fatalSigStack;
static bool
setupAltStack()
{
+static bool isFirstTime = true;
+if (isFirstTime) {
+fatalSigStack = new uint8_t[STKSZ];
+isFirstTime = false;
+}
stack_t stack;
#if defined(__FreeBSD__) && (__FreeBSD_version < 1100097)
stack.ss_sp = (char *)fatalSigStack;
#else
stack.ss_sp = fatalSigStack;
#endif
-stack.ss_size = sizeof(fatalSigStack);
+stack.ss_size = STKSZ;
stack.ss_flags = 0;
return sigaltstack(&stack, NULL) == 0;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibccc367818483b9c94beda871d1d95367d1e8b04
Gerrit-Change-Number: 53183
Gerrit-PatchSet: 1
Gerrit-Owner: Luming Wang
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fix inUserMode
Luming Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/53184 )
Change subject: arch-riscv: fix inUserMode
..
arch-riscv: fix inUserMode
The original inUserMode() simply returns true. However, it should
check the processor's current privilege level.
Change-Id: Iba74ccc6ff459e7d8c421ae9fe004c6c09920763
---
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index e26b6fa..0358889 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -205,6 +205,11 @@
clear();
}
+bool ISA::inUserMode() const
+{
+return miscRegFile[MISCREG_PRV] == PRV_U;
+}
+
void
ISA::copyRegsFrom(ThreadContext *src)
{
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 6435b74..143cc69 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -98,7 +98,7 @@
int flattenCCIndex(int reg) const { return reg; }
int flattenMiscIndex(int reg) const { return reg; }
-bool inUserMode() const override { return true; }
+bool inUserMode() const override;
void copyRegsFrom(ThreadContext *src) override;
void serialize(CheckpointOut &cp) const override;
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Iba74ccc6ff459e7d8c421ae9fe004c6c09920763
Gerrit-Change-Number: 53184
Gerrit-PatchSet: 1
Gerrit-Owner: Luming Wang
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim-se: add checks in selectFunc to fix up crashes
Luming Wang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/53143 )
Change subject: sim-se: add checks in selectFunc to fix up crashes
..
sim-se: add checks in selectFunc to fix up crashes
In selectFunc, FD_ZERO are invoked without checking whether
reinterpret_cast((typename OS::fd_set *)readfds) is NULL.
So does writefds and errorfds.
Change-Id: I175fe1369c85fd8a832a227c3f90f25d772f33e1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53143
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/sim/syscall_emul.hh
1 file changed, 26 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 6cbbf00..d78f4ac 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -2543,9 +2543,15 @@
if (retval == -1)
return -errno;
-FD_ZERO(reinterpret_cast((typename OS::fd_set *)readfds));
-FD_ZERO(reinterpret_cast((typename OS::fd_set *)writefds));
-FD_ZERO(reinterpret_cast((typename OS::fd_set *)errorfds));
+if (readfds) {
+FD_ZERO(reinterpret_cast((typename OS::fd_set
*)readfds));
+}
+if (writefds) {
+FD_ZERO(reinterpret_cast((typename OS::fd_set
*)writefds));
+}
+if (errorfds) {
+FD_ZERO(reinterpret_cast((typename OS::fd_set
*)errorfds));
+}
/**
* We need to translate the host file descriptor set into a target file
--
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Gerrit-Change-Id: I175fe1369c85fd8a832a227c3f90f25d772f33e1
Gerrit-Change-Number: 53143
Gerrit-PatchSet: 3
Gerrit-Owner: Luming Wang
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Luming Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fix inUserMode
Luming Wang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/53184 )
Change subject: arch-riscv: fix inUserMode
..
arch-riscv: fix inUserMode
The original inUserMode() simply returns true. However, it should
check whether the processor's current privilege level is PRV_U.
Change-Id: Iba74ccc6ff459e7d8c421ae9fe004c6c09920763
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53184
Reviewed-by: Jason Lowe-Power
Reviewed-by: Ayaz Akram
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/riscv/isa.cc
M src/arch/riscv/isa.hh
2 files changed, 23 insertions(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Ayaz Akram: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index e26b6fa..0358889 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -205,6 +205,11 @@
clear();
}
+bool ISA::inUserMode() const
+{
+return miscRegFile[MISCREG_PRV] == PRV_U;
+}
+
void
ISA::copyRegsFrom(ThreadContext *src)
{
diff --git a/src/arch/riscv/isa.hh b/src/arch/riscv/isa.hh
index 6435b74..143cc69 100644
--- a/src/arch/riscv/isa.hh
+++ b/src/arch/riscv/isa.hh
@@ -98,7 +98,7 @@
int flattenCCIndex(int reg) const { return reg; }
int flattenMiscIndex(int reg) const { return reg; }
-bool inUserMode() const override { return true; }
+bool inUserMode() const override;
void copyRegsFrom(ThreadContext *src) override;
void serialize(CheckpointOut &cp) const override;
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Iba74ccc6ff459e7d8c421ae9fe004c6c09920763
Gerrit-Change-Number: 53184
Gerrit-PatchSet: 3
Gerrit-Owner: Luming Wang
Gerrit-Reviewer: Ayaz Akram
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Luming Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: fix build error when glibc >= 2.34
Luming Wang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/53183 )
Change subject: sim: fix build error when glibc >= 2.34
..
sim: fix build error when glibc >= 2.34
Since glibc >= 2.34, MINSIGSTKSZ and SIGSTKSZ are no longer
constant on Linux. As a result, the definition
"fatalSigStack[2*SIGSTKSZ]" fails to be compiled.
Thus, we need to dynamically allocate it.
Change-Id: Ibccc367818483b9c94beda871d1d95367d1e8b04
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53183
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/sim/init_signals.cc
1 file changed, 23 insertions(+), 4 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/sim/init_signals.cc b/src/sim/init_signals.cc
index cac0190..b6db621 100644
--- a/src/sim/init_signals.cc
+++ b/src/sim/init_signals.cc
@@ -64,18 +64,19 @@
{
// Use an separate stack for fatal signal handlers
-static uint8_t fatalSigStack[2 * SIGSTKSZ];
static bool
setupAltStack()
{
+const auto stack_size = 2 * SIGSTKSZ;
+static uint8_t *fatal_sig_stack = new uint8_t[stack_size];
stack_t stack;
#if defined(__FreeBSD__) && (__FreeBSD_version < 1100097)
-stack.ss_sp = (char *)fatalSigStack;
+stack.ss_sp = (char *)fatal_sig_stack;
#else
-stack.ss_sp = fatalSigStack;
+stack.ss_sp = fatal_sig_stack;
#endif
-stack.ss_size = sizeof(fatalSigStack);
+stack.ss_size = stack_size;
stack.ss_flags = 0;
return sigaltstack(&stack, NULL) == 0;
--
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Gerrit-Branch: develop
Gerrit-Change-Id: Ibccc367818483b9c94beda871d1d95367d1e8b04
Gerrit-Change-Number: 53183
Gerrit-PatchSet: 5
Gerrit-Owner: Luming Wang
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Luming Wang
Gerrit-Reviewer: kokoro
Gerrit-CC: Jason Lowe-Power
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv,sim-se: Complements the system calls on RISC-V
Luming Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/54803 )
Change subject: arch-riscv,sim-se: Complements the system calls on RISC-V
..
arch-riscv,sim-se: Complements the system calls on RISC-V
There are many SE mode system calls that are implemented
in src/sim/syscall_emul.cc or src/sim/syscall_emul.hh.
And they work well under X86 and ARM platforms. However,
they are not supported in se_workload.cc under the RISC-V
platform. This patch adds support for all the system calls
already implemented in syscall_emul.hh/cc to the RISC-V
platform (in arch/riscv/linux/se_workload.cc).
Change-Id: Ia47c3c113767b50412b1c8ade3c1047c894376cf
---
M src/arch/riscv/linux/se_workload.cc
1 file changed, 77 insertions(+), 60 deletions(-)
diff --git a/src/arch/riscv/linux/se_workload.cc
b/src/arch/riscv/linux/se_workload.cc
index 2e2a7d2..54f6e55 100644
--- a/src/arch/riscv/linux/se_workload.cc
+++ b/src/arch/riscv/linux/se_workload.cc
@@ -157,8 +157,8 @@
{ 30, "ioprio_get" },
{ 31, "ioprio_set" },
{ 32, "flock" },
-{ 33, "mknodat" },
-{ 34, "mkdirat" },
+{ 33, "mknodat", mknodatFunc },
+{ 34, "mkdirat", mkdiratFunc },
{ 35, "unlinkat", unlinkatFunc },
{ 36, "symlinkat" },
{ 37, "linkat" },
@@ -173,7 +173,7 @@
{ 46, "ftruncate", ftruncate64Func },
{ 47, "fallocate", fallocateFunc },
{ 48, "faccessat", faccessatFunc },
-{ 49, "chdir" },
+{ 49, "chdir", chdirFunc },
{ 50, "fchdir" },
{ 51, "chroot" },
{ 52, "fchmod", fchmodFunc },
@@ -183,14 +183,14 @@
{ 56, "openat", openatFunc },
{ 57, "close", closeFunc },
{ 58, "vhangup" },
-{ 59, "pipe2" },
+{ 59, "pipe2", pipe2Func },
{ 60, "quotactl" },
-{ 61, "getdents64" },
+{ 61, "getdents64", getdents64Func },
{ 62, "lseek", lseekFunc },
{ 63, "read", readFunc },
{ 64, "write", writeFunc },
{ 66, "writev", writevFunc },
-{ 67, "pread64" },
+{ 67, "pread64", pread64Func },
{ 68, "pwrite64", pwrite64Func },
{ 69, "preadv" },
{ 70, "pwritev" },
@@ -246,7 +246,7 @@
{ 120, "sched_getscheduler" },
{ 121, "sched_getparam" },
{ 122, "sched_setaffinity" },
-{ 123, "sched_getaffinity" },
+{ 123, "sched_getaffinity", schedGetaffinityFunc },
{ 124, "sched_yield", ignoreWarnOnceFunc },
{ 125, "sched_get_priority_max" },
{ 126, "sched_get_priority_min" },
@@ -291,7 +291,7 @@
{ 165, "getrusage", getrusageFunc },
{ 166, "umask", umaskFunc },
{ 167, "prctl" },
-{ 168, "getcpu" },
+{ 168, "getcpu", getcpuFunc },
{ 169, "gettimeofday", gettimeofdayFunc },
{ 170, "settimeofday" },
{ 171, "adjtimex" },
@@ -321,21 +321,21 @@
{ 195, "shmctl" },
{ 196, "shmat" },
{ 197, "shmdt" },
-{ 198, "socket" },
-{ 199, "socketpair" },
+{ 198, "socket", socketFunc },
+{ 199, "socketpair", socketpairFunc },
{ 200, "bind" },
-{ 201, "listen" },
+{ 201, "listen", listenFunc },
{ 202, "accept" },
{ 203, "connect" },
-{ 204, "getsockname" },
-{ 205, "getpeername" },
+{ 204, "getsockname", getsocknameFunc },
+{ 205, "getpeername", getpeernameFunc },
{ 206, "sendo" },
-{ 207, "recvfrom" },
-{ 208, "setsockopt" },
-{ 209, "getsockopt" },
-{ 210, "shutdown" },
-{ 211, "sendmsg" },
-{ 212, "recvmsg" },
+{ 207, "recvfrom", recvfromFunc },
+{ 208, "setsockopt", setsockoptFunc },
+{ 209, "getsockopt", getsockoptFunc },
+{ 210, "shutdown", shutdownFunc },
+{ 211, "sendmsg", sendmsgFunc },
+{ 212, "recvmsg", recvmsgFunc },
{ 213, "readahead" },
{ 214, "brk", brkFunc },
{ 215, "munmap", munmapFunc },
@@ -367,7 +367,7 @@
{ 241, "perf_event_open" },
{ 242, "accept4" },
{ 243, "recvmmsg" },
-{ 260, "wait4" },
+{ 260, "wait4", wait4Func },
{ 261, "prlimit64", prlimitFunc },
{ 262, "fanotify_init" },
{ 263, "fanotify_mark" },
@@ -396,18 +396,18 @@
{ 286, "preadv2" },
{ 287, "pwritev2" },
{ 1024, "open", openFunc },
-{ 1025, "link" },
+{ 1025, "link", linkFunc },
{ 1026, "unlink", unlinkFunc },
-{ 1027, "mknod" },
+{ 1027, "mknod", mknodFunc },
{ 1028, "chmod", chmodFunc },
{ 1029, "chown", chownFunc },
{ 1030, "mkdir", mkdirFunc },
-{ 1031, "rmdir" },
+{ 1031, "rmdir", rmdirFunc },
{ 1032, "lchown" },
{ 1033, "access", accessFunc },
{ 1034, "rename", renameFunc },
{ 1035, "readlink", readlinkFunc },
-{ 1036, "symlink" },
+{ 1036, "symlink", symlinkFunc },
{ 1037, "utimes", utimesFunc },
{ 1038, "stat", stat64Func },
{ 1039, "lstat", lstat64Func },
@@ -415,7 +415,7 @@
{ 1
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv,sim-se: Complements the system calls on RISC-V
Luming Wang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/54803 )
Change subject: arch-riscv,sim-se: Complements the system calls on RISC-V
..
arch-riscv,sim-se: Complements the system calls on RISC-V
There are many SE mode system calls that are implemented
in src/sim/syscall_emul.cc or src/sim/syscall_emul.hh.
And they work well under X86 and ARM platforms. However,
they are not supported in se_workload.cc under the RISC-V
platform. This patch adds support for all the system calls
already implemented in syscall_emul.hh/cc to the RISC-V
platform (in arch/riscv/linux/se_workload.cc).
Change-Id: Ia47c3c113767b50412b1c8ade3c1047c894376cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54803
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
Reviewed-by: Bobby Bruce
---
M src/arch/riscv/linux/se_workload.cc
1 file changed, 88 insertions(+), 66 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Bobby Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/linux/se_workload.cc
b/src/arch/riscv/linux/se_workload.cc
index 2e2a7d2..815b63b 100644
--- a/src/arch/riscv/linux/se_workload.cc
+++ b/src/arch/riscv/linux/se_workload.cc
@@ -157,8 +157,8 @@
{ 30, "ioprio_get" },
{ 31, "ioprio_set" },
{ 32, "flock" },
-{ 33, "mknodat" },
-{ 34, "mkdirat" },
+{ 33, "mknodat", mknodatFunc },
+{ 34, "mkdirat", mkdiratFunc },
{ 35, "unlinkat", unlinkatFunc },
{ 36, "symlinkat" },
{ 37, "linkat" },
@@ -173,7 +173,7 @@
{ 46, "ftruncate", ftruncate64Func },
{ 47, "fallocate", fallocateFunc },
{ 48, "faccessat", faccessatFunc },
-{ 49, "chdir" },
+{ 49, "chdir", chdirFunc },
{ 50, "fchdir" },
{ 51, "chroot" },
{ 52, "fchmod", fchmodFunc },
@@ -183,14 +183,14 @@
{ 56, "openat", openatFunc },
{ 57, "close", closeFunc },
{ 58, "vhangup" },
-{ 59, "pipe2" },
+{ 59, "pipe2", pipe2Func },
{ 60, "quotactl" },
-{ 61, "getdents64" },
+{ 61, "getdents64", getdents64Func },
{ 62, "lseek", lseekFunc },
{ 63, "read", readFunc },
{ 64, "write", writeFunc },
{ 66, "writev", writevFunc },
-{ 67, "pread64" },
+{ 67, "pread64", pread64Func },
{ 68, "pwrite64", pwrite64Func },
{ 69, "preadv" },
{ 70, "pwritev" },
@@ -246,7 +246,7 @@
{ 120, "sched_getscheduler" },
{ 121, "sched_getparam" },
{ 122, "sched_setaffinity" },
-{ 123, "sched_getaffinity" },
+{ 123, "sched_getaffinity", schedGetaffinityFunc },
{ 124, "sched_yield", ignoreWarnOnceFunc },
{ 125, "sched_get_priority_max" },
{ 126, "sched_get_priority_min" },
@@ -291,7 +291,7 @@
{ 165, "getrusage", getrusageFunc },
{ 166, "umask", umaskFunc },
{ 167, "prctl" },
-{ 168, "getcpu" },
+{ 168, "getcpu", getcpuFunc },
{ 169, "gettimeofday", gettimeofdayFunc },
{ 170, "settimeofday" },
{ 171, "adjtimex" },
@@ -321,21 +321,21 @@
{ 195, "shmctl" },
{ 196, "shmat" },
{ 197, "shmdt" },
-{ 198, "socket" },
-{ 199, "socketpair" },
-{ 200, "bind" },
-{ 201, "listen" },
-{ 202, "accept" },
-{ 203, "connect" },
-{ 204, "getsockname" },
-{ 205, "getpeername" },
+{ 198, "socket", socketFunc },
+{ 199, "socketpair", socketpairFunc },
+{ 200, "bind", bindFunc },
+{ 201, "listen", listenFunc },
+{ 202, "accept", acceptFunc },
+{ 203, "connect", connectFunc },
+{ 204, "getsockname", getsocknameFunc },
+{ 205, "getpeername", getpeernameFunc },
{ 206, "sendo" },
-{ 207, "recvfrom" },
-{ 208, "setsockopt" },
-{ 209, "getsockopt" },
-{ 210, "shutdown" },
-{ 211, "sendmsg" },
-{ 212, "recvmsg" },
+{ 207, "recvfrom", recvfromFunc },
+{ 208, "setsockopt", setsockoptFunc },
+{ 209, "getsockopt", getsockoptFunc },
+{ 210, "shutdown", shutdownFunc },
+{ 211, "sendmsg", sendmsgFunc },
+{ 212, "recvmsg", recvmsgFunc },
{ 213, "readahead" },
{ 214, "brk", brkFunc },
{ 215, "munmap", munmapFunc },
@@ -367,7 +367,7 @@
{ 241, "perf_event_open" },
{ 242, "accept4" },
{ 243, "recvmmsg" },
-{ 260, "wait4" },
+{ 260, "wait4", wait4Func },
{ 261, "prlimit64", prlimitFunc },
{ 262, "fanotify_init" },
{ 263, "fanotify_mark" },
@@ -396,18 +396,18 @@
{ 286, "preadv2" },
{ 287, "pwritev2" },
{ 1024, "open", openFunc },
-{ 1025, "link" },
+{ 1025, "link", linkFunc },
{ 1026, "unlink", unlinkFunc },
-{ 1027, "mknod" },
+{ 1027, "mknod", mknodFunc },
{ 1028, "chmod", chmodFunc },
{ 1029, "
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, dev: add VirtIO entropy device(VirtIORng) support
Luming Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55483 )
Change subject: arch-riscv, dev: add VirtIO entropy device(VirtIORng)
support
..
arch-riscv, dev: add VirtIO entropy device(VirtIORng) support
Systemd, which is used by many main stream Linux distributions,
will lead to slow boot if entropy is low. On X86 platforms,
this problem can be alleviated by enabling RDRAND instructions.
However, RISC-V doesn't have similar instructions. For QEMU/KVM,
this problem can be solved by passing randomness from the host
via virtio_rng. But gem5 doesn't have VirtIORng support now.
Some user report that the boot time of riscv-ubuntu-run.py is
too long. To alleviate this problem, this patch add VirtIORng
device support for gem5.
Change-Id: Id93b5703161701212fd6683837034cb0cff590c5
---
M configs/example/riscv/fs_linux.py
A src/dev/virtio/VirtIORng.py
M src/python/gem5/components/boards/riscv_board.py
M src/dev/virtio/SConscript
A src/dev/virtio/rng.cc
A src/dev/virtio/rng.hh
M src/dev/riscv/HiFive.py
7 files changed, 327 insertions(+), 1 deletion(-)
diff --git a/configs/example/riscv/fs_linux.py
b/configs/example/riscv/fs_linux.py
index 2947c1e..ac83e30 100644
--- a/configs/example/riscv/fs_linux.py
+++ b/configs/example/riscv/fs_linux.py
@@ -75,6 +75,7 @@
# linux kernel payload)
# --disk-image (optional): Path to disk image file. Not needed if
using
# ramfs (might run into issues though).
+# --virtio-rng (optional): Enable VirtIO entropy source device
# --command-line (optional):Specify to override default.
# --dtb-filename (optional):Path to DTB file. Auto-generated if empty.
# --bare-metal (boolean): Use baremetal Riscv (default False). Use
this
@@ -129,6 +130,8 @@
parser.add_argument("--dtb-filename", action="store", type=str,
help="Specifies device tree blob file to use with device-tree-"\
"enabled kernels")
+parser.add_argument("--virtio-rng", action="store_true",
+help="Enable VirtIORng device")
# Parse Options --- #
args = parser.parse_args()
@@ -177,6 +180,15 @@
pio_addr=0x10008000
)
+# VirtIORng
+if args.virtio_rng:
+system.platform.rng = MmioVirtIO(
+vio=VirtIORng(),
+interrupt_id=0x8,
+pio_size=4096,
+pio_addr=0x10007000
+)
+
system.bridge = Bridge(delay='50ns')
system.bridge.mem_side_port = system.iobus.cpu_side_ports
system.bridge.cpu_side_port = system.membus.mem_side_ports
diff --git a/src/dev/riscv/HiFive.py b/src/dev/riscv/HiFive.py
index 2923b88..a76e456 100755
--- a/src/dev/riscv/HiFive.py
+++ b/src/dev/riscv/HiFive.py
@@ -126,6 +126,8 @@
devices = [self.uart]
if hasattr(self, "disk"):
devices.append(self.disk)
+if hasattr(self, "rng"):
+devices.append(self.rng)
return devices
def _on_chip_ranges(self):
diff --git a/src/dev/virtio/SConscript b/src/dev/virtio/SConscript
index bf083e7..b00679c 100644
--- a/src/dev/virtio/SConscript
+++ b/src/dev/virtio/SConscript
@@ -44,6 +44,7 @@
'VirtIODeviceBase', 'VirtIODummyDevice', 'PciVirtIO'])
SimObject('VirtIOConsole.py', sim_objects=['VirtIOConsole'])
SimObject('VirtIOBlock.py', sim_objects=['VirtIOBlock'])
+SimObject('VirtIORng.py', sim_objects=['VirtIORng'])
SimObject('VirtIO9P.py', sim_objects=[
'VirtIO9PBase', 'VirtIO9PProxy', 'VirtIO9PDiod', 'VirtIO9PSocket'])
@@ -52,8 +53,10 @@
Source('console.cc')
Source('block.cc')
Source('fs9p.cc')
+Source('rng.cc')
DebugFlag('VIO', 'VirtIO base functionality')
+DebugFlag('VIORng', 'VirtIO entropy source device ')
DebugFlag('VIOIface', 'VirtIO transport')
DebugFlag('VIOConsole', 'VirtIO console device')
DebugFlag('VIOBlock', 'VirtIO block device')
diff --git a/src/dev/virtio/VirtIORng.py b/src/dev/virtio/VirtIORng.py
new file mode 100644
index 000..54848ee
--- /dev/null
+++ b/src/dev/virtio/VirtIORng.py
@@ -0,0 +1,50 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2022 Institute of Computing Technology, Chinese
+# Academy of Sciences
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following condition
[gem5-dev] Change in gem5/gem5[develop]: configs, cpu: fix crashes related to switch_cpus
Luming Wang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/55486 ) Change subject: configs, cpu: fix crashes related to switch_cpus .. configs, cpu: fix crashes related to switch_cpus The decoder objects are turned into SimObjects. However, the decoder objects vector is initialized by calling `createThreads`(defined in BaseCPU.py). However, there is no code calling `createThreads` for switch_cpus. As a result, all functions related to it are broken (e.g. fast-forward, checkpoint). Related commits and JIRA issues: https://gem5-review.googlesource.com/c/public/gem5/+/52080 https://gem5.atlassian.net/browse/GEM5-1145 https://gem5.atlassian.net/browse/GEM5-1156 Change-Id: I4afc326c466627a11fc764fce85394c66c39b59e --- M configs/common/Simulation.py 1 file changed, 25 insertions(+), 0 deletions(-) diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index 3b9efc0..74643f9 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -488,6 +488,7 @@ options.indirect_bp_type) switch_cpus[i].branchPred.indirectBranchPred = \ IndirectBPClass() +switch_cpus[i].createThreads() # If elastic tracing is enabled attach the elastic trace probe # to the switch CPUs @@ -521,6 +522,7 @@ if options.checker: repeat_switch_cpus[i].addCheckerCpu() +repeat_switch_cpus[i].createThreads() testsys.repeat_switch_cpus = repeat_switch_cpus @@ -575,6 +577,8 @@ if options.checker: switch_cpus[i].addCheckerCpu() switch_cpus_1[i].addCheckerCpu() +switch_cpus[i].createThreads() +switch_cpus_1[i].createThreads() testsys.switch_cpus = switch_cpus testsys.switch_cpus_1 = switch_cpus_1 -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/55486 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I4afc326c466627a11fc764fce85394c66c39b59e Gerrit-Change-Number: 55486 Gerrit-PatchSet: 1 Gerrit-Owner: Luming Wang Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: reduced lr/sc implementation
Luming Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55663 )
Change subject: arch-riscv: reduced lr/sc implementation
..
arch-riscv: reduced lr/sc implementation
In gem5::RiscvISA::ISA, handleLocked* functions maintains a address
stack(i.e. locked_addrs) to check whether each SC matches the most
recent LR. However, there are some problems with this implementation.
First, the elements in the stack may only be popped when the
handleLockedSnoop function is invoked. In other cases, the elements
in the stack will not be popped even if the SC and LR match. This
makes the `locked_addrs` get bigger and bigger as gem5 runs.
Second, LR/SC does not always match. For example, in Linux's __cmpxchg[1],
after executing LR, if the value read is not equal to the old value,
the subsequent SC is skipped. For gem5's current implementation, this
would cause the address to be pushed into `locked_addrs` every time
__cmpxchg is failed. But these addresses are never popped. This also
makes the `locked_addrs` get bigger and bigger.
Third, existing emulator implementations (spike, qemu) do not use the
stack, but only record the last address accessed by LR. Afterward,
when executing SC, these implementations determine whether the address
accessed by SC is the same as the one recorded.
This patch modifies gem5's handleLocked* function by referring to
other existing RISC-V implementations. It eliminates `locked_addrs`
and simplifies the related code. Thus, it fixes the "memory leak"-like
error that can occur on `locked_addrs` when executing lr/sc.
Related links:
[1] Linux's cmpxchg implementation for RISC-V:
+
https://github.com/torvalds/linux/blob/master/arch/riscv/include/asm/cmpxchg.h
[2] spike lr/sc implementation:
+
https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/insns/sc_d.h
+
https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/insns/lr_d.h
+
https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/mmu.h
[3] rocket lr/sc implementation:
+
https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/rocket/NBDcache.scala
[4] QEMU lr/sc implementation:
+
https://gitlab.com/qemu-project/qemu/-/blob/master/target/riscv/insn_trans/trans_rva.c.inc
Change-Id: Ic79444cace62e39b7fe9e01f665cb13e4d990d0a
---
M src/arch/riscv/isa.cc
1 file changed, 65 insertions(+), 16 deletions(-)
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index f49a2a8..32cba39 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -504,30 +504,29 @@
const int WARN_FAILURE = 1;
-// RISC-V allows multiple locks per hart, but each SC has to unlock the
most
-// recent one, so we use a stack here.
-std::unordered_map> locked_addrs;
+const Addr INVALID_RESERVATION_ADDR = (Addr) -1;
+std::unordered_map load_reservation_addrs;
void
ISA::handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask)
{
-std::stack& locked_addr_stack = locked_addrs[tc->contextId()];
+Addr& load_reservation_addr = load_reservation_addrs[tc->contextId()];
-if (locked_addr_stack.empty())
+if (load_reservation_addr == INVALID_RESERVATION_ADDR)
return;
Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
DPRINTF(LLSC, "Locked snoop on address %x.\n", snoop_addr);
-if ((locked_addr_stack.top() & cacheBlockMask) == snoop_addr)
-locked_addr_stack.pop();
+if ((load_reservation_addr & cacheBlockMask) == snoop_addr)
+load_reservation_addr = INVALID_RESERVATION_ADDR;
}
void
ISA::handleLockedRead(const RequestPtr &req)
{
-std::stack& locked_addr_stack = locked_addrs[tc->contextId()];
+Addr& load_reservation_addr = load_reservation_addrs[tc->contextId()];
-locked_addr_stack.push(req->getPaddr() & ~0xF);
+load_reservation_addr = req->getPaddr() & ~0xF;
DPRINTF(LLSC, "[cid:%d]: Reserved address %x.\n",
req->contextId(), req->getPaddr() & ~0xF);
}
@@ -535,23 +534,25 @@
bool
ISA::handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask)
{
-std::stack& locked_addr_stack = locked_addrs[tc->contextId()];
+Addr& load_reservation_addr = load_reservation_addrs[tc->contextId()];
+bool lr_addr_empty = (load_reservation_addr ==
INVALID_RESERVATION_ADDR);
// Normally RISC-V uses zero to indicate success and nonzero to
indicate
// failure (right now only 1 is reserved), but in gem5 zero indicates
// failure and one indicates success, so here we conform to that (it
should
// be switched in the instruction's implementation)
-DPRINTF(LLSC, "[cid:%d]: locked_addrs empty? %s.\n", req->contextId(),
-locked_addr_stack.empty() ? "yes" : "no");
-if (!locked_addr_stack.empty()) {
+DPRINTF(LLSC, "[cid:%d]: load_reservation_addrs empty? %s.\n",
+req->contextId(),
+lr_addr_empty ? "yes" : "no
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv, dev: add VirtIO entropy device(VirtIORng) support
Luming Wang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/55483 )
Change subject: arch-riscv, dev: add VirtIO entropy device(VirtIORng)
support
..
arch-riscv, dev: add VirtIO entropy device(VirtIORng) support
Systemd, which is used by many main stream Linux distributions,
will lead to slow boot if entropy is low. On X86 platforms,
this problem can be alleviated by enabling RDRAND instructions.
However, RISC-V doesn't have similar instructions. For QEMU/KVM,
this problem can be solved by passing randomness from the host
via virtio_rng. But gem5 doesn't have VirtIORng support now.
Some user report that the boot time of riscv-ubuntu-run.py is
too long. To alleviate this problem, this patch add VirtIORng
device support for gem5.
Change-Id: Id93b5703161701212fd6683837034cb0cff590c5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55483
Reviewed-by: Bobby Bruce
Maintainer: Bobby Bruce
Tested-by: kokoro
---
M configs/example/riscv/fs_linux.py
A src/dev/virtio/VirtIORng.py
M src/python/gem5/components/boards/riscv_board.py
M src/dev/virtio/SConscript
A src/dev/virtio/rng.cc
A src/dev/virtio/rng.hh
M src/dev/riscv/HiFive.py
7 files changed, 331 insertions(+), 1 deletion(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/example/riscv/fs_linux.py
b/configs/example/riscv/fs_linux.py
index 2947c1e..570ef22 100644
--- a/configs/example/riscv/fs_linux.py
+++ b/configs/example/riscv/fs_linux.py
@@ -75,6 +75,7 @@
# linux kernel payload)
# --disk-image (optional): Path to disk image file. Not needed if
using
# ramfs (might run into issues though).
+# --virtio-rng (optional): Enable VirtIO entropy source device
# --command-line (optional):Specify to override default.
# --dtb-filename (optional):Path to DTB file. Auto-generated if empty.
# --bare-metal (boolean): Use baremetal Riscv (default False). Use
this
@@ -129,6 +130,8 @@
parser.add_argument("--dtb-filename", action="store", type=str,
help="Specifies device tree blob file to use with device-tree-"\
"enabled kernels")
+parser.add_argument("--virtio-rng", action="store_true",
+help="Enable VirtIORng device")
# Parse Options --- #
args = parser.parse_args()
@@ -177,6 +180,15 @@
pio_addr=0x10008000
)
+# VirtIORng
+if args.virtio_rng:
+system.platform.rng = RiscvMmioVirtIO(
+vio=VirtIORng(),
+interrupt_id=0x8,
+pio_size=4096,
+pio_addr=0x10007000
+)
+
system.bridge = Bridge(delay='50ns')
system.bridge.mem_side_port = system.iobus.cpu_side_ports
system.bridge.cpu_side_port = system.membus.mem_side_ports
diff --git a/src/dev/riscv/HiFive.py b/src/dev/riscv/HiFive.py
index 2923b88..a76e456 100755
--- a/src/dev/riscv/HiFive.py
+++ b/src/dev/riscv/HiFive.py
@@ -126,6 +126,8 @@
devices = [self.uart]
if hasattr(self, "disk"):
devices.append(self.disk)
+if hasattr(self, "rng"):
+devices.append(self.rng)
return devices
def _on_chip_ranges(self):
diff --git a/src/dev/virtio/SConscript b/src/dev/virtio/SConscript
index bf083e7..b00679c 100644
--- a/src/dev/virtio/SConscript
+++ b/src/dev/virtio/SConscript
@@ -44,6 +44,7 @@
'VirtIODeviceBase', 'VirtIODummyDevice', 'PciVirtIO'])
SimObject('VirtIOConsole.py', sim_objects=['VirtIOConsole'])
SimObject('VirtIOBlock.py', sim_objects=['VirtIOBlock'])
+SimObject('VirtIORng.py', sim_objects=['VirtIORng'])
SimObject('VirtIO9P.py', sim_objects=[
'VirtIO9PBase', 'VirtIO9PProxy', 'VirtIO9PDiod', 'VirtIO9PSocket'])
@@ -52,8 +53,10 @@
Source('console.cc')
Source('block.cc')
Source('fs9p.cc')
+Source('rng.cc')
DebugFlag('VIO', 'VirtIO base functionality')
+DebugFlag('VIORng', 'VirtIO entropy source device ')
DebugFlag('VIOIface', 'VirtIO transport')
DebugFlag('VIOConsole', 'VirtIO console device')
DebugFlag('VIOBlock', 'VirtIO block device')
diff --git a/src/dev/virtio/VirtIORng.py b/src/dev/virtio/VirtIORng.py
new file mode 100644
index 000..54848ee
--- /dev/null
+++ b/src/dev/virtio/VirtIORng.py
@@ -0,0 +1,50 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2022 Institute of Computing Technology, Chinese
+# Academy of Sciences
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its ent
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: reduced lr/sc implementation
Luming Wang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/55663 )
Change subject: arch-riscv: reduced lr/sc implementation
..
arch-riscv: reduced lr/sc implementation
In gem5::RiscvISA::ISA, handleLocked* functions maintain an address
stack(i.e. locked_addrs) to check whether each SC matches the most
recent LR. However, there are some problems with this implementation.
First, the elements in the stack may only be popped when the
handleLockedSnoop function is invoked. In other cases, the elements
in the stack will not be popped even if the SC and LR match. This
makes the `locked_addrs` get bigger and bigger as gem5 runs.
Second, LR/SC does not always match. For example, in Linux's __cmpxchg[1],
after executing LR, if the value read is not equal to the old value,
the subsequent SC is skipped. For gem5's current implementation, this
would cause the address to be pushed into `locked_addrs` every time
__cmpxchg is failed. But these addresses are never popped. This also
makes the `locked_addrs` get bigger and bigger.
Third, existing emulator implementations (spike, qemu) do not use the
stack, but only record the last address accessed by LR. Afterward,
when executing SC, these implementations determine whether the address
accessed by SC is the same as the one recorded.
This patch modifies gem5's handleLocked* function by referring to
other existing RISC-V implementations. It eliminates `locked_addrs`
and simplifies the related code. Thus, it fixes the "memory leak"-like
error that can occur on `locked_addrs` when executing LR/SC.
Related links:
[1] Linux's cmpxchg implementation for RISC-V:
+
https://github.com/torvalds/linux/blob/master/arch/riscv/include/asm/cmpxchg.h
[2] spike lr/sc implementation:
+
https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/insns/sc_d.h
+
https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/insns/lr_d.h
+
https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/mmu.h
[3] rocket lr/sc implementation:
+
https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/rocket/NBDcache.scala
[4] QEMU lr/sc implementation:
+
https://gitlab.com/qemu-project/qemu/-/blob/master/target/riscv/insn_trans/trans_rva.c.inc
Change-Id: Ic79444cace62e39b7fe9e01f665cb13e4d990d0a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55663
Reviewed-by: Bobby Bruce
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/riscv/isa.cc
1 file changed, 70 insertions(+), 16 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
Bobby Bruce: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index f49a2a8..32cba39 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -504,30 +504,29 @@
const int WARN_FAILURE = 1;
-// RISC-V allows multiple locks per hart, but each SC has to unlock the
most
-// recent one, so we use a stack here.
-std::unordered_map> locked_addrs;
+const Addr INVALID_RESERVATION_ADDR = (Addr) -1;
+std::unordered_map load_reservation_addrs;
void
ISA::handleLockedSnoop(PacketPtr pkt, Addr cacheBlockMask)
{
-std::stack& locked_addr_stack = locked_addrs[tc->contextId()];
+Addr& load_reservation_addr = load_reservation_addrs[tc->contextId()];
-if (locked_addr_stack.empty())
+if (load_reservation_addr == INVALID_RESERVATION_ADDR)
return;
Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
DPRINTF(LLSC, "Locked snoop on address %x.\n", snoop_addr);
-if ((locked_addr_stack.top() & cacheBlockMask) == snoop_addr)
-locked_addr_stack.pop();
+if ((load_reservation_addr & cacheBlockMask) == snoop_addr)
+load_reservation_addr = INVALID_RESERVATION_ADDR;
}
void
ISA::handleLockedRead(const RequestPtr &req)
{
-std::stack& locked_addr_stack = locked_addrs[tc->contextId()];
+Addr& load_reservation_addr = load_reservation_addrs[tc->contextId()];
-locked_addr_stack.push(req->getPaddr() & ~0xF);
+load_reservation_addr = req->getPaddr() & ~0xF;
DPRINTF(LLSC, "[cid:%d]: Reserved address %x.\n",
req->contextId(), req->getPaddr() & ~0xF);
}
@@ -535,23 +534,25 @@
bool
ISA::handleLockedWrite(const RequestPtr &req, Addr cacheBlockMask)
{
-std::stack& locked_addr_stack = locked_addrs[tc->contextId()];
+Addr& load_reservation_addr = load_reservation_addrs[tc->contextId()];
+bool lr_addr_empty = (load_reservation_addr ==
INVALID_RESERVATION_ADDR);
// Normally RISC-V uses zero to indicate success and nonzero to
indicate
// failure (right now only 1 is reserved), but in gem5 zero indicates
// failure and one indicates success, so here we conform to that (it
should
// be switched in
[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fix memory leak problem in page table walker
Luming Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56609 )
Change subject: arch-riscv: fix memory leak problem in page table walker
..
arch-riscv: fix memory leak problem in page table walker
Valgrind detects memory leak problems in RISC-V's page table
walker(`Walker::WalkerState::stepWalk()`). In some situation,
the response packet is not freed. This patch partially fix
these memory leak problems.
Change-Id: I86d4c69c3c502bd92856a3d8863bfa1722a94512
---
M src/arch/riscv/pagetable_walker.cc
1 file changed, 20 insertions(+), 0 deletions(-)
diff --git a/src/arch/riscv/pagetable_walker.cc
b/src/arch/riscv/pagetable_walker.cc
index 81d1eb2..43adf78 100644
--- a/src/arch/riscv/pagetable_walker.cc
+++ b/src/arch/riscv/pagetable_walker.cc
@@ -426,6 +426,10 @@
//If we didn't return, we're setting up another read.
RequestPtr request = std::make_shared(
nextRead, oldRead->getSize(), flags, walker->requestorId);
+
+delete oldRead;
+oldRead = NULL;
+
read = new Packet(request, MemCmd::ReadReq);
read->allocate();
@@ -501,6 +505,8 @@
}
sendPackets();
} else {
+delete pkt;
+
sendPackets();
}
if (inflight == 0 && read == NULL && writes.size() == 0) {
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I86d4c69c3c502bd92856a3d8863bfa1722a94512
Gerrit-Change-Number: 56609
Gerrit-PatchSet: 1
Gerrit-Owner: Luming Wang
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv,sim-se: correct the spelling of `sendto`
Luming Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56689 )
Change subject: arch-riscv,sim-se: correct the spelling of `sendto`
..
arch-riscv,sim-se: correct the spelling of `sendto`
The system call "sendto" is incorrectly written as "sendo".
This patch fixes this spelling error and adds support for `sendto`.
Change-Id: I21851fe7679509161b09d335a5df9640c8334430
---
M src/arch/riscv/linux/se_workload.cc
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/src/arch/riscv/linux/se_workload.cc
b/src/arch/riscv/linux/se_workload.cc
index 815b63b..b321ffc 100644
--- a/src/arch/riscv/linux/se_workload.cc
+++ b/src/arch/riscv/linux/se_workload.cc
@@ -329,7 +329,7 @@
{ 203, "connect", connectFunc },
{ 204, "getsockname", getsocknameFunc },
{ 205, "getpeername", getpeernameFunc },
-{ 206, "sendo" },
+{ 206, "sendto", sendtoFunc },
{ 207, "recvfrom", recvfromFunc },
{ 208, "setsockopt", setsockoptFunc },
{ 209, "getsockopt", getsockoptFunc },
@@ -660,7 +660,7 @@
{ 203, "connect", connectFunc },
{ 204, "getsockname", getsocknameFunc },
{ 205, "getpeername", getpeernameFunc },
-{ 206, "sendo" },
+{ 206, "sendto", sendtoFunc },
{ 207, "recvfrom", recvfromFunc },
{ 208, "setsockopt", setsockoptFunc },
{ 209, "getsockopt", getsockoptFunc },
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I21851fe7679509161b09d335a5df9640c8334430
Gerrit-Change-Number: 56689
Gerrit-PatchSet: 1
Gerrit-Owner: Luming Wang
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv,sim-se: correct the spelling of `sendto`
Luming Wang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/56689 )
Change subject: arch-riscv,sim-se: correct the spelling of `sendto`
..
arch-riscv,sim-se: correct the spelling of `sendto`
The system call "sendto" is incorrectly written as "sendo".
This patch fixes this spelling error and adds support for `sendto`.
Change-Id: I21851fe7679509161b09d335a5df9640c8334430
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56689
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/riscv/linux/se_workload.cc
1 file changed, 18 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/linux/se_workload.cc
b/src/arch/riscv/linux/se_workload.cc
index 815b63b..b321ffc 100644
--- a/src/arch/riscv/linux/se_workload.cc
+++ b/src/arch/riscv/linux/se_workload.cc
@@ -329,7 +329,7 @@
{ 203, "connect", connectFunc },
{ 204, "getsockname", getsocknameFunc },
{ 205, "getpeername", getpeernameFunc },
-{ 206, "sendo" },
+{ 206, "sendto", sendtoFunc },
{ 207, "recvfrom", recvfromFunc },
{ 208, "setsockopt", setsockoptFunc },
{ 209, "getsockopt", getsockoptFunc },
@@ -660,7 +660,7 @@
{ 203, "connect", connectFunc },
{ 204, "getsockname", getsocknameFunc },
{ 205, "getpeername", getpeernameFunc },
-{ 206, "sendo" },
+{ 206, "sendto", sendtoFunc },
{ 207, "recvfrom", recvfromFunc },
{ 208, "setsockopt", setsockoptFunc },
{ 209, "getsockopt", getsockoptFunc },
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I21851fe7679509161b09d335a5df9640c8334430
Gerrit-Change-Number: 56689
Gerrit-PatchSet: 2
Gerrit-Owner: Luming Wang
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Luming Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fix memory leak problem in page table walker
Luming Wang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/56609 )
Change subject: arch-riscv: fix memory leak problem in page table walker
..
arch-riscv: fix memory leak problem in page table walker
Valgrind detects memory leak problems in RISC-V's page table
walker(`Walker::WalkerState::stepWalk()`). In some situation,
the response packet is not freed. This patch partially fix
these memory leak problems.
Change-Id: I86d4c69c3c502bd92856a3d8863bfa1722a94512
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56609
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Reviewed-by: Ayaz Akram
Tested-by: kokoro
---
M src/arch/riscv/pagetable_walker.cc
1 file changed, 25 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Ayaz Akram: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/pagetable_walker.cc
b/src/arch/riscv/pagetable_walker.cc
index 81d1eb2..cbd5bd2 100644
--- a/src/arch/riscv/pagetable_walker.cc
+++ b/src/arch/riscv/pagetable_walker.cc
@@ -426,6 +426,10 @@
//If we didn't return, we're setting up another read.
RequestPtr request = std::make_shared(
nextRead, oldRead->getSize(), flags, walker->requestorId);
+
+delete oldRead;
+oldRead = nullptr;
+
read = new Packet(request, MemCmd::ReadReq);
read->allocate();
@@ -501,6 +505,8 @@
}
sendPackets();
} else {
+delete pkt;
+
sendPackets();
}
if (inflight == 0 && read == NULL && writes.size() == 0) {
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I86d4c69c3c502bd92856a3d8863bfa1722a94512
Gerrit-Change-Number: 56609
Gerrit-PatchSet: 3
Gerrit-Owner: Luming Wang
Gerrit-Reviewer: Ayaz Akram
Gerrit-Reviewer: Hoa Nguyen
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Luming Wang
Gerrit-Reviewer: Nils Asmussen
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim-se: add getrandom() syscall support
Luming Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/57809 )
Change subject: sim-se: add getrandom() syscall support
..
sim-se: add getrandom() syscall support
getrandom() was introduced in version 3.17 of the Linux kernel.
This commit implements getrandom() for Gem5 SE mode.
Change-Id: I86bfeee52048184dbf72330284933b70daab5850
---
M src/arch/arm/linux/se_workload.cc
M src/arch/riscv/linux/se_workload.cc
M src/arch/x86/linux/syscall_tbl32.cc
M src/arch/x86/linux/syscall_tbl64.cc
M src/sim/syscall_emul.hh
5 files changed, 37 insertions(+), 3 deletions(-)
diff --git a/src/arch/arm/linux/se_workload.cc
b/src/arch/arm/linux/se_workload.cc
index b511e02..f0c85ae 100644
--- a/src/arch/arm/linux/se_workload.cc
+++ b/src/arch/arm/linux/se_workload.cc
@@ -488,6 +488,7 @@
{ base + 363, "sys_rt_tgsigqueueinfo" },
{ base + 364, "sys_perf_event_open" },
{ base + 365, "sys_recvmmsg" },
+{ base + 384, "getrandom", getrandomFunc }
})
{}
};
@@ -758,6 +759,7 @@
{ base + 269, "sendmmsg" },
{ base + 270, "process_vm_readv" },
{ base + 271, "process_vm_writev" },
+{ base + 278, "getrandom", getrandomFunc },
{ base + 1024, "open", openFunc },
{ base + 1025, "link" },
{ base + 1026, "unlink", unlinkFunc },
diff --git a/src/arch/riscv/linux/se_workload.cc
b/src/arch/riscv/linux/se_workload.cc
index b321ffc..f8053d4 100644
--- a/src/arch/riscv/linux/se_workload.cc
+++ b/src/arch/riscv/linux/se_workload.cc
@@ -385,7 +385,7 @@
{ 275, "sched_getattr" },
{ 276, "renameat2" },
{ 277, "seccomp" },
-{ 278, "getrandom" },
+{ 278, "getrandom", getrandomFunc },
{ 279, "memfd_create" },
{ 280, "bpf" },
{ 281, "execveat" },
@@ -716,7 +716,7 @@
{ 275, "sched_getattr" },
{ 276, "renameat2" },
{ 277, "seccomp" },
-{ 278, "getrandom" },
+{ 278, "getrandom", getrandomFunc },
{ 279, "memfd_create" },
{ 280, "bpf" },
{ 281, "execveat" },
diff --git a/src/arch/x86/linux/syscall_tbl32.cc
b/src/arch/x86/linux/syscall_tbl32.cc
index 7f8e905..2de334c 100644
--- a/src/arch/x86/linux/syscall_tbl32.cc
+++ b/src/arch/x86/linux/syscall_tbl32.cc
@@ -370,7 +370,8 @@
{ 320, "utimensat" },
{ 321, "signalfd" },
{ 322, "timerfd" },
-{ 323, "eventfd", eventfdFunc }
+{ 323, "eventfd", eventfdFunc },
+{ 355, "getrandom", getrandomFunc}
};
} // namespace X86ISA
diff --git a/src/arch/x86/linux/syscall_tbl64.cc
b/src/arch/x86/linux/syscall_tbl64.cc
index 27ee8ec..6b6fa2a 100644
--- a/src/arch/x86/linux/syscall_tbl64.cc
+++ b/src/arch/x86/linux/syscall_tbl64.cc
@@ -361,6 +361,7 @@
{ 311, "proess_vm_writev" },
{ 312, "kcmp" },
{ 313, "finit_module" },
+{ 318, "getrandom", getrandomFunc }
};
} // namespace X86ISA
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 3fe1cf0..59a97d9 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -90,6 +90,7 @@
#include "base/intmath.hh"
#include "base/loader/object_file.hh"
#include "base/logging.hh"
+#include "base/random.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
@@ -3040,6 +3041,23 @@
return (result == -1) ? -errno : result;
}
+template
+SyscallReturn
+getrandomFunc(SyscallDesc *desc, ThreadContext *tc,
+ VPtr<> buf_ptr, typename OS::size_t count,
+ unsigned int flags)
+{
+SETranslatingPortProxy proxy(tc);
+
+TypedBufferArg buf(buf_ptr, count);
+for (int i = 0; i < count; ++i) {
+buf[i] = gem5::random_mt.random();
+}
+buf.copyOut(proxy);
+
+return count;
+}
+
} // namespace gem5
#endif // __SIM_SYSCALL_EMUL_HH__
--
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Gerrit-Branch: develop
Gerrit-Change-Id: I86bfeee52048184dbf72330284933b70daab5850
Gerrit-Change-Number: 57809
Gerrit-PatchSet: 1
Gerrit-Owner: Luming Wang
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: sim-se: add getrandom() syscall support
Luming Wang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/57809 )
Change subject: sim-se: add getrandom() syscall support
..
sim-se: add getrandom() syscall support
getrandom() was introduced in version 3.17 of the Linux kernel.
This commit implements getrandom() for Gem5 SE mode.
Change-Id: I86bfeee52048184dbf72330284933b70daab5850
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57809
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Tested-by: kokoro
Reviewed-by: Giacomo Travaglini
---
M src/arch/arm/linux/se_workload.cc
M src/arch/riscv/linux/se_workload.cc
M src/arch/x86/linux/syscall_tbl32.cc
M src/arch/x86/linux/syscall_tbl64.cc
M src/sim/syscall_emul.hh
5 files changed, 42 insertions(+), 3 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, but someone else must approve; Looks
good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/linux/se_workload.cc
b/src/arch/arm/linux/se_workload.cc
index b511e02..f0c85ae 100644
--- a/src/arch/arm/linux/se_workload.cc
+++ b/src/arch/arm/linux/se_workload.cc
@@ -488,6 +488,7 @@
{ base + 363, "sys_rt_tgsigqueueinfo" },
{ base + 364, "sys_perf_event_open" },
{ base + 365, "sys_recvmmsg" },
+{ base + 384, "getrandom", getrandomFunc }
})
{}
};
@@ -758,6 +759,7 @@
{ base + 269, "sendmmsg" },
{ base + 270, "process_vm_readv" },
{ base + 271, "process_vm_writev" },
+{ base + 278, "getrandom", getrandomFunc },
{ base + 1024, "open", openFunc },
{ base + 1025, "link" },
{ base + 1026, "unlink", unlinkFunc },
diff --git a/src/arch/riscv/linux/se_workload.cc
b/src/arch/riscv/linux/se_workload.cc
index b321ffc..f8053d4 100644
--- a/src/arch/riscv/linux/se_workload.cc
+++ b/src/arch/riscv/linux/se_workload.cc
@@ -385,7 +385,7 @@
{ 275, "sched_getattr" },
{ 276, "renameat2" },
{ 277, "seccomp" },
-{ 278, "getrandom" },
+{ 278, "getrandom", getrandomFunc },
{ 279, "memfd_create" },
{ 280, "bpf" },
{ 281, "execveat" },
@@ -716,7 +716,7 @@
{ 275, "sched_getattr" },
{ 276, "renameat2" },
{ 277, "seccomp" },
-{ 278, "getrandom" },
+{ 278, "getrandom", getrandomFunc },
{ 279, "memfd_create" },
{ 280, "bpf" },
{ 281, "execveat" },
diff --git a/src/arch/x86/linux/syscall_tbl32.cc
b/src/arch/x86/linux/syscall_tbl32.cc
index 7f8e905..2de334c 100644
--- a/src/arch/x86/linux/syscall_tbl32.cc
+++ b/src/arch/x86/linux/syscall_tbl32.cc
@@ -370,7 +370,8 @@
{ 320, "utimensat" },
{ 321, "signalfd" },
{ 322, "timerfd" },
-{ 323, "eventfd", eventfdFunc }
+{ 323, "eventfd", eventfdFunc },
+{ 355, "getrandom", getrandomFunc}
};
} // namespace X86ISA
diff --git a/src/arch/x86/linux/syscall_tbl64.cc
b/src/arch/x86/linux/syscall_tbl64.cc
index 27ee8ec..6b6fa2a 100644
--- a/src/arch/x86/linux/syscall_tbl64.cc
+++ b/src/arch/x86/linux/syscall_tbl64.cc
@@ -361,6 +361,7 @@
{ 311, "proess_vm_writev" },
{ 312, "kcmp" },
{ 313, "finit_module" },
+{ 318, "getrandom", getrandomFunc }
};
} // namespace X86ISA
diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 3fe1cf0..59a97d9 100644
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -90,6 +90,7 @@
#include "base/intmath.hh"
#include "base/loader/object_file.hh"
#include "base/logging.hh"
+#include "base/random.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
@@ -3040,6 +3041,23 @@
return (result == -1) ? -errno : result;
}
+template
+SyscallReturn
+getrandomFunc(SyscallDesc *desc, ThreadContext *tc,
+ VPtr<> buf_ptr, typename OS::size_t count,
+ unsigned int flags)
+{
+SETranslatingPortProxy proxy(tc);
+
+TypedBufferArg buf(buf_ptr, count);
+for (int i = 0; i < count; ++i) {
+buf[i] = gem5::random_mt.random();
+}
+buf.copyOut(proxy);
+
+return count;
+}
+
} // namespace gem5
#endif // __SIM_SYSCALL_EMUL_HH__
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I86bfeee52048184dbf72330284933b70daab5850
Gerrit-Change-Number: 57809
Gerrit-PatchSet: 2
Gerrit-Owner: Luming Wang
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Luming Wang
Gerrit-Reviewer: Srikant Bharadwaj
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: scons: fix build failed caused by Non-ASCII directory path
Luming Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58369 )
Change subject: scons: fix build failed caused by Non-ASCII directory path
..
scons: fix build failed caused by Non-ASCII directory path
This path fix build failed when gem5's path contains Non-ASCII
characters.
build_tools/marshal.py embed "abspath" and "modpath" into the
generated c++ file. However, if either of them contains Non-ASCII
characters, marshal.py will throw an exception.
This can be fixed if we set a suitable $LANG for gem5py. For
example, we can simply set $LANG=en_US.UTF-8 in src/SConscript
to fix this.
This patch fixes this bug by passing the host's $LANG environment
variable to gem5py. Because for users who may use Non-ASCII
characters, their $LANG is generally set to their native language
(e.g. zh_CN.UTF-8, en_US.UTF-8, etc.), which contains Non-ASCII
characters. Also, it is more reasonable to use the host $LANG than
to directly hard-code the $LANG used by gem5py into a language
that supports non-ASCII characters.
Change-Id: Ia0343cbd6995af3a9e43bf217ad3f186d5633fed
---
M src/SConscript
1 file changed, 29 insertions(+), 0 deletions(-)
diff --git a/src/SConscript b/src/SConscript
index c1b00f0..b760dfe 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -87,6 +87,7 @@
gem5py_m5 = gem5py_env.File('gem5py_m5')
gem5py_env['GEM5PY'] = gem5py
gem5py_env['GEM5PY_M5'] = gem5py_m5
+gem5py_env['ENV']['LANG'] = os.environ.get('LANG', 'en_US.UTF-8')
gem5py_env['OBJSUFFIX'] = '.pyo'
# Inject build_tools into PYTHONPATH for when we run gem5py.
pythonpath = gem5py_env['ENV'].get('PYTHONPATH', '').split(':')
--
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[gem5-dev] [S] Change in gem5/gem5[develop]: scons: fix build failed caused by Non-ASCII directory path
Luming Wang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/58369 ) Change subject: scons: fix build failed caused by Non-ASCII directory path .. scons: fix build failed caused by Non-ASCII directory path This path fix build failed when gem5's path contains Non-ASCII characters. build_tools/marshal.py embed "abspath" and "modpath" into the generated c++ file. However, if either of them contains Non-ASCII characters, marshal.py will throw an exception. This can be fixed if we set a suitable $LANG for gem5py. For example, we can simply set $LANG=en_US.UTF-8 in src/SConscript to fix this. This patch fixes this bug by passing the host's $LANG environment variable to gem5py. Because for users who may use Non-ASCII characters, their $LANG is generally set to their native language (e.g. zh_CN.UTF-8, en_US.UTF-8, etc.), which contains Non-ASCII characters. Also, it is more reasonable to use the host $LANG than to directly hard-code the $LANG used by gem5py into a language that supports non-ASCII characters. Change-Id: Ia0343cbd6995af3a9e43bf217ad3f186d5633fed Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/58369 Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- M site_scons/gem5_scons/defaults.py 1 file changed, 33 insertions(+), 1 deletion(-) Approvals: Gabe Black: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/site_scons/gem5_scons/defaults.py b/site_scons/gem5_scons/defaults.py index 4382937..7a24589 100644 --- a/site_scons/gem5_scons/defaults.py +++ b/site_scons/gem5_scons/defaults.py @@ -48,7 +48,7 @@ 'LIBRARY_PATH', 'PATH', 'PKG_CONFIG_PATH', 'PROTOC', 'PYTHONPATH', 'RANLIB', 'TERM', 'PYTHON_CONFIG', 'CCFLAGS_EXTRA', 'GEM5PY_CCFLAGS_EXTRA', - 'GEM5PY_LINKFLAGS_EXTRA', 'LINKFLAGS_EXTRA']) + 'GEM5PY_LINKFLAGS_EXTRA', 'LINKFLAGS_EXTRA', 'LANG']) use_prefixes = [ "ASAN_", # address sanitizer symbolizer path and settings -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/58369 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: Ia0343cbd6995af3a9e43bf217ad3f186d5633fed Gerrit-Change-Number: 58369 Gerrit-PatchSet: 4 Gerrit-Owner: Luming Wang Gerrit-Reviewer: Gabe Black Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Luming Wang Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-dev] [XS] Change in gem5/gem5[develop]: scons: fix build failed caused by Non-ASCII directory path
Luming Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/70818?usp=email )
Change subject: scons: fix build failed caused by Non-ASCII directory path
..
scons: fix build failed caused by Non-ASCII directory path
This patch addresses the issue of gem5 failing to build when
the build directory path contains non-ASCII characters.
The previous patches[1] that attempted to fix this issue
became ineffective after the upgrade of Python and pybind11
to new versions. This new patch manually sets the locale in
marshal.py based on the `LC_CTYPE` environment variable,
providing a comprehensive solution that works with Non-ASCII
build directory paths.
[1] https://gem5-review.googlesource.com/c/public/gem5/+/58369
Change-Id: I3ad28b6ee52fd347d2fe71f279baab629e88d12c
---
M build_tools/marshal.py
M site_scons/gem5_scons/defaults.py
2 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/build_tools/marshal.py b/build_tools/marshal.py
index 18afe2c..e93921b 100644
--- a/build_tools/marshal.py
+++ b/build_tools/marshal.py
@@ -48,6 +48,7 @@
this script, and to read in and execute the marshalled code later.
"""
+import locale
import marshal
import sys
import zlib
@@ -65,6 +66,11 @@
print(f"Usage: {sys.argv[0]} CPP PY MODPATH ABSPATH", file=sys.stderr)
sys.exit(1)
+# Set the Python's locale settings manually based on the `LANG`
+# environment variable
+if 'LC_CTYPE' in os.environ:
+locale.setlocale(locale.LC_CTYPE, os.environ["LC_CTYPE"])
+
_, cpp, python, modpath, abspath = sys.argv
with open(python, "r") as f:
diff --git a/site_scons/gem5_scons/defaults.py
b/site_scons/gem5_scons/defaults.py
index a07b7ff..996cfd4 100644
--- a/site_scons/gem5_scons/defaults.py
+++ b/site_scons/gem5_scons/defaults.py
@@ -66,6 +66,7 @@
"GEM5PY_LINKFLAGS_EXTRA",
"LINKFLAGS_EXTRA",
"LANG",
+"LC_CTYPE",
]
)
--
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[gem5-dev] [XS] Change in gem5/gem5[develop]: scons: fix build failed caused by Non-ASCII directory path
Luming Wang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70818?usp=email )
Change subject: scons: fix build failed caused by Non-ASCII directory path
..
scons: fix build failed caused by Non-ASCII directory path
This patch addresses the issue of gem5 failing to build when
the build directory path contains non-ASCII characters.
The previous patches[1] that attempted to fix this issue
became ineffective after the upgrade of Python and pybind11
to new versions. This new patch manually sets the locale in
marshal.py based on the `LC_CTYPE` environment variable,
providing a comprehensive solution that works with Non-ASCII
build directory paths.
[1] https://gem5-review.googlesource.com/c/public/gem5/+/58369
Change-Id: I3ad28b6ee52fd347d2fe71f279baab629e88d12c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70818
Tested-by: kokoro
Reviewed-by: Bobby Bruce
Maintainer: Bobby Bruce
---
M build_tools/marshal.py
M site_scons/gem5_scons/defaults.py
2 files changed, 7 insertions(+), 0 deletions(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/build_tools/marshal.py b/build_tools/marshal.py
index 18afe2c..4a1522f 100644
--- a/build_tools/marshal.py
+++ b/build_tools/marshal.py
@@ -48,6 +48,7 @@
this script, and to read in and execute the marshalled code later.
"""
+import locale
import marshal
import sys
import zlib
@@ -65,6 +66,11 @@
print(f"Usage: {sys.argv[0]} CPP PY MODPATH ABSPATH", file=sys.stderr)
sys.exit(1)
+# Set the Python's locale settings manually based on the `LC_CTYPE`
+# environment variable
+if "LC_CTYPE" in os.environ:
+locale.setlocale(locale.LC_CTYPE, os.environ["LC_CTYPE"])
+
_, cpp, python, modpath, abspath = sys.argv
with open(python, "r") as f:
diff --git a/site_scons/gem5_scons/defaults.py
b/site_scons/gem5_scons/defaults.py
index a07b7ff..996cfd4 100644
--- a/site_scons/gem5_scons/defaults.py
+++ b/site_scons/gem5_scons/defaults.py
@@ -66,6 +66,7 @@
"GEM5PY_LINKFLAGS_EXTRA",
"LINKFLAGS_EXTRA",
"LANG",
+"LC_CTYPE",
]
)
--
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Gerrit-Change-Id: I3ad28b6ee52fd347d2fe71f279baab629e88d12c
Gerrit-Change-Number: 70818
Gerrit-PatchSet: 4
Gerrit-Owner: Luming Wang
Gerrit-Reviewer: Bobby Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Luming Wang
Gerrit-Reviewer: kokoro
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[gem5-dev] [S] Change in gem5/gem5[develop]: sim,python: follow the new CPython startup sequence
Luming Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/70898?usp=email )
Change subject: sim,python: follow the new CPython startup sequence
..
sim,python: follow the new CPython startup sequence
Currently, gem5 suffers from several bugs related
to Python interpreter's locale encoding issues.
gem5 will crash when the working directory contains
Non-ASCII characters.
The reason is that Python 3.8+ introduces a new
interpreter startup sequence [1]. The startup
sequence consists of three phases:
1. Python core runtime preinitialization
2. Python core runtime initialization
3. Main interpreter configuration
Stage 1 determining the encodings used for system
interfaces.
However, gem5 doesn't preinitialize the Python
interpreter. Thus, the locale settings do not take
effect. This patch preinitialize the Python for
Python 3.8+.
Also, this patch avoid the use of `Py_SetProgramName`,
which is deprecated since Python 3.11[3].
[1] https://peps.python.org/pep-0432/
[2] https://peps.python.org/pep-0587/
[3] https://docs.python.org/3/c-api/init.html#c.Py_SetProgramName
Change-Id: I08a2ec6ab2b39a95ab194909932c8fc578c745ce
---
M src/python/gem5py.cc
M src/sim/main.cc
2 files changed, 33 insertions(+), 0 deletions(-)
diff --git a/src/python/gem5py.cc b/src/python/gem5py.cc
index f2d8759..37ddee2 100644
--- a/src/python/gem5py.cc
+++ b/src/python/gem5py.cc
@@ -51,6 +51,21 @@
int
main(int argc, const char **argv)
{
+#if PY_VERSION_HEX >= 0x0308
+// Preinitialize Python for Python 3.8+
+// This ensures that the locale configuration takes effect
+PyStatus status;
+PyPreConfig preconfig;
+PyPreConfig_InitPythonConfig(&preconfig);
+
+preconfig.utf8_mode = 1;
+
+status = Py_PreInitialize(&preconfig);
+if (PyStatus_Exception(status)) {
+Py_ExitStatusException(status);
+}
+#endif
+
py::scoped_interpreter guard;
// Embedded python doesn't set up sys.argv, so we'll do that ourselves.
diff --git a/src/sim/main.cc b/src/sim/main.cc
index 81a691d..1c42891 100644
--- a/src/sim/main.cc
+++ b/src/sim/main.cc
@@ -50,6 +50,7 @@
// Initialize gem5 special signal handling.
initSignals();
+#if PY_VERSION_HEX < 0x0308
// Convert argv[0] to a wchar_t string, using python's locale and
cleanup
// functions.
std::unique_ptr program(
@@ -59,6 +60,23 @@
// This can help python find libraries at run time relative to this
binary.
// It's probably not necessary, but is mostly harmless and might be
useful.
Py_SetProgramName(program.get());
+#else
+// Preinitialize Python for Python 3.8+
+// This ensures that the locale configuration takes effect
+PyStatus status;
+
+PyConfig config;
+PyConfig_InitPythonConfig(&config);
+
+/* Set the program name. Implicitly preinitialize Python. */
+status = PyConfig_SetBytesString(&config, &config.program_name,
+ argv[0]);
+if (PyStatus_Exception(status)) {
+PyConfig_Clear(&config);
+Py_ExitStatusException(status);
+return 1;
+}
+#endif
py::scoped_interpreter guard(true, argc, argv);
--
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