[gem5-dev] [XS] Change in gem5/gem5[develop]: dev: Warn when resp packet is error in dma port
Wei-Han Chen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/71778?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: dev: Warn when resp packet is error in dma port
..
dev: Warn when resp packet is error in dma port
This CL adds a warning when the response packet is error.
Change-Id: I8e94dc2b85cd1753a4d6265cfda3cd5d6325f425
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71778
Reviewed-by: Jason Lowe-Power
Maintainer: Jason Lowe-Power
Reviewed-by: Yu-hsin Wang
Tested-by: kokoro
---
M src/dev/dma_device.cc
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
Yu-hsin Wang: Looks good to me, but someone else must approve
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index 24e931e..70a74ee 100644
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -68,6 +68,7 @@
{
// Should always see a response with a sender state.
assert(pkt->isResponse());
+warn_if(pkt->isError(), "Response pkt error.");
// Get the DMA sender state.
auto *state = dynamic_cast(pkt->senderState);
--
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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8e94dc2b85cd1753a4d6265cfda3cd5d6325f425
Gerrit-Change-Number: 71778
Gerrit-PatchSet: 3
Gerrit-Owner: Wei-Han Chen
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Jason Lowe-Power
Gerrit-Reviewer: Wei-Han Chen
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-CC: kokoro
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[gem5-dev] [XS] Change in gem5/gem5[develop]: dev: Warn when resp packet is error in dma port
Wei-Han Chen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/71778?usp=email )
Change subject: dev: Warn when resp packet is error in dma port
..
dev: Warn when resp packet is error in dma port
This CL adds a warning when the response packet is error.
Change-Id: I8e94dc2b85cd1753a4d6265cfda3cd5d6325f425
---
M src/dev/dma_device.cc
1 file changed, 1 insertion(+), 0 deletions(-)
diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index 24e931e..70a74ee 100644
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -68,6 +68,7 @@
{
// Should always see a response with a sender state.
assert(pkt->isResponse());
+warn_if(pkt->isError(), "Response pkt error.");
// Get the DMA sender state.
auto *state = dynamic_cast(pkt->senderState);
--
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Gerrit-Change-Id: I8e94dc2b85cd1753a4d6265cfda3cd5d6325f425
Gerrit-Change-Number: 71778
Gerrit-PatchSet: 1
Gerrit-Owner: Wei-Han Chen
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[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: Remove sendFunc
Wei-Han Chen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70157?usp=email )
Change subject: fastmodel: Remove sendFunc
..
fastmodel: Remove sendFunc
The original functionality is to access memory inside CPU. However, in
this CL: https://gem5-review.googlesource.com/c/public/gem5/+/45581,
the access method has been changed to use Iris API.
Thus, this CL removes this function.
Change-Id: Ide5e7c7c10a30b3c3ed00b97ba5894679d615e6b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70157
Tested-by: kokoro
Reviewed-by: Yu-hsin Wang
Maintainer: Gabe Black
---
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/iris/cpu.hh
5 files changed, 0 insertions(+), 25 deletions(-)
Approvals:
kokoro: Regressions pass
Yu-hsin Wang: Looks good to me, approved
Gabe Black: Looks good to me, approved
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc
b/src/arch/arm/fastmodel/CortexA76/evs.cc
index b299ad1..6d21a37 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -134,16 +134,6 @@
template
void
-ScxEvsCortexA76::sendFunc(PacketPtr pkt)
-{
-auto *trans = sc_gem5::packet2payload(pkt);
-panic_if(Base::amba->transport_dbg(*trans) != trans->get_data_length(),
-"Didn't send entire functional packet!");
-trans->release();
-}
-
-template
-void
ScxEvsCortexA76::before_end_of_elaboration()
{
Base::before_end_of_elaboration();
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh
b/src/arch/arm/fastmodel/CortexA76/evs.hh
index 9f08071..cdaa266 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -119,8 +119,6 @@
}
void start_of_simulation() override {}
-void sendFunc(PacketPtr pkt) override;
-
void setClkPeriod(Tick clk_period) override;
void setSysCounterFrq(uint64_t sys_counter_frq) override;
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc
b/src/arch/arm/fastmodel/CortexR52/evs.cc
index 47fbc36..ee5b4cc 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -129,16 +129,6 @@
}
template
-void
-ScxEvsCortexR52::sendFunc(PacketPtr pkt)
-{
-auto *trans = sc_gem5::packet2payload(pkt);
-panic_if(Base::amba[0]->transport_dbg(*trans) !=
trans->get_data_length(),
-"Didn't send entire functional packet!");
-trans->release();
-}
-
-template
Port &
ScxEvsCortexR52::gem5_getPort(const std::string _name, int idx)
{
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh
b/src/arch/arm/fastmodel/CortexR52/evs.hh
index 6516f4c..79bc22f 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -158,8 +158,6 @@
}
void start_of_simulation() override {}
-void sendFunc(PacketPtr pkt) override;
-
void setClkPeriod(Tick clk_period) override;
void setSysCounterFrq(uint64_t sys_counter_frq) override;
diff --git a/src/arch/arm/fastmodel/iris/cpu.hh
b/src/arch/arm/fastmodel/iris/cpu.hh
index b43eb8e..dd3992c 100644
--- a/src/arch/arm/fastmodel/iris/cpu.hh
+++ b/src/arch/arm/fastmodel/iris/cpu.hh
@@ -47,7 +47,6 @@
class BaseCpuEvs
{
public:
-virtual void sendFunc(PacketPtr pkt) = 0;
virtual void setClkPeriod(Tick clk_period) = 0;
virtual void setSysCounterFrq(uint64_t sys_counter_frq) = 0;
virtual void setCluster(SimObject *cluster) = 0;
--
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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ide5e7c7c10a30b3c3ed00b97ba5894679d615e6b
Gerrit-Change-Number: 70157
Gerrit-PatchSet: 2
Gerrit-Owner: Wei-Han Chen
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Wei-Han Chen
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
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[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: Remove sendFunc
Wei-Han Chen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/70157?usp=email )
Change subject: fastmodel: Remove sendFunc
..
fastmodel: Remove sendFunc
The original functionality is to access memory inside CPU. However, in
this CL: https://gem5-review.googlesource.com/c/public/gem5/+/45581,
the access method has been changed to use Iris API.
Thus, this CL removes this function.
Change-Id: Ide5e7c7c10a30b3c3ed00b97ba5894679d615e6b
---
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/iris/cpu.hh
5 files changed, 0 insertions(+), 25 deletions(-)
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc
b/src/arch/arm/fastmodel/CortexA76/evs.cc
index b299ad1..6d21a37 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -134,16 +134,6 @@
template
void
-ScxEvsCortexA76::sendFunc(PacketPtr pkt)
-{
-auto *trans = sc_gem5::packet2payload(pkt);
-panic_if(Base::amba->transport_dbg(*trans) != trans->get_data_length(),
-"Didn't send entire functional packet!");
-trans->release();
-}
-
-template
-void
ScxEvsCortexA76::before_end_of_elaboration()
{
Base::before_end_of_elaboration();
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh
b/src/arch/arm/fastmodel/CortexA76/evs.hh
index 9f08071..cdaa266 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -119,8 +119,6 @@
}
void start_of_simulation() override {}
-void sendFunc(PacketPtr pkt) override;
-
void setClkPeriod(Tick clk_period) override;
void setSysCounterFrq(uint64_t sys_counter_frq) override;
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc
b/src/arch/arm/fastmodel/CortexR52/evs.cc
index 47fbc36..ee5b4cc 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -129,16 +129,6 @@
}
template
-void
-ScxEvsCortexR52::sendFunc(PacketPtr pkt)
-{
-auto *trans = sc_gem5::packet2payload(pkt);
-panic_if(Base::amba[0]->transport_dbg(*trans) !=
trans->get_data_length(),
-"Didn't send entire functional packet!");
-trans->release();
-}
-
-template
Port &
ScxEvsCortexR52::gem5_getPort(const std::string _name, int idx)
{
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh
b/src/arch/arm/fastmodel/CortexR52/evs.hh
index 6516f4c..79bc22f 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -158,8 +158,6 @@
}
void start_of_simulation() override {}
-void sendFunc(PacketPtr pkt) override;
-
void setClkPeriod(Tick clk_period) override;
void setSysCounterFrq(uint64_t sys_counter_frq) override;
diff --git a/src/arch/arm/fastmodel/iris/cpu.hh
b/src/arch/arm/fastmodel/iris/cpu.hh
index b43eb8e..dd3992c 100644
--- a/src/arch/arm/fastmodel/iris/cpu.hh
+++ b/src/arch/arm/fastmodel/iris/cpu.hh
@@ -47,7 +47,6 @@
class BaseCpuEvs
{
public:
-virtual void sendFunc(PacketPtr pkt) = 0;
virtual void setClkPeriod(Tick clk_period) = 0;
virtual void setSysCounterFrq(uint64_t sys_counter_frq) = 0;
virtual void setCluster(SimObject *cluster) = 0;
--
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[gem5-dev] [XS] Change in gem5/gem5[develop]: base: Add missing headers in extensible.hh
Wei-Han Chen has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/69480?usp=email ) Change subject: base: Add missing headers in extensible.hh .. base: Add missing headers in extensible.hh Add missing headers and in extensible.hh Change-Id: I01e49c62619383ea4f7da668ceaefe4a41418cd8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69480 Tested-by: kokoro Reviewed-by: Daniel Carvalho Maintainer: Daniel Carvalho --- M src/base/extensible.hh 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: kokoro: Regressions pass Daniel Carvalho: Looks good to me, approved; Looks good to me, approved diff --git a/src/base/extensible.hh b/src/base/extensible.hh index e80103c..5acf49f 100644 --- a/src/base/extensible.hh +++ b/src/base/extensible.hh @@ -36,8 +36,10 @@ #ifndef __BASE_EXTENSIBLE_HH__ #define __BASE_EXTENSIBLE_HH__ +#include #include #include +#include #include namespace gem5 -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/69480?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I01e49c62619383ea4f7da668ceaefe4a41418cd8 Gerrit-Change-Number: 69480 Gerrit-PatchSet: 3 Gerrit-Owner: Wei-Han Chen Gerrit-Reviewer: Bobby Bruce Gerrit-Reviewer: Daniel Carvalho Gerrit-Reviewer: Wei-Han Chen Gerrit-Reviewer: Yan Lee Gerrit-Reviewer: Yu-hsin Wang Gerrit-Reviewer: kokoro Gerrit-MessageType: merged ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: Create amba_pv extension if not exist
Wei-Han Chen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/69481?usp=email )
Change subject: fastmodel: Create amba_pv extension if not exist
..
fastmodel: Create amba_pv extension if not exist
This CL create amba_pv extension is it doesn't exist in tlm to amba
bridge. Also, when creating a new amba_pv extension, it tries to set
that correctly.
Change-Id: I5cbb537192e95a615ff7e606657f73426f2c79a8
---
M src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
b/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
index d21b5f8..34a63bb 100644
--- a/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
+++ b/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
@@ -108,8 +108,29 @@
amba_pv::amba_pv_extension *amba_ex = nullptr;
trans.get_extension(amba_ex);
+
if (!amba_ex) {
-return;
+amba_ex = new amba_pv::amba_pv_extension();
+
+// Codes are copied from amba_pv_from_tlm_bridge header.
+// It tries to initiate a new amba_pv extension correctly.
+unsigned int l = trans.get_data_length();
+unsigned int w = amba_pv_m.get_bus_width_bytes();
+if (l > w) {
+amba_ex->set_size(w);
+amba_ex->set_length(l / w);
+if (trans.get_streaming_width() < l) {
+amba_ex->set_burst(amba_pv::AMBA_PV_FIXED);
+}
+} else {
+amba_ex->set_size(l);
+}
+
+if (trans.has_mm()) {
+trans.set_auto_extension(amba_ex);
+} else {
+trans.set_extension(amba_ex);
+}
}
amba_ex->set_privileged(control_ex->isPrivileged());
--
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[gem5-dev] [XS] Change in gem5/gem5[develop]: base: Add missing header in extensible.hh
Wei-Han Chen has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/69480?usp=email ) Change subject: base: Add missing header in extensible.hh .. base: Add missing header in extensible.hh Add a missing header in extensible.hh Change-Id: I01e49c62619383ea4f7da668ceaefe4a41418cd8 --- M src/base/extensible.hh 1 file changed, 1 insertion(+), 0 deletions(-) diff --git a/src/base/extensible.hh b/src/base/extensible.hh index e80103c..c3bfa49 100644 --- a/src/base/extensible.hh +++ b/src/base/extensible.hh @@ -36,6 +36,7 @@ #ifndef __BASE_EXTENSIBLE_HH__ #define __BASE_EXTENSIBLE_HH__ +#include #include #include #include -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/69480?usp=email To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: develop Gerrit-Change-Id: I01e49c62619383ea4f7da668ceaefe4a41418cd8 Gerrit-Change-Number: 69480 Gerrit-PatchSet: 1 Gerrit-Owner: Wei-Han Chen Gerrit-MessageType: newchange ___ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
[gem5-dev] [S] Change in gem5/gem5[develop]: systemc: Add helper function to set AXI4 attributes from flag
Wei-Han Chen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/69478?usp=email )
Change subject: systemc: Add helper function to set AXI4 attributes from
flag
..
systemc: Add helper function to set AXI4 attributes from flag
This CL adds helper function to setup AXI4 cache attributes in
ControlExtension from AXI4 cache attribute flag.
Change-Id: Id4e8f234fe2ca88282b24fda9fcbe2f5fdcc4a3d
---
M src/systemc/tlm_bridge/sc_ext.cc
M src/systemc/tlm_bridge/sc_ext.hh
2 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/src/systemc/tlm_bridge/sc_ext.cc
b/src/systemc/tlm_bridge/sc_ext.cc
index 10daa9a..2b78508 100644
--- a/src/systemc/tlm_bridge/sc_ext.cc
+++ b/src/systemc/tlm_bridge/sc_ext.cc
@@ -387,4 +387,13 @@
write_allocate = std::move(wa);
}
+void
+ControlExtension::setAXI4CacheAttributesFromFlag(uint32_t axi4_flag)
+{
+setBufferable((axi4_flag >> 0) & 1);
+setModifiable((axi4_flag >> 1) & 1);
+setReadAllocate((axi4_flag >> 2) & 1);
+setWriteAllocate((axi4_flag >> 3) & 1);
+}
+
} // namespace Gem5SystemC
diff --git a/src/systemc/tlm_bridge/sc_ext.hh
b/src/systemc/tlm_bridge/sc_ext.hh
index 96e679c..bc33e48 100644
--- a/src/systemc/tlm_bridge/sc_ext.hh
+++ b/src/systemc/tlm_bridge/sc_ext.hh
@@ -138,6 +138,8 @@
std::optional getWriteAllocate() const;
void setWriteAllocate(std::optional wa);
+void setAXI4CacheAttributesFromFlag(uint32_t axi4_flag);
+
private:
/* Secure and privileged access */
bool privileged;
--
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[gem5-dev] [M] Change in gem5/gem5[develop]: systemc: Add AXI4 cache attributes entry in control extension
Wei-Han Chen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/69477?usp=email )
Change subject: systemc: Add AXI4 cache attributes entry in control
extension
..
systemc: Add AXI4 cache attributes entry in control extension
This CL adds the entry of AXI4 cache attributes in gem5
ControlExtension. It gives us an opportunity to bring this information /
take out this information from AXI4 world.
Change-Id: Icf451566da46c40e42677459c66fbf446bec6185
---
M src/systemc/tlm_bridge/sc_ext.cc
M src/systemc/tlm_bridge/sc_ext.hh
2 files changed, 92 insertions(+), 0 deletions(-)
diff --git a/src/systemc/tlm_bridge/sc_ext.cc
b/src/systemc/tlm_bridge/sc_ext.cc
index 6e3cf11..10daa9a 100644
--- a/src/systemc/tlm_bridge/sc_ext.cc
+++ b/src/systemc/tlm_bridge/sc_ext.cc
@@ -315,4 +315,76 @@
substream_id = std::move(s);
}
+bool
+ControlExtension::hasBufferable() const
+{
+return bufferable.has_value();
+}
+
+std::optional
+ControlExtension::getBufferable() const
+{
+return bufferable;
+}
+
+void
+ControlExtension::setBufferable(std::optional b)
+{
+bufferable = std::move(b);
+}
+
+bool
+ControlExtension::hasModifiable() const
+{
+return modifiable.has_value();
+}
+
+std::optional
+ControlExtension::getModifiable() const
+{
+return modifiable;
+}
+
+void
+ControlExtension::setModifiable(std::optional m)
+{
+modifiable = std::move(m);
+}
+
+bool
+ControlExtension::hasReadAllocate() const
+{
+return read_allocate.has_value();
+}
+
+std::optional
+ControlExtension::getReadAllocate() const
+{
+return read_allocate;
+}
+
+void
+ControlExtension::setReadAllocate(std::optional ra)
+{
+read_allocate = std::move(ra);
+}
+
+bool
+ControlExtension::hasWriteAllocate() const
+{
+return write_allocate.has_value();
+}
+
+std::optional
+ControlExtension::getWriteAllocate() const
+{
+return write_allocate;
+}
+
+void
+ControlExtension::setWriteAllocate(std::optional wa)
+{
+write_allocate = std::move(wa);
+}
+
} // namespace Gem5SystemC
diff --git a/src/systemc/tlm_bridge/sc_ext.hh
b/src/systemc/tlm_bridge/sc_ext.hh
index f23f3fa..96e679c 100644
--- a/src/systemc/tlm_bridge/sc_ext.hh
+++ b/src/systemc/tlm_bridge/sc_ext.hh
@@ -124,6 +124,20 @@
std::optional getSubstreamId() const;
void setSubstreamId(std::optional s);
+/* AXI4 Cache Attributes */
+bool hasBufferable() const;
+std::optional getBufferable() const;
+void setBufferable(std::optional b);
+bool hasModifiable() const;
+std::optional getModifiable() const;
+void setModifiable(std::optional m);
+bool hasReadAllocate() const;
+std::optional getReadAllocate() const;
+void setReadAllocate(std::optional ra);
+bool hasWriteAllocate() const;
+std::optional getWriteAllocate() const;
+void setWriteAllocate(std::optional wa);
+
private:
/* Secure and privileged access */
bool privileged;
@@ -136,6 +150,12 @@
/* Stream ID and Substream ID */
std::optional stream_id;
std::optional substream_id;
+
+/* AXI4 Cache Attributes */
+std::optional bufferable;
+std::optional modifiable;
+std::optional read_allocate;
+std::optional write_allocate;
};
} // namespace Gem5SystemC
--
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Gerrit-Change-Number: 69477
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[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: Forward AXI4 cache attribute to tlm
Wei-Han Chen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/69479?usp=email )
Change subject: fastmodel: Forward AXI4 cache attribute to tlm
..
fastmodel: Forward AXI4 cache attribute to tlm
We have AXI4 cache attribute in ControlExtension now. Forward this
information from amba world to tlm and vice versa.
Change-Id: Ib5c001480dd680b14cc44f264cd55e142a2aa3d8
---
M src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
M src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
2 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
b/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
index 8db0d6a..d21b5f8 100644
--- a/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
+++ b/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
@@ -115,6 +115,19 @@
amba_ex->set_privileged(control_ex->isPrivileged());
amba_ex->set_non_secure(!control_ex->isSecure());
amba_ex->set_instruction(control_ex->isInstruction());
+
+if (control_ex->hasBufferable()) {
+amba_ex->set_bufferable(control_ex->getBufferable().value());
+}
+if (control_ex->hasModifiable()) {
+amba_ex->set_modifiable(control_ex->getModifiable().value());
+}
+if (control_ex->hasReadAllocate()) {
+amba_ex->set_read_allocate(control_ex->getReadAllocate().value());
+}
+if (control_ex->hasWriteAllocate()) {
+
amba_ex->set_write_allocate(control_ex->getWriteAllocate().value());
+}
}
} // namespace fastmodel
diff --git a/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
b/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
index 2f065fc..acebe50 100644
--- a/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
+++ b/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
@@ -196,6 +196,11 @@
control_ex->setStreamId(amba_ex->get_id());
}
+control_ex->setBufferable(amba_ex->is_bufferable());
+control_ex->setModifiable(amba_ex->is_modifiable());
+control_ex->setReadAllocate(amba_ex->is_read_allocate());
+control_ex->setWriteAllocate(amba_ex->is_write_allocate());
+
if (trans.has_mm()) {
trans.set_auto_extension(control_ex);
} else {
--
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[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: forward stream ID to gem5
Wei-Han Chen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67591?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: fastmodel: forward stream ID to gem5
..
fastmodel: forward stream ID to gem5
This CL enables forwarding stream ID from amba_pv to gem5 world.
The stream ID information is originally stored in master_id of
pv::TransactionAtrribute, then it will be stored to m_id of
amba_pv::amba_pv_extension.
This CL brings the information to stream ID field of
Gem5SystemC::ControlExtension. Then the information can be set to stream
ID of the gem5 packet's request.
After bringing the information to gem5, we can identify the packet's
stream ID from gem5 side. One example usage is PL330. In PL330_DMAC, each
transaction is associated with a stream ID. If we can identitfy the
stream ID, we can, for example, set attribute to specific DMAC channel.
Change-Id: I943ce49fde57b0bcfc18b58c7566eec61cc676f4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67591
Reviewed-by: Yu-hsin Wang
Tested-by: kokoro
Maintainer: Gabe Black
---
M src/arch/arm/fastmodel/FastModel.py
M src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
M src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
3 files changed, 39 insertions(+), 1 deletion(-)
Approvals:
Gabe Black: Looks good to me, approved
Yu-hsin Wang: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/FastModel.py
b/src/arch/arm/fastmodel/FastModel.py
index 8a28522..1ea3c5e 100644
--- a/src/arch/arm/fastmodel/FastModel.py
+++ b/src/arch/arm/fastmodel/FastModel.py
@@ -108,6 +108,10 @@
amba = AmbaTargetSocket(64, "AMBA PV target socket")
tlm = TlmInitiatorSocket(64, "TLM initiator socket")
+set_stream_id = Param.Bool(
+False, "Set this true to forward stream ID to gem5 world"
+)
+
class AmbaFromTlmBridge64(SystemC_ScModule):
type = "AmbaFromTlmBridge64"
diff --git a/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
b/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
index 888e077..2f065fc 100644
--- a/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
+++ b/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
@@ -77,7 +77,8 @@
targetProxy("target_proxy"),
initiatorProxy("initiator_proxy"),
tlmWrapper(initiatorProxy, std::string(name) + ".tlm", -1),
-ambaWrapper(amba_pv_s, std::string(name) + ".amba", -1)
+ambaWrapper(amba_pv_s, std::string(name) + ".amba", -1),
+setStreamId(params.set_stream_id)
{
targetProxy.register_b_transport(this, ::bTransport);
targetProxy.register_get_direct_mem_ptr(
@@ -191,6 +192,10 @@
control_ex->setSecure(!amba_ex->is_non_secure());
control_ex->setInstruction(amba_ex->is_instruction());
+if (setStreamId) {
+control_ex->setStreamId(amba_ex->get_id());
+}
+
if (trans.has_mm()) {
trans.set_auto_extension(control_ex);
} else {
diff --git a/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
b/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
index 176d31f..6729604 100644
--- a/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
+++ b/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
@@ -71,6 +71,7 @@
AmbaToTlmBridge64, 64, tlm::tlm_base_protocol_types>
initiatorProxy;
sc_gem5::TlmInitiatorWrapper<64> tlmWrapper;
AmbaTarget ambaWrapper;
+bool setStreamId;
};
} // namespace fastmodel
--
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Gerrit-Change-Id: I943ce49fde57b0bcfc18b58c7566eec61cc676f4
Gerrit-Change-Number: 67591
Gerrit-PatchSet: 3
Gerrit-Owner: Wei-Han Chen
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Wei-Han Chen
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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[gem5-dev] [M] Change in gem5/gem5[develop]: fastmodel: change the constructor of bridges
Wei-Han Chen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/67297?usp=email )
(
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: fastmodel: change the constructor of bridges
..
fastmodel: change the constructor of bridges
This CL changes the construction of bridges between amba and tlm. This
enables us to add parameters when using this bridge.
Change-Id: I4bbbe8fb1c2573a796a3a0a7976adf3553bbaa86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67297
Maintainer: Gabe Black
Tested-by: kokoro
Reviewed-by: Yu-hsin Wang
---
M src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
M src/arch/arm/fastmodel/amba_from_tlm_bridge.hh
M src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
M src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
4 files changed, 33 insertions(+), 18 deletions(-)
Approvals:
kokoro: Regressions pass
Yu-hsin Wang: Looks good to me, approved
Gabe Black: Looks good to me, approved
diff --git a/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
b/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
index 4baf0ef..8db0d6a 100644
--- a/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
+++ b/src/arch/arm/fastmodel/amba_from_tlm_bridge.cc
@@ -37,7 +37,9 @@
namespace fastmodel
{
-AmbaFromTlmBridge64::AmbaFromTlmBridge64(const sc_core::sc_module_name&
name) :
+AmbaFromTlmBridge64::AmbaFromTlmBridge64(
+const AmbaFromTlmBridge64Params ,
+const sc_core::sc_module_name& name) :
amba_pv::amba_pv_from_tlm_bridge<64>(name),
targetProxy("target_proxy"),
initiatorProxy("initiator_proxy"),
@@ -116,11 +118,4 @@
}
} // namespace fastmodel
-
-fastmodel::AmbaFromTlmBridge64 *
-AmbaFromTlmBridge64Params::create() const
-{
-return new fastmodel::AmbaFromTlmBridge64(name.c_str());
-}
-
} // namespace gem5
diff --git a/src/arch/arm/fastmodel/amba_from_tlm_bridge.hh
b/src/arch/arm/fastmodel/amba_from_tlm_bridge.hh
index 8ea8b8a..11f7b5d 100644
--- a/src/arch/arm/fastmodel/amba_from_tlm_bridge.hh
+++ b/src/arch/arm/fastmodel/amba_from_tlm_bridge.hh
@@ -33,6 +33,7 @@
#include "amba_pv.h"
#pragma GCC diagnostic pop
#include "arch/arm/fastmodel/amba_ports.hh"
+#include "params/AmbaFromTlmBridge64.hh"
#include "systemc/tlm_port_wrapper.hh"
namespace gem5
@@ -46,7 +47,11 @@
class AmbaFromTlmBridge64 : public amba_pv::amba_pv_from_tlm_bridge<64>
{
public:
-AmbaFromTlmBridge64(const sc_core::sc_module_name );
+AmbaFromTlmBridge64(const AmbaFromTlmBridge64Params ,
+const sc_core::sc_module_name );
+AmbaFromTlmBridge64(const AmbaFromTlmBridge64Params ) :
+ AmbaFromTlmBridge64(params, params.name.c_str())
+{}
gem5::Port _getPort(const std::string _name, int idx=-1)
override;
diff --git a/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
b/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
index 58f6eea..888e077 100644
--- a/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
+++ b/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
@@ -71,7 +71,8 @@
namespace fastmodel
{
-AmbaToTlmBridge64::AmbaToTlmBridge64(const sc_core::sc_module_name& name) :
+AmbaToTlmBridge64::AmbaToTlmBridge64(const AmbaToTlmBridge64Params ,
+ const sc_core::sc_module_name& name) :
amba_pv::amba_pv_to_tlm_bridge<64>(name),
targetProxy("target_proxy"),
initiatorProxy("initiator_proxy"),
@@ -198,11 +199,4 @@
}
} // namespace fastmodel
-
-fastmodel::AmbaToTlmBridge64 *
-AmbaToTlmBridge64Params::create() const
-{
-return new fastmodel::AmbaToTlmBridge64(name.c_str());
-}
-
} // namespace gem5
diff --git a/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
b/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
index addaac6..176d31f 100644
--- a/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
+++ b/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
@@ -33,6 +33,7 @@
#include "amba_pv.h"
#pragma GCC diagnostic pop
#include "arch/arm/fastmodel/amba_ports.hh"
+#include "params/AmbaToTlmBridge64.hh"
#include "systemc/tlm_port_wrapper.hh"
namespace gem5
@@ -46,7 +47,11 @@
class AmbaToTlmBridge64 : public amba_pv::amba_pv_to_tlm_bridge<64>
{
public:
-AmbaToTlmBridge64(const sc_core::sc_module_name );
+AmbaToTlmBridge64(const AmbaToTlmBridge64Params ,
+ const sc_core::sc_module_name );
+AmbaToTlmBridge64(const AmbaToTlmBridge64Params ) :
+ AmbaToTlmBridge64(params, params.name.c_str())
+{}
gem5::Port _getPort(const std::string _name, int idx=-1)
override;
--
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Gerrit-Change-Number: 67297
[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: forward stream ID to gem5
Wei-Han Chen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67591?usp=email )
Change subject: fastmodel: forward stream ID to gem5
..
fastmodel: forward stream ID to gem5
This CL enables forwarding stream ID from amba_pv to gem5 world.
The stream ID information is originally stored in master_id of
pv::TransactionAtrribute, then it will be stored to m_id of
amba_pv::amba_pv_extension.
This CL brings the information to stream ID field of
Gem5SystemC::ControlExtension. Then the information can be set to stream
ID of the gem5 packet's request.
After bringing the information to gem5, we can identify the packet's
stream ID from gem5 side. One example usage is PL330. In PL330_DMAC, each
transaction is associated with a stream ID. If we can identitfy the
stream ID, we can, for example, set attribute to specific DMAC channel.
Change-Id: I943ce49fde57b0bcfc18b58c7566eec61cc676f4
---
M src/arch/arm/fastmodel/FastModel.py
M src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
M src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
3 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/fastmodel/FastModel.py
b/src/arch/arm/fastmodel/FastModel.py
index 8a28522..1ea3c5e 100644
--- a/src/arch/arm/fastmodel/FastModel.py
+++ b/src/arch/arm/fastmodel/FastModel.py
@@ -108,6 +108,10 @@
amba = AmbaTargetSocket(64, "AMBA PV target socket")
tlm = TlmInitiatorSocket(64, "TLM initiator socket")
+set_stream_id = Param.Bool(
+False, "Set this true to forward stream ID to gem5 world"
+)
+
class AmbaFromTlmBridge64(SystemC_ScModule):
type = "AmbaFromTlmBridge64"
diff --git a/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
b/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
index 888e077..2f065fc 100644
--- a/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
+++ b/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
@@ -77,7 +77,8 @@
targetProxy("target_proxy"),
initiatorProxy("initiator_proxy"),
tlmWrapper(initiatorProxy, std::string(name) + ".tlm", -1),
-ambaWrapper(amba_pv_s, std::string(name) + ".amba", -1)
+ambaWrapper(amba_pv_s, std::string(name) + ".amba", -1),
+setStreamId(params.set_stream_id)
{
targetProxy.register_b_transport(this, ::bTransport);
targetProxy.register_get_direct_mem_ptr(
@@ -191,6 +192,10 @@
control_ex->setSecure(!amba_ex->is_non_secure());
control_ex->setInstruction(amba_ex->is_instruction());
+if (setStreamId) {
+control_ex->setStreamId(amba_ex->get_id());
+}
+
if (trans.has_mm()) {
trans.set_auto_extension(control_ex);
} else {
diff --git a/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
b/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
index 176d31f..6729604 100644
--- a/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
+++ b/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
@@ -71,6 +71,7 @@
AmbaToTlmBridge64, 64, tlm::tlm_base_protocol_types>
initiatorProxy;
sc_gem5::TlmInitiatorWrapper<64> tlmWrapper;
AmbaTarget ambaWrapper;
+bool setStreamId;
};
} // namespace fastmodel
--
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[gem5-dev] [M] Change in gem5/gem5[develop]: fastmodel: forward stream ID to gem5
Wei-Han Chen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67297?usp=email )
Change subject: fastmodel: forward stream ID to gem5
..
fastmodel: forward stream ID to gem5
This CL enables forwarding stream ID from amba_pv to gem5 world.
The stream ID information is originally stored in master_id of
pv::TransactionAtrribute, then it will be stored to m_id of
amba_pv::amba_pv_extension.
This CL brings the information to stream ID field of
Gem5SystemC::ControlExtension. Then the information can be set to stream
ID of the gem5 packet's request.
After bringing the information to gem5, we can identify the packet's
stream ID from gem5 side. One example usage is PL330. In PL330_DMAC, each
transaction is associated with a stream ID. If we can identitfy the
stream ID, we can, for example, set attribute to specific DMAC channel.
Change-Id: I4bbbe8fb1c2573a796a3a0a7976adf3553bbaa86
---
M src/arch/arm/fastmodel/FastModel.py
M src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
M src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
3 files changed, 43 insertions(+), 10 deletions(-)
diff --git a/src/arch/arm/fastmodel/FastModel.py
b/src/arch/arm/fastmodel/FastModel.py
index 8a28522..1ea3c5e 100644
--- a/src/arch/arm/fastmodel/FastModel.py
+++ b/src/arch/arm/fastmodel/FastModel.py
@@ -108,6 +108,10 @@
amba = AmbaTargetSocket(64, "AMBA PV target socket")
tlm = TlmInitiatorSocket(64, "TLM initiator socket")
+set_stream_id = Param.Bool(
+False, "Set this true to forward stream ID to gem5 world"
+)
+
class AmbaFromTlmBridge64(SystemC_ScModule):
type = "AmbaFromTlmBridge64"
diff --git a/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
b/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
index 58f6eea..2f065fc 100644
--- a/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
+++ b/src/arch/arm/fastmodel/amba_to_tlm_bridge.cc
@@ -71,12 +71,14 @@
namespace fastmodel
{
-AmbaToTlmBridge64::AmbaToTlmBridge64(const sc_core::sc_module_name& name) :
+AmbaToTlmBridge64::AmbaToTlmBridge64(const AmbaToTlmBridge64Params ,
+ const sc_core::sc_module_name& name) :
amba_pv::amba_pv_to_tlm_bridge<64>(name),
targetProxy("target_proxy"),
initiatorProxy("initiator_proxy"),
tlmWrapper(initiatorProxy, std::string(name) + ".tlm", -1),
-ambaWrapper(amba_pv_s, std::string(name) + ".amba", -1)
+ambaWrapper(amba_pv_s, std::string(name) + ".amba", -1),
+setStreamId(params.set_stream_id)
{
targetProxy.register_b_transport(this, ::bTransport);
targetProxy.register_get_direct_mem_ptr(
@@ -190,6 +192,10 @@
control_ex->setSecure(!amba_ex->is_non_secure());
control_ex->setInstruction(amba_ex->is_instruction());
+if (setStreamId) {
+control_ex->setStreamId(amba_ex->get_id());
+}
+
if (trans.has_mm()) {
trans.set_auto_extension(control_ex);
} else {
@@ -198,11 +204,4 @@
}
} // namespace fastmodel
-
-fastmodel::AmbaToTlmBridge64 *
-AmbaToTlmBridge64Params::create() const
-{
-return new fastmodel::AmbaToTlmBridge64(name.c_str());
-}
-
} // namespace gem5
diff --git a/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
b/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
index addaac6..6729604 100644
--- a/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
+++ b/src/arch/arm/fastmodel/amba_to_tlm_bridge.hh
@@ -33,6 +33,7 @@
#include "amba_pv.h"
#pragma GCC diagnostic pop
#include "arch/arm/fastmodel/amba_ports.hh"
+#include "params/AmbaToTlmBridge64.hh"
#include "systemc/tlm_port_wrapper.hh"
namespace gem5
@@ -46,7 +47,11 @@
class AmbaToTlmBridge64 : public amba_pv::amba_pv_to_tlm_bridge<64>
{
public:
-AmbaToTlmBridge64(const sc_core::sc_module_name );
+AmbaToTlmBridge64(const AmbaToTlmBridge64Params ,
+ const sc_core::sc_module_name );
+AmbaToTlmBridge64(const AmbaToTlmBridge64Params ) :
+ AmbaToTlmBridge64(params, params.name.c_str())
+{}
gem5::Port _getPort(const std::string _name, int idx=-1)
override;
@@ -66,6 +71,7 @@
AmbaToTlmBridge64, 64, tlm::tlm_base_protocol_types>
initiatorProxy;
sc_gem5::TlmInitiatorWrapper<64> tlmWrapper;
AmbaTarget ambaWrapper;
+bool setStreamId;
};
} // namespace fastmodel
--
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Gerrit-Project: public/gem5
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Gerrit-Change-Id: I4bbbe8fb1c2573a796a3a0a7976adf3553bbaa86
Gerrit-Change-Number: 67297
Gerrit-PatchSet: 1
Gerrit-Owner: Wei-Han Chen
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