[gem5-dev] Change in gem5/gem5[master]: arch-riscv: fix asmtest concurrent issues.
Xin Ouyang has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/22863 ) Change subject: arch-riscv: fix asmtest concurrent issues. .. arch-riscv: fix asmtest concurrent issues. riscv asmtest uses multiprocessing.Pool to run multiple gem5 processes concurrently. By using gem5 default options, processes will fail because: - accessing to the same m5out directory - listening too many remote gdb ports at the same time This will set independent m5out directories and disable remote gdb ports for asmtest gem5 processes. Change-Id: Ie4c81232210568cd1945adc2b99eebc019d705b6 Signed-off-by: Xin Ouyang Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22863 Reviewed-by: Jason Lowe-Power Reviewed-by: Alec Roelke Maintainer: Jason Lowe-Power Tested-by: kokoro --- M tests/test-progs/asmtest/src/riscv/run-tests.py 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved Alec Roelke: Looks good to me, approved kokoro: Regressions pass diff --git a/tests/test-progs/asmtest/src/riscv/run-tests.py b/tests/test-progs/asmtest/src/riscv/run-tests.py index 53a8476..f5b847f 100755 --- a/tests/test-progs/asmtest/src/riscv/run-tests.py +++ b/tests/test-progs/asmtest/src/riscv/run-tests.py @@ -109,6 +109,8 @@ test_name = test + '-' + model job_names.append(test_name) job_cmds.append([gem5_bin, + '-d', 'm5out/' + test_name, + '--listener-mode', 'off', config, '-m', str(args.max_tick), '--cpu-type', model, -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/22863 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ie4c81232210568cd1945adc2b99eebc019d705b6 Gerrit-Change-Number: 22863 Gerrit-PatchSet: 3 Gerrit-Owner: Xin Ouyang Gerrit-Reviewer: Alec Roelke Gerrit-Reviewer: Jason Lowe-Power Gerrit-Reviewer: Xin Ouyang Gerrit-Reviewer: kokoro Gerrit-CC: Bobby R. Bruce Gerrit-MessageType: merged ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-riscv: merge FFLAGS&FRM fields into fcsr register.
Xin Ouyang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/22864 )
Change subject: arch-riscv: merge FFLAGS&FRM fields into fcsr register.
..
arch-riscv: merge FFLAGS&FRM fields into fcsr register.
According to riscv isa spec, FFLAGS and FRM are not registers,
they are just fields of FCSR. The fields can be accessed
individually through CSR addresses "FFLAGS" and "FRM" in CSROp
instructions.
This will remove the FFLAGS&FRM registers, and merge into FCSR.
Change-Id: I46b0419ee52a3fe30ceb203a142201c239cdbf8e
Signed-off-by: Xin Ouyang
---
M src/arch/riscv/isa/formats/fp.isa
M src/arch/riscv/isa/formats/standard.isa
M src/arch/riscv/registers.hh
3 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/src/arch/riscv/isa/formats/fp.isa
b/src/arch/riscv/isa/formats/fp.isa
index 1047285..97e5d11 100644
--- a/src/arch/riscv/isa/formats/fp.isa
+++ b/src/arch/riscv/isa/formats/fp.isa
@@ -60,7 +60,8 @@
fault = make_shared(ROUND_MODE, machInst);
break;
case 0x7: {
-uint8_t frm = xc->readMiscReg(MISCREG_FRM);
+RegVal fcsr = xc->readMiscReg(MISCREG_FCSR);
+uint8_t frm = (fcsr >> FRM_OFFSET) & FRM_MASK;
switch (frm) {
case 0x0:
std::fesetround(FE_TONEAREST);
@@ -91,7 +92,8 @@
}
if (fault == NoFault) {
-RegVal FFLAGS = xc->readMiscReg(MISCREG_FFLAGS);
+RegVal fcsr = xc->readMiscReg(MISCREG_FCSR);
+uint8_t FFLAGS = fcsr & FFLAGS_MASK;
std::feclearexcept(FE_ALL_EXCEPT);
%(code)s;
if (std::fetestexcept(FE_INEXACT)) {
@@ -109,7 +111,9 @@
if (std::fetestexcept(FE_INVALID)) {
FFLAGS |= FloatInvalid;
}
-xc->setMiscReg(MISCREG_FFLAGS, FFLAGS);
+
+fcsr = (fcsr & ~FFLAGS_MASK) | FFLAGS;
+xc->setMiscReg(MISCREG_FCSR, fcsr);
}
if (fault == NoFault) {
diff --git a/src/arch/riscv/isa/formats/standard.isa
b/src/arch/riscv/isa/formats/standard.isa
index 15d2681..17d6567 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -223,8 +223,7 @@
RegVal data, olddata;
switch (csr) {
case CSR_FCSR:
-olddata = xc->readMiscReg(MISCREG_FFLAGS) |
- (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
+olddata = xc->readMiscReg(MISCREG_FCSR);
break;
default:
if (CSRData.find(csr) != CSRData.end()) {
@@ -260,8 +259,7 @@
INTERRUPT newinterrupt = data;
switch (csr) {
case CSR_FCSR:
-xc->setMiscReg(MISCREG_FFLAGS, bits(data, 4,
0));
-xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5));
+xc->setMiscReg(MISCREG_FCSR, data);
break;
case CSR_MIP: case CSR_MIE:
if (oldinterrupt.mei == newinterrupt.mei &&
diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 582a6c5..88da40e 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -258,6 +258,7 @@
MISCREG_UTVAL,
MISCREG_FFLAGS,
MISCREG_FRM,
+MISCREG_FCSR,
NUM_MISCREGS
};
@@ -446,7 +447,7 @@
{CSR_UIP, {"uip", MISCREG_IP}},
{CSR_FFLAGS, {"fflags", MISCREG_FFLAGS}},
{CSR_FRM, {"frm", MISCREG_FRM}},
-{CSR_FCSR, {"fcsr", MISCREG_FFLAGS}}, // Actually FRM << 5 | FFLAGS
+{CSR_FCSR, {"fcsr", MISCREG_FCSR}},
{CSR_CYCLE, {"cycle", MISCREG_CYCLE}},
{CSR_TIME, {"time", MISCREG_TIME}},
{CSR_INSTRET, {"instret", MISCREG_INSTRET}},
@@ -714,6 +715,7 @@
const RegVal UI_MASK = UEI_MASK | UTI_MASK | USI_MASK;
const RegVal FFLAGS_MASK = (1 << FRM_OFFSET) - 1;
const RegVal FRM_MASK = 0x7;
+const RegVal FCSR_MASK = FFLAGS_MASK | (FRM_MASK << FRM_OFFSET);
const std::map CSRMasks = {
{CSR_USTATUS, USTATUS_MASK},
@@ -721,7 +723,7 @@
{CSR_UIP, UI_MASK},
{CSR_FFLAGS, FFLAGS_MASK},
{CSR_FRM, FRM_MASK},
-{CSR_FCSR, FFLAGS_MASK | (FRM_MASK << FRM_OFFSET)},
+{CSR_FCSR, FCSR_MASK},
{CSR_SSTATUS, SSTATUS_MASK},
{CSR_SIE, SI_MASK},
{CSR_SIP, SI_MASK},
--
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[gem5-dev] Change in gem5/gem5[master]: arch-riscv: fix asmtest clusterjob concurrent issues.
Xin Ouyang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/22863 ) Change subject: arch-riscv: fix asmtest clusterjob concurrent issues. .. arch-riscv: fix asmtest clusterjob concurrent issues. riscv asmtest uses "clusterjob" module to run multiple gem5 processes concurrently. By using gem5 default options, processes will fail because: - accessing to the same m5out directory - listening too many remote gdb ports at the same time This will set independent m5out directories and disable remote gdb ports for asmtest gem5 processes. Change-Id: Ie4c81232210568cd1945adc2b99eebc019d705b6 Signed-off-by: Xin Ouyang --- M tests/test-progs/asmtest/src/riscv/run-tests.py 1 file changed, 2 insertions(+), 0 deletions(-) diff --git a/tests/test-progs/asmtest/src/riscv/run-tests.py b/tests/test-progs/asmtest/src/riscv/run-tests.py index 53a8476..f5b847f 100755 --- a/tests/test-progs/asmtest/src/riscv/run-tests.py +++ b/tests/test-progs/asmtest/src/riscv/run-tests.py @@ -109,6 +109,8 @@ test_name = test + '-' + model job_names.append(test_name) job_cmds.append([gem5_bin, + '-d', 'm5out/' + test_name, + '--listener-mode', 'off', config, '-m', str(args.max_tick), '--cpu-type', model, -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/22863 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ie4c81232210568cd1945adc2b99eebc019d705b6 Gerrit-Change-Number: 22863 Gerrit-PatchSet: 1 Gerrit-Owner: Xin Ouyang Gerrit-MessageType: newchange ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
