[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_IDST
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70723?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Implement FEAT_IDST
..
arch-arm: Implement FEAT_IDST
Change-Id: I3cabcfdb10f4eefaf2ab039376d840cc4c54609a
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70723
Tested-by: kokoro
Maintainer: Jason Lowe-Power
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/regs/misc.cc
2 files changed, 59 insertions(+), 17 deletions(-)
Approvals:
Richard Cooper: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index c3b3cf6..b826f0d 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -86,6 +86,7 @@
"FEAT_SEL2",
"FEAT_TLBIOS",
"FEAT_FLAGM",
+"FEAT_IDST",
# Armv8.5
"FEAT_FLAGM2",
"FEAT_RNG",
@@ -170,6 +171,7 @@
"FEAT_SEL2",
"FEAT_TLBIOS",
"FEAT_FLAGM",
+"FEAT_IDST",
# Armv8.5
"FEAT_FLAGM2",
# Armv9.2
@@ -202,7 +204,12 @@
class Armv84(Armv83):
-extensions = Armv83.extensions +
["FEAT_SEL2", "FEAT_TLBIOS", "FEAT_FLAGM"]
+extensions = Armv83.extensions + [
+"FEAT_SEL2",
+"FEAT_TLBIOS",
+"FEAT_FLAGM",
+"FEAT_IDST",
+]
class Armv85(Armv84):
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 56644e9..53e9268 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2077,6 +2077,22 @@
}
}
+Fault
+faultIdst(const MiscRegLUTEntry ,
+ThreadContext *tc, const MiscRegOp64 )
+{
+if (HaveExt(tc, ArmExtension::FEAT_IDST)) {
+const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
+if (EL2Enabled(tc) && hcr.tge) {
+return inst.generateTrap(EL2);
+} else {
+return inst.generateTrap(EL1);
+}
+} else {
+return inst.undefined();
+}
+}
+
}
MiscRegIndex
@@ -3828,6 +3844,7 @@
// AArch64 registers (Op0=1,3);
InitReg(MISCREG_MIDR_EL1)
.allPrivileges().exceptUserMode().writes(0)
+ .faultRead(EL0, faultIdst)
.mapsTo(MISCREG_MIDR);
InitReg(MISCREG_MPIDR_EL1)
.allPrivileges().exceptUserMode().writes(0)
@@ -3923,34 +3940,40 @@
return pfr0_el1;
}())
.unserialize(0)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
- .allPrivileges().exceptUserMode().writes(0);
+ .allPrivileges().writes(0);
InitReg(MISCREG_ID_AA64PFR1_EL1)
.reset(release->has(ArmExtension::FEAT_SME) ?
0x1 << 24 : 0)
.unserialize(0)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
- .allPrivileges().exceptUserMode().writes(0);
+ .allPrivileges().writes(0);
InitReg(MISCREG_ID_AA64DFR0_EL1)
.reset([p](){
AA64DFR0 dfr0_el1 = p.id_aa64dfr0_el1;
dfr0_el1.pmuver = p.pmu ? 1 : 0; // Enable PMUv3
return dfr0_el1;
}())
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
- .allPrivileges().exceptUserMode().writes(0);
+ .allPrivileges().writes(0);
InitReg(MISCREG_ID_AA64DFR1_EL1)
.reset(p.id_aa64dfr1_el1)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
- .allPrivileges().exceptUserMode().writes(0);
+ .allPrivileges().writes(0);
InitReg(MISCREG_ID_AA64AFR0_EL1)
.reset(p.id_aa64afr0_el1)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
- .allPrivileges().exceptUserMode().writes(0);
+ .allPrivileges().writes(0);
InitReg(MISCREG_ID_AA64AFR1_EL1)
.reset(p.id_aa64afr1_el1)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
- .allPrivileges().exceptUserMode().writes(0);
+ .allPrivileges().writes(0);
InitReg(MISCREG_ID_AA64ISAR0_EL1)
.reset([p,release=release](){
AA64ISAR0 isar0_el1 = p.id_aa64isar0_el1;
@@ -3975,8 +3998,9 @@
isar0_el1.rndr = release->has(ArmExtension::FEAT_RNG) ? 0x1 :
0x0;
return isar0_el1;
}())
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
- .allPrivileges().exceptUserMode().writes(0);
+ .allPrivileges().writes(0);
InitReg(MISCREG_ID_AA64ISAR1_EL1)
.reset([p,release=release](){
AA64ISAR1 isar1_el1 = p.id_aa64isar1_el1;
@@ -3986,8 +4010,9 @@
isar1_el1.gpa = release->has(ArmExtension::FEAT_PAuth) ? 0x1 :
0x0;
return isar1_el1;
}())
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
-
[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_IDST
Attention is currently required from: Richard Cooper.
Hello Richard Cooper,
I'd like you to do a code review.
Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/70723?usp=email
to review the following change.
Change subject: arch-arm: Implement FEAT_IDST
..
arch-arm: Implement FEAT_IDST
Change-Id: I3cabcfdb10f4eefaf2ab039376d840cc4c54609a
Signed-off-by: Giacomo Travaglini
Reviewed-by: Richard Cooper
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/regs/misc.cc
2 files changed, 59 insertions(+), 17 deletions(-)
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index c3b3cf6..b826f0d 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -86,6 +86,7 @@
"FEAT_SEL2",
"FEAT_TLBIOS",
"FEAT_FLAGM",
+"FEAT_IDST",
# Armv8.5
"FEAT_FLAGM2",
"FEAT_RNG",
@@ -170,6 +171,7 @@
"FEAT_SEL2",
"FEAT_TLBIOS",
"FEAT_FLAGM",
+"FEAT_IDST",
# Armv8.5
"FEAT_FLAGM2",
# Armv9.2
@@ -202,7 +204,12 @@
class Armv84(Armv83):
-extensions = Armv83.extensions +
["FEAT_SEL2", "FEAT_TLBIOS", "FEAT_FLAGM"]
+extensions = Armv83.extensions + [
+"FEAT_SEL2",
+"FEAT_TLBIOS",
+"FEAT_FLAGM",
+"FEAT_IDST",
+]
class Armv85(Armv84):
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 10b7d38..a151177 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2077,6 +2077,22 @@
}
}
+Fault
+faultIdst(const MiscRegLUTEntry ,
+ThreadContext *tc, const MiscRegOp64 )
+{
+if (HaveExt(tc, ArmExtension::FEAT_IDST)) {
+const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
+if (EL2Enabled(tc) && hcr.tge) {
+return inst.generateTrap(EL2);
+} else {
+return inst.generateTrap(EL1);
+}
+} else {
+return inst.undefined();
+}
+}
+
}
MiscRegIndex
@@ -3828,6 +3844,7 @@
// AArch64 registers (Op0=1,3);
InitReg(MISCREG_MIDR_EL1)
.allPrivileges().exceptUserMode().writes(0)
+ .faultRead(EL0, faultIdst)
.mapsTo(MISCREG_MIDR);
InitReg(MISCREG_MPIDR_EL1)
.allPrivileges().exceptUserMode().writes(0)
@@ -3923,34 +3940,40 @@
return pfr0_el1;
}())
.unserialize(0)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
- .allPrivileges().exceptUserMode().writes(0);
+ .allPrivileges().writes(0);
InitReg(MISCREG_ID_AA64PFR1_EL1)
.reset(release->has(ArmExtension::FEAT_SME) ?
0x1 << 24 : 0)
.unserialize(0)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
- .allPrivileges().exceptUserMode().writes(0);
+ .allPrivileges().writes(0);
InitReg(MISCREG_ID_AA64DFR0_EL1)
.reset([p](){
AA64DFR0 dfr0_el1 = p.id_aa64dfr0_el1;
dfr0_el1.pmuver = p.pmu ? 1 : 0; // Enable PMUv3
return dfr0_el1;
}())
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
- .allPrivileges().exceptUserMode().writes(0);
+ .allPrivileges().writes(0);
InitReg(MISCREG_ID_AA64DFR1_EL1)
.reset(p.id_aa64dfr1_el1)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
- .allPrivileges().exceptUserMode().writes(0);
+ .allPrivileges().writes(0);
InitReg(MISCREG_ID_AA64AFR0_EL1)
.reset(p.id_aa64afr0_el1)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
- .allPrivileges().exceptUserMode().writes(0);
+ .allPrivileges().writes(0);
InitReg(MISCREG_ID_AA64AFR1_EL1)
.reset(p.id_aa64afr1_el1)
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
- .allPrivileges().exceptUserMode().writes(0);
+ .allPrivileges().writes(0);
InitReg(MISCREG_ID_AA64ISAR0_EL1)
.reset([p,release=release](){
AA64ISAR0 isar0_el1 = p.id_aa64isar0_el1;
@@ -3974,8 +3997,9 @@
0x1 : 0x0;
return isar0_el1;
}())
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
- .allPrivileges().exceptUserMode().writes(0);
+ .allPrivileges().writes(0);
InitReg(MISCREG_ID_AA64ISAR1_EL1)
.reset([p,release=release](){
AA64ISAR1 isar1_el1 = p.id_aa64isar1_el1;
@@ -3985,8 +4009,9 @@
isar1_el1.gpa = release->has(ArmExtension::FEAT_PAuth) ? 0x1 :
0x0;
return isar1_el1;
}())
+ .faultRead(EL0, faultIdst)
.faultRead(EL1, HCR_TRAP(tid3))
- .allPrivileges().exceptUserMode().writes(0);
+ .allPrivileges().writes(0);
InitReg(MISCREG_ID_AA64MMFR0_EL1)
.reset([p,asidbits=haveLargeAsid64,parange=physAddrRange](){
AA64MMFR0 mmfr0_el1 = p.id_aa64mmfr0_el1;
@@ -3994,8 +4019,9 @@
mmfr0_el1.parange =
