subject:"\[gem5\-dev\] \[M\] Change in gem5\/gem5\[develop\]\: arch\-arm\: Implement FEAT

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_RNG

2023-05-23 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/70721?usp=email )


Change subject: arch-arm: Implement FEAT_RNG
..

arch-arm: Implement FEAT_RNG

Change-Id: I9d60d249172ef4bbaf5d9b38ef279eff344b80d8
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70721
Tested-by: kokoro 
Maintainer: Jason Lowe-Power 
Reviewed-by: Jason Lowe-Power 
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/isa.cc
M src/arch/arm/process.cc
M src/arch/arm/regs/misc.cc
M src/arch/arm/regs/misc.hh
M src/arch/arm/regs/misc_types.hh
6 files changed, 64 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index e08108f..c3b3cf6 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -88,6 +88,8 @@
 "FEAT_FLAGM",
 # Armv8.5
 "FEAT_FLAGM2",
+"FEAT_RNG",
+"FEAT_RNG_TRAP",
 # Armv9.2
 "FEAT_SME",  # Optional in Armv9.2
 # Others
@@ -204,7 +206,11 @@


 class Armv85(Armv84):
-extensions = Armv84.extensions + ["FEAT_FLAGM2"]
+extensions = Armv84.extensions + [
+"FEAT_FLAGM2",
+"FEAT_RNG",
+"FEAT_RNG_TRAP",
+]


 class Armv92(Armv85):
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 9c8e282..0212926 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -49,6 +49,7 @@
 #include "arch/arm/utility.hh"
 #include "arch/generic/decoder.hh"
 #include "base/cprintf.hh"
+#include "base/random.hh"
 #include "cpu/base.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/reg_class.hh"
@@ -596,6 +597,21 @@
   case MISCREG_HIFAR: // alias for secure IFAR
 return readMiscRegNoEffect(MISCREG_IFAR_S);

+  case MISCREG_RNDR:
+tc->setReg(cc_reg::Nz, (RegVal)0);
+tc->setReg(cc_reg::C, (RegVal)0);
+tc->setReg(cc_reg::V, (RegVal)0);
+return random_mt.random();
+  case MISCREG_RNDRRS:
+tc->setReg(cc_reg::Nz, (RegVal)0);
+tc->setReg(cc_reg::C, (RegVal)0);
+tc->setReg(cc_reg::V, (RegVal)0);
+// Note: we are not reseeding
+// The random number generator already has an hardcoded
+// seed for the sake of determinism. There is no point
+// in simulating non-determinism here
+return random_mt.random();
+
   // Generic Timer registers
   case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
   case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index b2378cc..fda9415 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -318,6 +318,7 @@

 const AA64ISAR0 isa_r0 = tc->readMiscReg(MISCREG_ID_AA64ISAR0_EL1);
 hwcap |= (isa_r0.ts >= 2) ? Arm_Flagm2 : Arm_None;
+hwcap |= (isa_r0.rndr >= 1) ? Arm_Rng : Arm_None;

 return hwcap;
 }
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 9e633c0..0e92e3d 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -1057,6 +1057,8 @@
 { MiscRegNum64(3, 2, 0, 0, 0), MISCREG_CSSELR_EL1 },
 { MiscRegNum64(3, 3, 0, 0, 1), MISCREG_CTR_EL0 },
 { MiscRegNum64(3, 3, 0, 0, 7), MISCREG_DCZID_EL0 },
+{ MiscRegNum64(3, 3, 2, 4, 0), MISCREG_RNDR },
+{ MiscRegNum64(3, 3, 2, 4, 1), MISCREG_RNDRRS },
 { MiscRegNum64(3, 3, 4, 2, 0), MISCREG_NZCV },
 { MiscRegNum64(3, 3, 4, 2, 1), MISCREG_DAIF },
 { MiscRegNum64(3, 3, 4, 2, 2), MISCREG_SVCR },
@@ -1999,6 +2001,20 @@
 }
 }

+Fault
+faultRng(const MiscRegLUTEntry ,
+ThreadContext *tc, const MiscRegOp64 )
+{
+const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+if (HaveExt(tc, ArmExtension::FEAT_RNG_TRAP) && scr.trndr) {
+return inst.generateTrap(EL3);
+} else if (!HaveExt(tc, ArmExtension::FEAT_RNG)) {
+return inst.undefined();
+} else {
+return NoFault;
+}
+}
+
 }

 MiscRegIndex
@@ -3894,6 +3910,7 @@
   isar0_el1.ts = release->has(ArmExtension::FEAT_FLAGM2) ?
   0x2 : release->has(ArmExtension::FEAT_FLAGM) ?
   0x1 : 0x0;
+  isar0_el1.rndr = release->has(ArmExtension::FEAT_RNG) ? 0x1 :  
0x0;

   return isar0_el1;
   }())
   .faultRead(EL1, HCR_TRAP(tid3))
@@ -5400,6 +5417,21 @@
 InitReg(MISCREG_MPAMSM_EL1)
 .allPrivileges().exceptUserMode();

+InitReg(MISCREG_RNDR)
+.faultRead(EL0, faultRng)
+.faultRead(EL1, faultRng)
+.faultRead(EL2, faultRng)
+.faultRead(EL3, faultRng)
+.unverifiable()
+.allPrivileges().writes(0);
+InitReg(MISCREG_RNDRRS)
+.faultRead(EL0, faultRng)
+.faultRead(EL1, faultRng)
+.faultRead(EL2, faultRng)
+.faultRead(EL3,

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_RNG

2023-05-17 Thread Giacomo Travaglini (Gerrit) via gem5-dev


Attention is currently required from: Richard Cooper.

Hello Richard Cooper,

I'd like you to do a code review.
Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/70721?usp=email

to review the following change.


Change subject: arch-arm: Implement FEAT_RNG
..

arch-arm: Implement FEAT_RNG

Change-Id: I9d60d249172ef4bbaf5d9b38ef279eff344b80d8
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Richard Cooper 
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.cc
M src/arch/arm/regs/misc.hh
M src/arch/arm/regs/misc_types.hh
5 files changed, 62 insertions(+), 1 deletion(-)



diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index e08108f..c3b3cf6 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -88,6 +88,8 @@
 "FEAT_FLAGM",
 # Armv8.5
 "FEAT_FLAGM2",
+"FEAT_RNG",
+"FEAT_RNG_TRAP",
 # Armv9.2
 "FEAT_SME",  # Optional in Armv9.2
 # Others
@@ -204,7 +206,11 @@


 class Armv85(Armv84):
-extensions = Armv84.extensions + ["FEAT_FLAGM2"]
+extensions = Armv84.extensions + [
+"FEAT_FLAGM2",
+"FEAT_RNG",
+"FEAT_RNG_TRAP",
+]


 class Armv92(Armv85):
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 9c8e282..0212926 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -49,6 +49,7 @@
 #include "arch/arm/utility.hh"
 #include "arch/generic/decoder.hh"
 #include "base/cprintf.hh"
+#include "base/random.hh"
 #include "cpu/base.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/reg_class.hh"
@@ -596,6 +597,21 @@
   case MISCREG_HIFAR: // alias for secure IFAR
 return readMiscRegNoEffect(MISCREG_IFAR_S);

+  case MISCREG_RNDR:
+tc->setReg(cc_reg::Nz, (RegVal)0);
+tc->setReg(cc_reg::C, (RegVal)0);
+tc->setReg(cc_reg::V, (RegVal)0);
+return random_mt.random();
+  case MISCREG_RNDRRS:
+tc->setReg(cc_reg::Nz, (RegVal)0);
+tc->setReg(cc_reg::C, (RegVal)0);
+tc->setReg(cc_reg::V, (RegVal)0);
+// Note: we are not reseeding
+// The random number generator already has an hardcoded
+// seed for the sake of determinism. There is no point
+// in simulating non-determinism here
+return random_mt.random();
+
   // Generic Timer registers
   case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
   case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 9e633c0..df1f6db 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -1057,6 +1057,8 @@
 { MiscRegNum64(3, 2, 0, 0, 0), MISCREG_CSSELR_EL1 },
 { MiscRegNum64(3, 3, 0, 0, 1), MISCREG_CTR_EL0 },
 { MiscRegNum64(3, 3, 0, 0, 7), MISCREG_DCZID_EL0 },
+{ MiscRegNum64(3, 3, 2, 4, 0), MISCREG_RNDR },
+{ MiscRegNum64(3, 3, 2, 4, 1), MISCREG_RNDRRS },
 { MiscRegNum64(3, 3, 4, 2, 0), MISCREG_NZCV },
 { MiscRegNum64(3, 3, 4, 2, 1), MISCREG_DAIF },
 { MiscRegNum64(3, 3, 4, 2, 2), MISCREG_SVCR },
@@ -1999,6 +2001,20 @@
 }
 }

+Fault
+faultRng(const MiscRegLUTEntry ,
+ThreadContext *tc, const MiscRegOp64 )
+{
+const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+if (HaveExt(tc, ArmExtension::FEAT_RNG_TRAP) && scr.trndr) {
+return inst.generateTrap(EL3);
+} else if (!HaveExt(tc, ArmExtension::FEAT_RNG)) {
+return inst.undefined();
+} else {
+return NoFault;
+}
+}
+
 }

 MiscRegIndex
@@ -5400,6 +5416,21 @@
 InitReg(MISCREG_MPAMSM_EL1)
 .allPrivileges().exceptUserMode();

+InitReg(MISCREG_RNDR)
+.faultRead(EL0, faultRng)
+.faultRead(EL1, faultRng)
+.faultRead(EL2, faultRng)
+.faultRead(EL3, faultRng)
+.unverifiable()
+.allPrivileges().writes(0);
+InitReg(MISCREG_RNDRRS)
+.faultRead(EL0, faultRng)
+.faultRead(EL1, faultRng)
+.faultRead(EL2, faultRng)
+.faultRead(EL3, faultRng)
+.unverifiable()
+.allPrivileges().writes(0);
+
 // Dummy registers
 InitReg(MISCREG_NOP)
   .allPrivileges();
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index c43cf74..429fcb5 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -1091,6 +1091,10 @@
 MISCREG_TPIDR2_EL0,
 MISCREG_MPAMSM_EL1,

+// FEAT_RNG
+MISCREG_RNDR,
+MISCREG_RNDRRS,
+
 // NUM_PHYS_MISCREGS specifies the number of actual physical
 // registers, not considering the following pseudo-registers
 // (dummy registers), like MISCREG_UNKNOWN, MISCREG_IMPDEF_UNIMPL.
@@ -2760,6 +2764,9 @@
 "tpidr2_el0",
 "mpamsm_el1",

+"rndr",
+"rndrrs",
+
 "num_phys_regs",

 // Dummy registers
diff --git a/src/arch/arm/regs/misc_types.hh

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_RNG

[gem5-dev] [M] Change in gem5/gem5[develop]: arch-arm: Implement FEAT_RNG

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