Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/50207 )
Change subject: arch-arm: Modify the AAPCS32 ABI implementation to use
VecElems.
..
arch-arm: Modify the AAPCS32 ABI implementation to use VecElems.
Use the VecElem register file when using the 32 bit ARM ABI. This is not
only consistent with an upcoming change which will make the 64 bit
vector registers and the 32 bit vector elements no longer act as views
into the same data, it also simplifies the implementation a little.
Change-Id: Ie8f17b764402a6331012f13b7605520512c2d5c9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50207
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/aapcs32.hh
1 file changed, 19 insertions(+), 12 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/aapcs32.hh b/src/arch/arm/aapcs32.hh
index 75c8593..beaaa7f 100644
--- a/src/arch/arm/aapcs32.hh
+++ b/src/arch/arm/aapcs32.hh
@@ -475,10 +475,14 @@
return;
}
-RegId id(VecRegClass, 0);
-auto reg = tc->readVecReg(id);
-reg.as()[0] = f;
-tc->setVecReg(id, reg);
+auto bytes = floatToBits(f);
+auto *vec_elems = static_cast();
+constexpr int chunks = sizeof(Float) / sizeof(ArmISA::VecElem);
+for (int chunk = 0; chunk < chunks; chunk++) {
+int reg = chunk / ArmISA::NumVecElemPerVecReg;
+int elem = chunk % ArmISA::NumVecElemPerVecReg;
+tc->setVecElem(RegId(VecElemClass, reg, elem),
vec_elems[chunk]);
+}
};
};
@@ -494,17 +498,20 @@
const int index = state.allocate(Float{}, 1);
-if (index >= 0) {
-constexpr int lane_per_reg = 16 / sizeof(Float);
-const int reg = index / lane_per_reg;
-const int lane = index % lane_per_reg;
+if (index < 0)
+return loadFromStack(tc, state);
-RegId id(VecRegClass, reg);
-auto val = tc->readVecReg(id);
-return val.as()[lane];
+decltype(floatToBits(Float{})) result;
+auto *vec_elems = static_cast();
+
+constexpr int chunks = sizeof(Float) / sizeof(ArmISA::VecElem);
+for (int chunk = 0; chunk < chunks; chunk++) {
+int reg = chunk / ArmISA::NumVecElemPerVecReg;
+int elem = chunk % ArmISA::NumVecElemPerVecReg;
+vec_elems[chunk] = tc->readVecElem(RegId(VecElemClass, reg,
elem));
}
-return loadFromStack(tc, state);
+return bitsToFloat(result);
}
};
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50207
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie8f17b764402a6331012f13b7605520512c2d5c9
Gerrit-Change-Number: 50207
Gerrit-PatchSet: 5
Gerrit-Owner: Gabe Black
Gerrit-Reviewer: Andreas Sandberg
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Giacomo Travaglini
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
___
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
