Ciro Santilli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/30935 )
Change subject: arch-arm: implement the ID_ISAR6_EL1 miscregister
......................................................................
arch-arm: implement the ID_ISAR6_EL1 miscregister
This register is used since the Linux kernel 5.6 aarch64 boot.
Its capability values are analogous to those present in
ID_AA64ISAR0_EL1 and ID_AA64ISAR1_EL1.
The arm architecture document clarifies that reads to this system register
location before it had defined should return 0, but we were faulting
instead:
Prior to the introduction of the features described by this register,
this register was unnamed and reserved, RES0 from EL1, EL2, and EL3.
Change-Id: I70e99536dc98925e88233fd4c6887bbcdd5d87dc
---
M src/arch/arm/ArmISA.py
M src/arch/arm/fastmodel/CortexA76/thread_context.cc
M src/arch/arm/insts/misc64.cc
M src/arch/arm/isa.cc
M src/arch/arm/kvm/arm_cpu.cc
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/utility.cc
9 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 47ba5c8..702c110 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -80,6 +80,8 @@
id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute
Register 3")
id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute
Register 4")
id_isar5 = Param.UInt32(0x10000000, "Instruction Set Attribute
Register 5")
+ # !I8MM | !BF16 | SPECRES = 0 | !SB | !FHM | DP | JSCVT
+ id_isar6 = Param.UInt32(0x00000001, "Instruction Set Attribute
Register 6")
fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register")
@@ -97,10 +99,11 @@
id_aa64dfr1_el1 = Param.UInt64(0x0000000000000000,
"AArch64 Debug Feature Register 1")
- # !CRC32 | !SHA2 | !SHA1 | !AES
+ # !FHM | !CRC32 | !SHA2 | !SHA1 | !AES
id_aa64isar0_el1 = Param.UInt64(0x0000000000000000,
"AArch64 Instruction Set Attribute Register 0")
+ # !I8MM | !BF16 | SPECRES = 0 | !SB |
# GPI = 0x0 | GPA = 0x1 | API=0x0 | FCMA | JSCVT | APA=0x1
id_aa64isar1_el1 = Param.UInt64(0x0000000001011010,
"AArch64 Instruction Set Attribute Register 1")
diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
index 4016d2b..825934b 100644
--- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
@@ -306,6 +306,7 @@
{ ArmISA::MISCREG_ID_ISAR3, "ID_ISAR3" },
{ ArmISA::MISCREG_ID_ISAR4, "ID_ISAR4" },
{ ArmISA::MISCREG_ID_ISAR5, "ID_ISAR5" },
+ { ArmISA::MISCREG_ID_ISAR6, "ID_ISAR6" },
{ ArmISA::MISCREG_CCSIDR, "CCSIDR" },
{ ArmISA::MISCREG_CLIDR, "CLIDR" },
{ ArmISA::MISCREG_AIDR, "AIDR" },
@@ -587,6 +588,7 @@
{ ArmISA::MISCREG_ID_ISAR3_EL1, "ID_ISAR3_EL1" },
{ ArmISA::MISCREG_ID_ISAR4_EL1, "ID_ISAR4_EL1" },
{ ArmISA::MISCREG_ID_ISAR5_EL1, "ID_ISAR5_EL1" },
+ { ArmISA::MISCREG_ID_ISAR6_EL1, "ID_ISAR6_EL1" },
{ ArmISA::MISCREG_MVFR0_EL1, "MVFR0_EL1" },
{ ArmISA::MISCREG_MVFR1_EL1, "MVFR1_EL1" },
{ ArmISA::MISCREG_MVFR2_EL1, "MVFR2_EL1" },
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 51e6028..e1310c4 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -250,6 +250,7 @@
case MISCREG_ID_ISAR3_EL1:
case MISCREG_ID_ISAR4_EL1:
case MISCREG_ID_ISAR5_EL1:
+ case MISCREG_ID_ISAR6_EL1:
case MISCREG_MVFR0_EL1:
case MISCREG_MVFR1_EL1:
case MISCREG_MVFR2_EL1:
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 29c5538..9cac0cf 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -338,6 +338,7 @@
miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
+ miscRegs[MISCREG_ID_ISAR6] = p->id_isar6;
miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
diff --git a/src/arch/arm/kvm/arm_cpu.cc b/src/arch/arm/kvm/arm_cpu.cc
index a8b07b9..5dd1725 100644
--- a/src/arch/arm/kvm/arm_cpu.cc
+++ b/src/arch/arm/kvm/arm_cpu.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -157,6 +157,7 @@
REG_CP32(15, 0, 0, 2, 3), // ID_ISAR3
REG_CP32(15, 0, 0, 2, 4), // ID_ISAR4
REG_CP32(15, 0, 0, 2, 5), // ID_ISAR5
+ REG_CP32(15, 0, 0, 2, 7), // ID_ISAR6
REG_CP32(15, 0, 1, 0, 0), // CSSIDR
REG_CP32(15, 0, 1, 0, 1), // CLIDR
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 3c80de4..0b74629 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -183,8 +183,9 @@
case 5:
return MISCREG_ID_ISAR5;
case 6:
- case 7:
return MISCREG_RAZ; // read as zero
+ case 7:
+ return MISCREG_ID_ISAR6;
}
break;
default:
@@ -1732,6 +1733,8 @@
return MISCREG_ID_ISAR4_EL1;
case 5:
return MISCREG_ID_ISAR5_EL1;
+ case 7:
+ return MISCREG_ID_ISAR6_EL1;
}
break;
case 3:
@@ -3253,6 +3256,8 @@
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_ISAR5)
.allPrivileges().exceptUserMode().writes(0);
+ InitReg(MISCREG_ID_ISAR6)
+ .allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_CCSIDR)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_CLIDR)
@@ -4047,6 +4052,9 @@
InitReg(MISCREG_ID_ISAR5_EL1)
.allPrivileges().exceptUserMode().writes(0)
.mapsTo(MISCREG_ID_ISAR5);
+ InitReg(MISCREG_ID_ISAR6_EL1)
+ .allPrivileges().exceptUserMode().writes(0)
+ .mapsTo(MISCREG_ID_ISAR6);
InitReg(MISCREG_MVFR0_EL1)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_MVFR1_EL1)
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 550b51c..79a4142 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -160,6 +160,7 @@
MISCREG_ID_ISAR3,
MISCREG_ID_ISAR4,
MISCREG_ID_ISAR5,
+ MISCREG_ID_ISAR6,
MISCREG_CCSIDR,
MISCREG_CLIDR,
MISCREG_AIDR,
@@ -444,6 +445,7 @@
MISCREG_ID_ISAR3_EL1,
MISCREG_ID_ISAR4_EL1,
MISCREG_ID_ISAR5_EL1,
+ MISCREG_ID_ISAR6_EL1,
MISCREG_MVFR0_EL1,
MISCREG_MVFR1_EL1,
MISCREG_MVFR2_EL1,
@@ -1137,6 +1139,7 @@
"id_isar3",
"id_isar4",
"id_isar5",
+ "id_isar6",
"ccsidr",
"clidr",
"aidr",
@@ -1419,6 +1422,7 @@
"id_isar3_el1",
"id_isar4_el1",
"id_isar5_el1",
+ "id_isar6_el1",
"mvfr0_el1",
"mvfr1_el1",
"mvfr2_el1",
diff --git a/src/arch/arm/tracers/tarmac_parser.cc
b/src/arch/arm/tracers/tarmac_parser.cc
index 96678b0..739ad51 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011,2017-2019 ARM Limited
+ * Copyright (c) 2011,2017-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -148,6 +148,7 @@
{ "id_isar3", MISCREG_ID_ISAR3 },
{ "id_isar4", MISCREG_ID_ISAR4 },
{ "id_isar5", MISCREG_ID_ISAR5 },
+ { "id_isar6", MISCREG_ID_ISAR6 },
{ "ccsidr", MISCREG_CCSIDR },
{ "clidr", MISCREG_CLIDR },
{ "aidr", MISCREG_AIDR },
@@ -402,6 +403,7 @@
{ "id_isar3_el1", MISCREG_ID_ISAR3_EL1 },
{ "id_isar4_el1", MISCREG_ID_ISAR4_EL1 },
{ "id_isar5_el1", MISCREG_ID_ISAR5_EL1 },
+ { "id_isar6_el1", MISCREG_ID_ISAR6_EL1 },
{ "mvfr0_el1", MISCREG_MVFR0_EL1 },
{ "mvfr1_el1", MISCREG_MVFR1_EL1 },
{ "mvfr2_el1", MISCREG_MVFR2_EL1 },
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 9947bdd..167ee35 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -585,6 +585,7 @@
case MISCREG_ID_ISAR3:
case MISCREG_ID_ISAR4:
case MISCREG_ID_ISAR5:
+ case MISCREG_ID_ISAR6:
trapToHype = hcr.tid3;
break;
case MISCREG_DCISW:
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I70e99536dc98925e88233fd4c6887bbcdd5d87dc
Gerrit-Change-Number: 30935
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli <ciro.santi...@arm.com>
Gerrit-MessageType: newchange
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