[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add fields for VA form instructions

2021-06-28 Thread Boris Shingarov (Gerrit) via gem5-dev
Boris Shingarov has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40904 )


Change subject: arch-power: Add fields for VA form instructions
..

arch-power: Add fields for VA form instructions

This introduces the extended opcode field for VA form
instructions and the RC field that specifes a GPR to
be used as a register operand.

Change-Id: Ibc63b7392cb552613c755463fb34f2ee2362b2b6
Signed-off-by: Sandipan Das 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40904
Reviewed-by: Boris Shingarov 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M src/arch/power/isa/bitfields.isa
M src/arch/power/isa/operands.isa
2 files changed, 4 insertions(+), 1 deletion(-)

Approvals:
  Boris Shingarov: Looks good to me, approved
  Jason Lowe-Power: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/power/isa/bitfields.isa  
b/src/arch/power/isa/bitfields.isa

index 84a3a2c..8783081 100644
--- a/src/arch/power/isa/bitfields.isa
+++ b/src/arch/power/isa/bitfields.isa
@@ -38,6 +38,7 @@
 def bitfield A_XO  <5:1>;
 def bitfield DS_XO <1:0>;
 def bitfield DX_XO <5:1>;
+def bitfield VA_XO <5:0>;
 def bitfield X_XO  <10:1>;
 def bitfield XFL_XO<10:1>;
 def bitfield XFX_XO<10:1>;
@@ -47,6 +48,7 @@
 // Register fields
 def bitfield RA<20:16>;
 def bitfield RB<15:11>;
+def bitfield RC<10:6>;
 def bitfield RS<25:21>;
 def bitfield RT<25:21>;
 def bitfield FRA   <20:16>;
diff --git a/src/arch/power/isa/operands.isa  
b/src/arch/power/isa/operands.isa

index 8cb39eb..7d85749 100644
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -44,7 +44,8 @@
 'Rs': ('IntReg', 'ud', 'RS', 'IsInteger', 1),
 'Ra': ('IntReg', 'ud', 'RA', 'IsInteger', 2),
 'Rb': ('IntReg', 'ud', 'RB', 'IsInteger', 3),
-'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 4),
+'Rc': ('IntReg', 'ud', 'RC', 'IsInteger', 4),
+'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 5),

 # General Purpose Floating Point Reg Operands
 'Fa': ('FloatReg', 'df', 'FRA', 'IsFloating', 1),



6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibc63b7392cb552613c755463fb34f2ee2362b2b6
Gerrit-Change-Number: 40904
Gerrit-PatchSet: 8
Gerrit-Owner: Sandipan Das 
Gerrit-Reviewer: Boris Shingarov 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-power: Add fields for VA form instructions

2021-02-07 Thread Sandipan Das (Gerrit) via gem5-dev
Sandipan Das has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40904 )



Change subject: arch-power: Add fields for VA form instructions
..

arch-power: Add fields for VA form instructions

This introduces the extended opcode field for VA form
instructions and the RC field that specifes a GPR to
be used as a register operand.

Change-Id: Ibc63b7392cb552613c755463fb34f2ee2362b2b6
Signed-off-by: Sandipan Das 
---
M src/arch/power/isa/bitfields.isa
M src/arch/power/isa/operands.isa
2 files changed, 4 insertions(+), 1 deletion(-)



diff --git a/src/arch/power/isa/bitfields.isa  
b/src/arch/power/isa/bitfields.isa

index 84a3a2c..8783081 100644
--- a/src/arch/power/isa/bitfields.isa
+++ b/src/arch/power/isa/bitfields.isa
@@ -38,6 +38,7 @@
 def bitfield A_XO  <5:1>;
 def bitfield DS_XO <1:0>;
 def bitfield DX_XO <5:1>;
+def bitfield VA_XO <5:0>;
 def bitfield X_XO  <10:1>;
 def bitfield XFL_XO<10:1>;
 def bitfield XFX_XO<10:1>;
@@ -47,6 +48,7 @@
 // Register fields
 def bitfield RA<20:16>;
 def bitfield RB<15:11>;
+def bitfield RC<10:6>;
 def bitfield RS<25:21>;
 def bitfield RT<25:21>;
 def bitfield FRA   <20:16>;
diff --git a/src/arch/power/isa/operands.isa  
b/src/arch/power/isa/operands.isa

index 017469a..bdd5948 100644
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -44,7 +44,8 @@
 'Rs': ('IntReg', 'ud', 'RS', 'IsInteger', 1),
 'Ra': ('IntReg', 'ud', 'RA', 'IsInteger', 2),
 'Rb': ('IntReg', 'ud', 'RB', 'IsInteger', 3),
-'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 4),
+'Rc': ('IntReg', 'ud', 'RC', 'IsInteger', 4),
+'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 5),

 # General Purpose Floating Point Reg Operands
 'Fa': ('FloatReg', 'df', 'FRA', 'IsFloating', 1),

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40904
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibc63b7392cb552613c755463fb34f2ee2362b2b6
Gerrit-Change-Number: 40904
Gerrit-PatchSet: 1
Gerrit-Owner: Sandipan Das 
Gerrit-MessageType: newchange
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