[gem5-dev] Change in gem5/gem5[develop]: arch-power: Refactor CR field generation
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/42943 )
Change subject: arch-power: Refactor CR field generation
..
arch-power: Refactor CR field generation
This splits the existing makeCRField utility into signed
and unsigned variants to help callers avoid confusion.
The CR bit union is also used to clean up the underlying
bit setting logic.
Change-Id: I2aa6ec0666d2bc5096eb6c775cc47f2a5a0621ee
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42943
Tested-by: kokoro
Reviewed-by: Gabe Black
Maintainer: Bobby R. Bruce
---
M src/arch/power/insts/integer.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/integer.isa
3 files changed, 21 insertions(+), 19 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/integer.hh
b/src/arch/power/insts/integer.hh
index 1c9b1cc..1771fea 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -65,28 +65,30 @@
/* Compute the CR (condition register) field using signed comparison */
inline uint32_t
-makeCRField(int32_t a, int32_t b, uint32_t xerSO) const
+makeCRFieldSigned(int64_t a, int64_t b, bool so) const
{
-uint32_t c = xerSO;
+Cr cr = 0;
-/* We've pre-shifted the immediate values here */
-if (a < b) { c += 0x8; }
-else if (a > b) { c += 0x4; }
-else{ c += 0x2; }
-return c;
+if (a < b) { cr.cr0.lt = 1; }
+else if (a > b) { cr.cr0.gt = 1; }
+else{ cr.cr0.eq = 1; }
+if (so) { cr.cr0.so = 1; }
+
+return cr.cr0;
}
/* Compute the CR (condition register) field using unsigned comparison
*/
inline uint32_t
-makeCRField(uint32_t a, uint32_t b, uint32_t xerSO) const
+makeCRFieldUnsigned(uint64_t a, uint64_t b, bool so) const
{
-uint32_t c = xerSO;
+Cr cr = 0;
-/* We've pre-shifted the immediate values here */
-if (a < b) { c += 0x8; }
-else if (a > b) { c += 0x4; }
-else{ c += 0x2; }
-return c;
+if (a < b) { cr.cr0.lt = 1; }
+else if (a > b) { cr.cr0.gt = 1; }
+else{ cr.cr0.eq = 1; }
+if (so) { cr.cr0.so = 1; }
+
+return cr.cr0;
}
std::string generateDisassembly(
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index f32861b..7f22d8c 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -39,12 +39,12 @@
format IntImmOp {
10: cmpli({{
Xer xer = XER;
-uint32_t cr = makeCRField(Ra, (uint32_t)uimm, xer.so);
+uint32_t cr = makeCRFieldUnsigned(Ra_uw, uimm, xer.so);
CR = insertCRField(CR, BF, cr);
}});
11: cmpi({{
Xer xer = XER;
-uint32_t cr = makeCRField(Ra_sw, (int32_t)imm, xer.so);
+uint32_t cr = makeCRFieldSigned(Ra_sw, imm, xer.so);
CR = insertCRField(CR, BF, cr);
}});
}
@@ -250,12 +250,12 @@
format IntOp {
0: cmp({{
Xer xer = XER;
-uint32_t cr = makeCRField(Ra_sw, Rb_sw, xer.so);
+uint32_t cr = makeCRFieldSigned(Ra_sw, Rb_sw, xer.so);
CR = insertCRField(CR, BF, cr);
}});
32: cmpl({{
Xer xer = XER;
-uint32_t cr = makeCRField(Ra, Rb, xer.so);
+uint32_t cr = makeCRFieldUnsigned(Ra_uw, Rb_uw, xer.so);
CR = insertCRField(CR, BF, cr);
}});
144: mtcrf({{
diff --git a/src/arch/power/isa/formats/integer.isa
b/src/arch/power/isa/formats/integer.isa
index 50badce..0ed0bf02 100644
--- a/src/arch/power/isa/formats/integer.isa
+++ b/src/arch/power/isa/formats/integer.isa
@@ -77,7 +77,7 @@
computeCR0Code = '''
Cr cr = CR;
-cr.cr0 = makeCRField((int32_t)%(result)s, (int32_t)0, xer.so);
+cr.cr0 = makeCRFieldSigned(%(result)s, 0, xer.so);
CR = cr;
'''
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/42943
To unsubscribe, or for help writing mail filters, visit
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2aa6ec0666d2bc5096eb6c775cc47f2a5a0621ee
Gerrit-Change-Number: 42943
Gerrit-PatchSet: 5
Gerrit-Owner: Sandipan Das
Gerrit-Reviewer: Bobby R. Bruce
Gerrit-Reviewer: Boris Shingarov
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Refactor CR field generation
Sandipan Das has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/42943 )
Change subject: arch-power: Refactor CR field generation
..
arch-power: Refactor CR field generation
This splits the existing makeCRField utility into signed
and unsigned variants to help callers avoid confusion.
The CR bit union is also used to clean up the underlying
bit setting logic.
Change-Id: I2aa6ec0666d2bc5096eb6c775cc47f2a5a0621ee
Signed-off-by: Sandipan Das
---
M src/arch/power/insts/integer.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/integer.isa
3 files changed, 21 insertions(+), 19 deletions(-)
diff --git a/src/arch/power/insts/integer.hh
b/src/arch/power/insts/integer.hh
index 1c9b1cc..1771fea 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -65,28 +65,30 @@
/* Compute the CR (condition register) field using signed comparison */
inline uint32_t
-makeCRField(int32_t a, int32_t b, uint32_t xerSO) const
+makeCRFieldSigned(int64_t a, int64_t b, bool so) const
{
-uint32_t c = xerSO;
+Cr cr = 0;
-/* We've pre-shifted the immediate values here */
-if (a < b) { c += 0x8; }
-else if (a > b) { c += 0x4; }
-else{ c += 0x2; }
-return c;
+if (a < b) { cr.cr0.lt = 1; }
+else if (a > b) { cr.cr0.gt = 1; }
+else{ cr.cr0.eq = 1; }
+if (so) { cr.cr0.so = 1; }
+
+return cr.cr0;
}
/* Compute the CR (condition register) field using unsigned comparison
*/
inline uint32_t
-makeCRField(uint32_t a, uint32_t b, uint32_t xerSO) const
+makeCRFieldUnsigned(uint64_t a, uint64_t b, bool so) const
{
-uint32_t c = xerSO;
+Cr cr = 0;
-/* We've pre-shifted the immediate values here */
-if (a < b) { c += 0x8; }
-else if (a > b) { c += 0x4; }
-else{ c += 0x2; }
-return c;
+if (a < b) { cr.cr0.lt = 1; }
+else if (a > b) { cr.cr0.gt = 1; }
+else{ cr.cr0.eq = 1; }
+if (so) { cr.cr0.so = 1; }
+
+return cr.cr0;
}
std::string generateDisassembly(
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index f32861b..7f22d8c 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -39,12 +39,12 @@
format IntImmOp {
10: cmpli({{
Xer xer = XER;
-uint32_t cr = makeCRField(Ra, (uint32_t)uimm, xer.so);
+uint32_t cr = makeCRFieldUnsigned(Ra_uw, uimm, xer.so);
CR = insertCRField(CR, BF, cr);
}});
11: cmpi({{
Xer xer = XER;
-uint32_t cr = makeCRField(Ra_sw, (int32_t)imm, xer.so);
+uint32_t cr = makeCRFieldSigned(Ra_sw, imm, xer.so);
CR = insertCRField(CR, BF, cr);
}});
}
@@ -250,12 +250,12 @@
format IntOp {
0: cmp({{
Xer xer = XER;
-uint32_t cr = makeCRField(Ra_sw, Rb_sw, xer.so);
+uint32_t cr = makeCRFieldSigned(Ra_sw, Rb_sw, xer.so);
CR = insertCRField(CR, BF, cr);
}});
32: cmpl({{
Xer xer = XER;
-uint32_t cr = makeCRField(Ra, Rb, xer.so);
+uint32_t cr = makeCRFieldUnsigned(Ra_uw, Rb_uw, xer.so);
CR = insertCRField(CR, BF, cr);
}});
144: mtcrf({{
diff --git a/src/arch/power/isa/formats/integer.isa
b/src/arch/power/isa/formats/integer.isa
index 50badce..834cd50 100644
--- a/src/arch/power/isa/formats/integer.isa
+++ b/src/arch/power/isa/formats/integer.isa
@@ -77,7 +77,7 @@
computeCR0Code = '''
Cr cr = CR;
-cr.cr0 = makeCRField((int32_t)%(result)s, (int32_t)0, xer.so);
+cr.cr0 = makeCRFieldSigned((int32_t)%(result)s, (int32_t)0, xer.so);
CR = cr;
'''
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/42943
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2aa6ec0666d2bc5096eb6c775cc47f2a5a0621ee
Gerrit-Change-Number: 42943
Gerrit-PatchSet: 1
Gerrit-Owner: Sandipan Das
Gerrit-MessageType: newchange
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